2009-04-23 03:08:17 +08:00
|
|
|
/*
|
|
|
|
* arch/arm/mach-orion5x/include/mach/bridge-regs.h
|
|
|
|
*
|
|
|
|
* Orion CPU Bridge Registers
|
|
|
|
*
|
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __ASM_ARCH_BRIDGE_REGS_H
|
|
|
|
#define __ASM_ARCH_BRIDGE_REGS_H
|
|
|
|
|
|
|
|
#include <mach/orion5x.h>
|
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
|
2009-04-23 03:08:17 +08:00
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
|
2009-04-23 03:08:17 +08:00
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
|
2014-02-11 07:00:25 +08:00
|
|
|
#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
|
2009-04-23 03:08:17 +08:00
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
|
2009-04-23 03:08:17 +08:00
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
|
2010-10-15 22:50:26 +08:00
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
|
2009-04-23 03:08:17 +08:00
|
|
|
|
|
|
|
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
|
2009-04-23 03:08:17 +08:00
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
|
2009-04-23 03:08:17 +08:00
|
|
|
|
2012-09-11 20:27:17 +08:00
|
|
|
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
|
|
|
|
#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
|
2009-04-23 03:08:17 +08:00
|
|
|
#endif
|