317 lines
7.7 KiB
C
317 lines
7.7 KiB
C
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/*
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* Copyright(c) 2015 EZchip Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#ifndef _NPS_ENET_H
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#define _NPS_ENET_H
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/* default values */
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#define NPS_ENET_NAPI_POLL_WEIGHT 0x2
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#define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
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#define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
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#define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
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#define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
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#define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
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#define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
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#define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
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#define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
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#define NPS_ENET_ENABLE 1
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#define NPS_ENET_DISABLE 0
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/* register definitions */
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#define NPS_ENET_REG_TX_CTL 0x800
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#define NPS_ENET_REG_TX_BUF 0x808
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#define NPS_ENET_REG_RX_CTL 0x810
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#define NPS_ENET_REG_RX_BUF 0x818
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#define NPS_ENET_REG_BUF_INT_ENABLE 0x8C0
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#define NPS_ENET_REG_GE_MAC_CFG_0 0x1000
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#define NPS_ENET_REG_GE_MAC_CFG_1 0x1004
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#define NPS_ENET_REG_GE_MAC_CFG_2 0x1008
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#define NPS_ENET_REG_GE_MAC_CFG_3 0x100C
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#define NPS_ENET_REG_GE_RST 0x1400
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#define NPS_ENET_REG_PHASE_FIFO_CTL 0x1404
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/* Tx control register */
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struct nps_enet_tx_ctl {
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union {
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/* ct: SW sets to indicate frame ready in Tx buffer for
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* transmission. HW resets to when transmission done
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* et: Transmit error
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* nt: Length in bytes of Tx frame loaded to Tx buffer
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*/
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struct {
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u32
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__reserved_1:16,
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ct:1,
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et:1,
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__reserved_2:3,
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nt:11;
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};
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u32 value;
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};
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};
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/* Rx control register */
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struct nps_enet_rx_ctl {
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union {
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/* cr: HW sets to indicate frame ready in Rx buffer.
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* SW resets to indicate host read received frame
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* and new frames can be written to Rx buffer
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* er: Rx error indication
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* crc: Rx CRC error indication
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* nr: Length in bytes of Rx frame loaded by MAC to Rx buffer
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*/
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struct {
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u32
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__reserved_1:16,
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cr:1,
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er:1,
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crc:1,
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__reserved_2:2,
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nr:11;
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};
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u32 value;
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};
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};
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/* Interrupt enable for data buffer events register */
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struct nps_enet_buf_int_enable {
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union {
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/* tx_done: Interrupt generation in the case when new frame
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* is ready in Rx buffer
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* rx_rdy: Interrupt generation in the case when current frame
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* was read from TX buffer
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*/
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struct {
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u32
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__reserved:30,
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tx_done:1,
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rx_rdy:1;
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};
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u32 value;
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};
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};
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/* Gbps Eth MAC Configuration 0 register */
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struct nps_enet_ge_mac_cfg_0 {
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union {
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/* tx_pr_len: Transmit preamble length in bytes
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* tx_ifg_nib: Tx idle pattern
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* nib_mode: Nibble (4-bit) Mode
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* rx_pr_check_en: Receive preamble Check Enable
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* tx_ifg: Transmit inter-Frame Gap
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* rx_ifg: Receive inter-Frame Gap
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* tx_fc_retr: Transmit Flow Control Retransmit Mode
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* rx_length_check_en: Receive Length Check Enable
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* rx_crc_ignore: Results of the CRC check are ignored
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* rx_crc_strip: MAC strips the CRC from received frames
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* rx_fc_en: Receive Flow Control Enable
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* tx_crc_en: Transmit CRC Enabled
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* tx_pad_en: Transmit Padding Enable
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* tx_cf_en: Transmit Flow Control Enable
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* tx_en: Transmit Enable
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* rx_en: Receive Enable
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*/
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struct {
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u32
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tx_pr_len:4,
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tx_ifg_nib:4,
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nib_mode:1,
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rx_pr_check_en:1,
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tx_ifg:6,
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rx_ifg:4,
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tx_fc_retr:3,
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rx_length_check_en:1,
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rx_crc_ignore:1,
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rx_crc_strip:1,
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rx_fc_en:1,
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tx_crc_en:1,
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tx_pad_en:1,
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tx_fc_en:1,
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tx_en:1,
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rx_en:1;
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};
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u32 value;
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};
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};
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/* Gbps Eth MAC Configuration 1 register */
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struct nps_enet_ge_mac_cfg_1 {
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union {
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/* octet_3: MAC address octet 3
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* octet_2: MAC address octet 2
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* octet_1: MAC address octet 1
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* octet_0: MAC address octet 0
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*/
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struct {
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u32
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octet_3:8,
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octet_2:8,
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octet_1:8,
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octet_0:8;
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};
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u32 value;
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};
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};
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/* Gbps Eth MAC Configuration 2 register */
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struct nps_enet_ge_mac_cfg_2 {
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union {
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/* transmit_flush_en: MAC flush enable
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* stat_en: RMON statistics interface enable
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* disc_da: Discard frames with DA different
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* from MAC address
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* disc_bc: Discard broadcast frames
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* disc_mc: Discard multicast frames
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* octet_5: MAC address octet 5
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* octet_4: MAC address octet 4
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*/
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struct {
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u32
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transmit_flush_en:1,
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__reserved_1:5,
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stat_en:2,
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__reserved_2:1,
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disc_da:1,
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disc_bc:1,
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disc_mc:1,
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__reserved_3:4,
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octet_5:8,
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octet_4:8;
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};
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u32 value;
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};
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};
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/* Gbps Eth MAC Configuration 3 register */
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struct nps_enet_ge_mac_cfg_3 {
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union {
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/* ext_oob_cbfc_sel: Selects one of the 4 profiles for
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* extended OOB in-flow-control indication
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* max_len: Maximum receive frame length in bytes
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* tx_cbfc_en: Enable transmission of class-based
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* flow control packets
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* rx_ifg_th: Threshold for IFG status reporting via OOB
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* cf_timeout: Configurable time to decrement FC counters
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* cf_drop: Drop control frames
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* redirect_cbfc_sel: Selects one of CBFC redirect profiles
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* rx_cbfc_redir_en: Enable Rx class-based flow
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* control redirect
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* rx_cbfc_en: Enable Rx class-based flow control
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* tm_hd_mode: TM header mode
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*/
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struct {
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u32
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ext_oob_cbfc_sel:2,
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max_len:14,
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tx_cbfc_en:1,
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rx_ifg_th:5,
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cf_timeout:4,
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cf_drop:1,
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redirect_cbfc_sel:2,
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rx_cbfc_redir_en:1,
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rx_cbfc_en:1,
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tm_hd_mode:1;
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};
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u32 value;
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};
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};
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/* GE MAC, PCS reset control register */
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struct nps_enet_ge_rst {
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union {
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/* gmac_0: GE MAC reset
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* spcs_0: SGMII PCS reset
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*/
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struct {
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u32
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__reserved_1:23,
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gmac_0:1,
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__reserved_2:7,
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spcs_0:1;
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};
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u32 value;
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};
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};
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/* Tx phase sync FIFO control register */
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struct nps_enet_phase_fifo_ctl {
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union {
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/* init: initialize serdes TX phase sync FIFO pointers
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* rst: reset serdes TX phase sync FIFO
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*/
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struct {
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u32
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__reserved:30,
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init:1,
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rst:1;
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};
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u32 value;
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};
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};
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/**
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* struct nps_enet_priv - Storage of ENET's private information.
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* @regs_base: Base address of ENET memory-mapped control registers.
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* @irq: For RX/TX IRQ number.
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* @tx_packet_sent: SW indication if frame is being sent.
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* @tx_skb: socket buffer of sent frame.
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* @napi: Structure for NAPI.
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*/
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struct nps_enet_priv {
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void __iomem *regs_base;
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s32 irq;
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bool tx_packet_sent;
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struct sk_buff *tx_skb;
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struct napi_struct napi;
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struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2;
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struct nps_enet_ge_mac_cfg_3 ge_mac_cfg_3;
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};
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/**
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* nps_reg_set - Sets ENET register with provided value.
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* @priv: Pointer to EZchip ENET private data structure.
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* @reg: Register offset from base address.
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* @value: Value to set in register.
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*/
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static inline void nps_enet_reg_set(struct nps_enet_priv *priv,
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s32 reg, s32 value)
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{
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iowrite32be(value, priv->regs_base + reg);
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}
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/**
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* nps_reg_get - Gets value of specified ENET register.
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* @priv: Pointer to EZchip ENET private data structure.
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* @reg: Register offset from base address.
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*
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* returns: Value of requested register.
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*/
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static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg)
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{
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return ioread32be(priv->regs_base + reg);
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}
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#endif /* _NPS_ENET_H */
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