2011-11-18 01:41:28 +08:00
|
|
|
/*
|
|
|
|
|
* reset AT91SAM9G45 as per errata
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
|
|
|
|
|
*
|
|
|
|
|
* unless the SDRAM is cleanly shutdown before we hit the
|
|
|
|
|
* reset register it can be left driving the data bus and
|
|
|
|
|
* killing the chance of a subsequent boot from NAND
|
|
|
|
|
*
|
|
|
|
|
* GPLv2 Only
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <linux/linkage.h>
|
|
|
|
|
#include <mach/hardware.h>
|
2012-02-13 12:58:53 +08:00
|
|
|
#include <mach/at91_ramc.h>
|
2012-10-30 08:11:24 +08:00
|
|
|
#include "at91_rstc.h"
|
2011-11-18 01:41:28 +08:00
|
|
|
.arm
|
|
|
|
|
|
|
|
|
|
.globl at91sam9g45_restart
|
|
|
|
|
|
|
|
|
|
at91sam9g45_restart:
|
2012-02-13 12:58:53 +08:00
|
|
|
ldr r5, =at91_ramc_base @ preload constants
|
|
|
|
|
ldr r0, [r5]
|
|
|
|
|
ldr r4, =at91_rstc_base
|
|
|
|
|
ldr r1, [r4]
|
2011-11-18 01:41:28 +08:00
|
|
|
|
|
|
|
|
mov r2, #1
|
|
|
|
|
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
|
|
|
|
|
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
|
|
|
|
|
|
|
|
|
|
.balign 32 @ align to cache line
|
|
|
|
|
|
|
|
|
|
str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
|
|
|
|
|
str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
|
|
|
|
|
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
|
|
|
|
|
|
|
|
|
b .
|
