2010-04-01 23:28:22 +08:00
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/*
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* This file is part of the Chelsio T4 Ethernet driver for Linux.
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*
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* Copyright (c) 2010 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __T4_REGS_H
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#define __T4_REGS_H
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#define MYPF_BASE 0x1b000
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#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
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#define PF0_BASE 0x1e000
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#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
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#define PF_STRIDE 0x400
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#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
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#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
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#define MYPORT_BASE 0x1c000
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#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
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#define PORT0_BASE 0x20000
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#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
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#define PORT_STRIDE 0x2000
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#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
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#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
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#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
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#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
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#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
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#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
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#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
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#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
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#define SGE_PF_KDOORBELL 0x0
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#define QID_MASK 0xffff8000U
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#define QID_SHIFT 15
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#define QID(x) ((x) << QID_SHIFT)
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2012-11-16 01:11:17 +08:00
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#define DBPRIO(x) ((x) << 14)
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2013-03-14 13:08:47 +08:00
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#define DBTYPE(x) ((x) << 13)
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2010-04-01 23:28:22 +08:00
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#define PIDX_MASK 0x00003fffU
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#define PIDX_SHIFT 0
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#define PIDX(x) ((x) << PIDX_SHIFT)
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2013-03-14 13:08:47 +08:00
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#define S_PIDX_T5 0
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#define M_PIDX_T5 0x1fffU
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#define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
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2010-04-01 23:28:22 +08:00
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#define SGE_PF_GTS 0x4
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#define INGRESSQID_MASK 0xffff0000U
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#define INGRESSQID_SHIFT 16
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#define INGRESSQID(x) ((x) << INGRESSQID_SHIFT)
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#define TIMERREG_MASK 0x0000e000U
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#define TIMERREG_SHIFT 13
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#define TIMERREG(x) ((x) << TIMERREG_SHIFT)
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#define SEINTARM_MASK 0x00001000U
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#define SEINTARM_SHIFT 12
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#define SEINTARM(x) ((x) << SEINTARM_SHIFT)
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#define CIDXINC_MASK 0x00000fffU
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#define CIDXINC_SHIFT 0
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#define CIDXINC(x) ((x) << CIDXINC_SHIFT)
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2012-09-26 10:39:38 +08:00
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#define X_RXPKTCPLMODE_SPLIT 1
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#define X_INGPADBOUNDARY_SHIFT 5
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2010-04-01 23:28:22 +08:00
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#define SGE_CONTROL 0x1008
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#define DCASYSTYPE 0x00080000U
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2012-09-26 10:39:38 +08:00
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#define RXPKTCPLMODE_MASK 0x00040000U
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#define RXPKTCPLMODE_SHIFT 18
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#define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT)
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#define EGRSTATUSPAGESIZE_MASK 0x00020000U
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#define EGRSTATUSPAGESIZE_SHIFT 17
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#define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT)
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2010-04-01 23:28:22 +08:00
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#define PKTSHIFT_MASK 0x00001c00U
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#define PKTSHIFT_SHIFT 10
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#define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT)
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2010-06-25 20:11:05 +08:00
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#define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
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2010-04-01 23:28:22 +08:00
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#define INGPCIEBOUNDARY_MASK 0x00000380U
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#define INGPCIEBOUNDARY_SHIFT 7
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#define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT)
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#define INGPADBOUNDARY_MASK 0x00000070U
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#define INGPADBOUNDARY_SHIFT 4
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#define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT)
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2010-06-25 20:11:05 +08:00
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#define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \
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>> INGPADBOUNDARY_SHIFT)
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2010-04-01 23:28:22 +08:00
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#define EGRPCIEBOUNDARY_MASK 0x0000000eU
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#define EGRPCIEBOUNDARY_SHIFT 1
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#define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT)
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#define GLOBALENABLE 0x00000001U
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#define SGE_HOST_PAGE_SIZE 0x100c
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2012-09-26 10:39:39 +08:00
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#define HOSTPAGESIZEPF7_MASK 0x0000000fU
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#define HOSTPAGESIZEPF7_SHIFT 28
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#define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT)
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#define HOSTPAGESIZEPF6_MASK 0x0000000fU
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#define HOSTPAGESIZEPF6_SHIFT 24
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#define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT)
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#define HOSTPAGESIZEPF5_MASK 0x0000000fU
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#define HOSTPAGESIZEPF5_SHIFT 20
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#define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT)
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#define HOSTPAGESIZEPF4_MASK 0x0000000fU
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#define HOSTPAGESIZEPF4_SHIFT 16
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#define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT)
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#define HOSTPAGESIZEPF3_MASK 0x0000000fU
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#define HOSTPAGESIZEPF3_SHIFT 12
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#define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT)
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#define HOSTPAGESIZEPF2_MASK 0x0000000fU
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#define HOSTPAGESIZEPF2_SHIFT 8
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#define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT)
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#define HOSTPAGESIZEPF1_MASK 0x0000000fU
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#define HOSTPAGESIZEPF1_SHIFT 4
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#define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT)
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2010-04-01 23:28:22 +08:00
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#define HOSTPAGESIZEPF0_MASK 0x0000000fU
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#define HOSTPAGESIZEPF0_SHIFT 0
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#define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT)
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#define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
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#define QUEUESPERPAGEPF0_MASK 0x0000000fU
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#define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
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2013-03-14 13:08:47 +08:00
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#define QUEUESPERPAGEPF1 4
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2010-04-01 23:28:22 +08:00
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#define SGE_INT_CAUSE1 0x1024
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#define SGE_INT_CAUSE2 0x1030
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#define SGE_INT_CAUSE3 0x103c
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#define ERR_FLM_DBP 0x80000000U
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#define ERR_FLM_IDMA1 0x40000000U
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#define ERR_FLM_IDMA0 0x20000000U
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#define ERR_FLM_HINT 0x10000000U
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#define ERR_PCIE_ERROR3 0x08000000U
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#define ERR_PCIE_ERROR2 0x04000000U
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#define ERR_PCIE_ERROR1 0x02000000U
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#define ERR_PCIE_ERROR0 0x01000000U
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#define ERR_TIMER_ABOVE_MAX_QID 0x00800000U
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#define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U
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#define ERR_INVALID_CIDX_INC 0x00200000U
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#define ERR_ITP_TIME_PAUSED 0x00100000U
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#define ERR_CPL_OPCODE_0 0x00080000U
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#define ERR_DROPPED_DB 0x00040000U
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#define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
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#define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
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#define ERR_BAD_DB_PIDX3 0x00008000U
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#define ERR_BAD_DB_PIDX2 0x00004000U
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#define ERR_BAD_DB_PIDX1 0x00002000U
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#define ERR_BAD_DB_PIDX0 0x00001000U
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#define ERR_ING_PCIE_CHAN 0x00000800U
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#define ERR_ING_CTXT_PRIO 0x00000400U
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#define ERR_EGR_CTXT_PRIO 0x00000200U
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#define DBFIFO_HP_INT 0x00000100U
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#define DBFIFO_LP_INT 0x00000080U
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#define REG_ADDRESS_ERR 0x00000040U
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#define INGRESS_SIZE_ERR 0x00000020U
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#define EGRESS_SIZE_ERR 0x00000010U
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#define ERR_INV_CTXT3 0x00000008U
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#define ERR_INV_CTXT2 0x00000004U
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#define ERR_INV_CTXT1 0x00000002U
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#define ERR_INV_CTXT0 0x00000001U
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#define SGE_INT_ENABLE3 0x1040
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#define SGE_FL_BUFFER_SIZE0 0x1044
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#define SGE_FL_BUFFER_SIZE1 0x1048
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2012-09-26 10:39:39 +08:00
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#define SGE_FL_BUFFER_SIZE2 0x104c
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#define SGE_FL_BUFFER_SIZE3 0x1050
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2012-11-16 01:11:17 +08:00
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#define SGE_FL_BUFFER_SIZE4 0x1054
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#define SGE_FL_BUFFER_SIZE5 0x1058
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#define SGE_FL_BUFFER_SIZE6 0x105c
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#define SGE_FL_BUFFER_SIZE7 0x1060
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#define SGE_FL_BUFFER_SIZE8 0x1064
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2010-04-01 23:28:22 +08:00
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#define SGE_INGRESS_RX_THRESHOLD 0x10a0
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#define THRESHOLD_0_MASK 0x3f000000U
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#define THRESHOLD_0_SHIFT 24
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#define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT)
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#define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
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#define THRESHOLD_1_MASK 0x003f0000U
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#define THRESHOLD_1_SHIFT 16
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#define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT)
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#define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
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#define THRESHOLD_2_MASK 0x00003f00U
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#define THRESHOLD_2_SHIFT 8
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#define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT)
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#define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
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#define THRESHOLD_3_MASK 0x0000003fU
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#define THRESHOLD_3_SHIFT 0
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#define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT)
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#define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
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2012-09-26 10:39:38 +08:00
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#define SGE_CONM_CTRL 0x1094
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#define EGRTHRESHOLD_MASK 0x00003f00U
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#define EGRTHRESHOLDshift 8
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#define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
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#define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
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2012-11-16 01:11:17 +08:00
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#define SGE_DBFIFO_STATUS 0x10a4
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#define HP_INT_THRESH_SHIFT 28
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#define HP_INT_THRESH_MASK 0xfU
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#define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT)
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#define LP_INT_THRESH_SHIFT 12
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#define LP_INT_THRESH_MASK 0xfU
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#define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT)
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#define SGE_DOORBELL_CONTROL 0x10a8
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#define ENABLE_DROP (1 << 13)
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2010-04-01 23:28:22 +08:00
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#define SGE_TIMER_VALUE_0_AND_1 0x10b8
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#define TIMERVALUE0_MASK 0xffff0000U
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#define TIMERVALUE0_SHIFT 16
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#define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT)
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#define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
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#define TIMERVALUE1_MASK 0x0000ffffU
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#define TIMERVALUE1_SHIFT 0
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#define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT)
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#define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
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#define SGE_TIMER_VALUE_2_AND_3 0x10bc
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2012-09-26 10:39:38 +08:00
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#define TIMERVALUE2_MASK 0xffff0000U
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#define TIMERVALUE2_SHIFT 16
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#define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT)
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#define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
|
|
|
|
|
#define TIMERVALUE3_MASK 0x0000ffffU
|
|
|
|
|
#define TIMERVALUE3_SHIFT 0
|
|
|
|
|
#define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT)
|
|
|
|
|
#define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
|
|
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define SGE_TIMER_VALUE_4_AND_5 0x10c0
|
2012-09-26 10:39:38 +08:00
|
|
|
#define TIMERVALUE4_MASK 0xffff0000U
|
|
|
|
|
#define TIMERVALUE4_SHIFT 16
|
|
|
|
|
#define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT)
|
|
|
|
|
#define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
|
|
|
|
|
#define TIMERVALUE5_MASK 0x0000ffffU
|
|
|
|
|
#define TIMERVALUE5_SHIFT 0
|
|
|
|
|
#define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT)
|
|
|
|
|
#define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
|
|
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define SGE_DEBUG_INDEX 0x10cc
|
|
|
|
|
#define SGE_DEBUG_DATA_HIGH 0x10d0
|
|
|
|
|
#define SGE_DEBUG_DATA_LOW 0x10d4
|
|
|
|
|
#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
|
|
|
|
|
|
2012-05-18 17:59:26 +08:00
|
|
|
#define S_HP_INT_THRESH 28
|
2012-09-05 10:01:55 +08:00
|
|
|
#define M_HP_INT_THRESH 0xfU
|
2012-05-18 17:59:26 +08:00
|
|
|
#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
|
2013-03-14 13:08:47 +08:00
|
|
|
#define S_LP_INT_THRESH_T5 18
|
|
|
|
|
#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
|
|
|
|
|
#define M_LP_COUNT_T5 0x3ffffU
|
|
|
|
|
#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
|
2012-09-05 10:01:55 +08:00
|
|
|
#define M_HP_COUNT 0x7ffU
|
|
|
|
|
#define S_HP_COUNT 16
|
|
|
|
|
#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
|
|
|
|
|
#define S_LP_INT_THRESH 12
|
|
|
|
|
#define M_LP_INT_THRESH 0xfU
|
2013-03-14 13:08:47 +08:00
|
|
|
#define M_LP_INT_THRESH_T5 0xfffU
|
2012-09-05 10:01:55 +08:00
|
|
|
#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
|
|
|
|
|
#define M_LP_COUNT 0x7ffU
|
|
|
|
|
#define S_LP_COUNT 0
|
|
|
|
|
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
|
2012-05-18 17:59:26 +08:00
|
|
|
#define A_SGE_DBFIFO_STATUS 0x10a4
|
|
|
|
|
|
2013-03-14 13:08:47 +08:00
|
|
|
#define SGE_STAT_TOTAL 0x10e4
|
|
|
|
|
#define SGE_STAT_MATCH 0x10e8
|
|
|
|
|
|
|
|
|
|
#define SGE_STAT_CFG 0x10ec
|
|
|
|
|
#define S_STATSOURCE_T5 9
|
|
|
|
|
#define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
|
|
|
|
|
|
|
|
|
|
#define SGE_DBFIFO_STATUS2 0x1118
|
|
|
|
|
#define M_HP_COUNT_T5 0x3ffU
|
|
|
|
|
#define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5)
|
|
|
|
|
#define S_HP_INT_THRESH_T5 10
|
|
|
|
|
#define M_HP_INT_THRESH_T5 0xfU
|
|
|
|
|
#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
|
|
|
|
|
|
2012-05-18 17:59:26 +08:00
|
|
|
#define S_ENABLE_DROP 13
|
|
|
|
|
#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
|
|
|
|
|
#define F_ENABLE_DROP V_ENABLE_DROP(1U)
|
|
|
|
|
#define S_DROPPED_DB 0
|
|
|
|
|
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
|
|
|
|
|
#define F_DROPPED_DB V_DROPPED_DB(1U)
|
2012-09-05 10:01:55 +08:00
|
|
|
#define A_SGE_DOORBELL_CONTROL 0x10a8
|
2012-05-18 17:59:26 +08:00
|
|
|
|
2012-09-05 10:01:55 +08:00
|
|
|
#define A_SGE_CTXT_CMD 0x11fc
|
|
|
|
|
#define A_SGE_DBQ_CTXT_BADDR 0x1084
|
2012-05-18 17:59:26 +08:00
|
|
|
|
2012-11-16 01:11:17 +08:00
|
|
|
#define PCIE_PF_CFG 0x40
|
|
|
|
|
#define AIVEC(x) ((x) << 4)
|
|
|
|
|
#define AIVEC_MASK 0x3ffU
|
|
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define PCIE_PF_CLI 0x44
|
|
|
|
|
#define PCIE_INT_CAUSE 0x3004
|
|
|
|
|
#define UNXSPLCPLERR 0x20000000U
|
|
|
|
|
#define PCIEPINT 0x10000000U
|
|
|
|
|
#define PCIESINT 0x08000000U
|
|
|
|
|
#define RPLPERR 0x04000000U
|
|
|
|
|
#define RXWRPERR 0x02000000U
|
|
|
|
|
#define RXCPLPERR 0x01000000U
|
|
|
|
|
#define PIOTAGPERR 0x00800000U
|
|
|
|
|
#define MATAGPERR 0x00400000U
|
|
|
|
|
#define INTXCLRPERR 0x00200000U
|
|
|
|
|
#define FIDPERR 0x00100000U
|
|
|
|
|
#define CFGSNPPERR 0x00080000U
|
|
|
|
|
#define HRSPPERR 0x00040000U
|
|
|
|
|
#define HREQPERR 0x00020000U
|
|
|
|
|
#define HCNTPERR 0x00010000U
|
|
|
|
|
#define DRSPPERR 0x00008000U
|
|
|
|
|
#define DREQPERR 0x00004000U
|
|
|
|
|
#define DCNTPERR 0x00002000U
|
|
|
|
|
#define CRSPPERR 0x00001000U
|
|
|
|
|
#define CREQPERR 0x00000800U
|
|
|
|
|
#define CCNTPERR 0x00000400U
|
|
|
|
|
#define TARTAGPERR 0x00000200U
|
|
|
|
|
#define PIOREQPERR 0x00000100U
|
|
|
|
|
#define PIOCPLPERR 0x00000080U
|
|
|
|
|
#define MSIXDIPERR 0x00000040U
|
|
|
|
|
#define MSIXDATAPERR 0x00000020U
|
|
|
|
|
#define MSIXADDRHPERR 0x00000010U
|
|
|
|
|
#define MSIXADDRLPERR 0x00000008U
|
|
|
|
|
#define MSIDATAPERR 0x00000004U
|
|
|
|
|
#define MSIADDRHPERR 0x00000002U
|
|
|
|
|
#define MSIADDRLPERR 0x00000001U
|
|
|
|
|
|
2013-03-14 13:08:47 +08:00
|
|
|
#define READRSPERR 0x20000000U
|
|
|
|
|
#define TRGT1GRPPERR 0x10000000U
|
|
|
|
|
#define IPSOTPERR 0x08000000U
|
|
|
|
|
#define IPRXDATAGRPPERR 0x02000000U
|
|
|
|
|
#define IPRXHDRGRPPERR 0x01000000U
|
|
|
|
|
#define MAGRPPERR 0x00400000U
|
|
|
|
|
#define VFIDPERR 0x00200000U
|
|
|
|
|
#define HREQWRPERR 0x00010000U
|
|
|
|
|
#define DREQWRPERR 0x00002000U
|
|
|
|
|
#define MSTTAGQPERR 0x00000400U
|
|
|
|
|
#define PIOREQGRPPERR 0x00000100U
|
|
|
|
|
#define PIOCPLGRPPERR 0x00000080U
|
|
|
|
|
#define MSIXSTIPERR 0x00000004U
|
|
|
|
|
#define MSTTIMEOUTPERR 0x00000002U
|
|
|
|
|
#define MSTGRPPERR 0x00000001U
|
|
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define PCIE_NONFAT_ERR 0x3010
|
|
|
|
|
#define PCIE_MEM_ACCESS_BASE_WIN 0x3068
|
2013-03-14 13:08:47 +08:00
|
|
|
#define S_PCIEOFST 10
|
|
|
|
|
#define M_PCIEOFST 0x3fffffU
|
|
|
|
|
#define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
|
2010-04-01 23:28:22 +08:00
|
|
|
#define PCIEOFST_MASK 0xfffffc00U
|
|
|
|
|
#define BIR_MASK 0x00000300U
|
|
|
|
|
#define BIR_SHIFT 8
|
|
|
|
|
#define BIR(x) ((x) << BIR_SHIFT)
|
|
|
|
|
#define WINDOW_MASK 0x000000ffU
|
|
|
|
|
#define WINDOW_SHIFT 0
|
|
|
|
|
#define WINDOW(x) ((x) << WINDOW_SHIFT)
|
2010-08-02 21:19:19 +08:00
|
|
|
#define PCIE_MEM_ACCESS_OFFSET 0x306c
|
2010-04-01 23:28:22 +08:00
|
|
|
|
2013-03-14 13:08:47 +08:00
|
|
|
#define S_PFNUM 0
|
|
|
|
|
#define V_PFNUM(x) ((x) << S_PFNUM)
|
|
|
|
|
|
2012-09-26 10:39:42 +08:00
|
|
|
#define PCIE_FW 0x30b8
|
2012-11-16 01:11:17 +08:00
|
|
|
#define PCIE_FW_ERR 0x80000000U
|
|
|
|
|
#define PCIE_FW_INIT 0x40000000U
|
|
|
|
|
#define PCIE_FW_HALT 0x20000000U
|
|
|
|
|
#define PCIE_FW_MASTER_VLD 0x00008000U
|
|
|
|
|
#define PCIE_FW_MASTER(x) ((x) << 12)
|
|
|
|
|
#define PCIE_FW_MASTER_MASK 0x7
|
|
|
|
|
#define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK)
|
2012-09-26 10:39:42 +08:00
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
|
|
|
|
|
#define RNPP 0x80000000U
|
|
|
|
|
#define RPCP 0x20000000U
|
|
|
|
|
#define RCIP 0x08000000U
|
|
|
|
|
#define RCCP 0x04000000U
|
|
|
|
|
#define RFTP 0x00800000U
|
|
|
|
|
#define PTRP 0x00100000U
|
|
|
|
|
|
|
|
|
|
#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
|
|
|
|
|
#define TPCP 0x40000000U
|
|
|
|
|
#define TNPP 0x20000000U
|
|
|
|
|
#define TFTP 0x10000000U
|
|
|
|
|
#define TCAP 0x08000000U
|
|
|
|
|
#define TCIP 0x04000000U
|
|
|
|
|
#define RCAP 0x02000000U
|
|
|
|
|
#define PLUP 0x00800000U
|
|
|
|
|
#define PLDN 0x00400000U
|
|
|
|
|
#define OTDD 0x00200000U
|
|
|
|
|
#define GTRP 0x00100000U
|
|
|
|
|
#define RDPE 0x00040000U
|
|
|
|
|
#define TDCE 0x00020000U
|
|
|
|
|
#define TDUE 0x00010000U
|
|
|
|
|
|
|
|
|
|
#define MC_INT_CAUSE 0x7518
|
|
|
|
|
#define ECC_UE_INT_CAUSE 0x00000004U
|
|
|
|
|
#define ECC_CE_INT_CAUSE 0x00000002U
|
|
|
|
|
#define PERR_INT_CAUSE 0x00000001U
|
|
|
|
|
|
|
|
|
|
#define MC_ECC_STATUS 0x751c
|
|
|
|
|
#define ECC_CECNT_MASK 0xffff0000U
|
|
|
|
|
#define ECC_CECNT_SHIFT 16
|
|
|
|
|
#define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT)
|
|
|
|
|
#define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
|
|
|
|
|
#define ECC_UECNT_MASK 0x0000ffffU
|
|
|
|
|
#define ECC_UECNT_SHIFT 0
|
|
|
|
|
#define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT)
|
|
|
|
|
#define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define MC_BIST_CMD 0x7600
|
|
|
|
|
#define START_BIST 0x80000000U
|
|
|
|
|
#define BIST_CMD_GAP_MASK 0x0000ff00U
|
|
|
|
|
#define BIST_CMD_GAP_SHIFT 8
|
|
|
|
|
#define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT)
|
|
|
|
|
#define BIST_OPCODE_MASK 0x00000003U
|
|
|
|
|
#define BIST_OPCODE_SHIFT 0
|
|
|
|
|
#define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define MC_BIST_CMD_ADDR 0x7604
|
|
|
|
|
#define MC_BIST_CMD_LEN 0x7608
|
|
|
|
|
#define MC_BIST_DATA_PATTERN 0x760c
|
|
|
|
|
#define BIST_DATA_TYPE_MASK 0x0000000fU
|
|
|
|
|
#define BIST_DATA_TYPE_SHIFT 0
|
|
|
|
|
#define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define MC_BIST_STATUS_RDATA 0x7688
|
|
|
|
|
|
2013-03-14 13:08:47 +08:00
|
|
|
#define MA_EDRAM0_BAR 0x77c0
|
|
|
|
|
#define MA_EDRAM1_BAR 0x77c4
|
|
|
|
|
#define EDRAM_SIZE_MASK 0xfffU
|
|
|
|
|
#define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK)
|
|
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define MA_EXT_MEMORY_BAR 0x77c8
|
|
|
|
|
#define EXT_MEM_SIZE_MASK 0x00000fffU
|
|
|
|
|
#define EXT_MEM_SIZE_SHIFT 0
|
|
|
|
|
#define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define MA_TARGET_MEM_ENABLE 0x77d8
|
2013-03-14 13:08:47 +08:00
|
|
|
#define EXT_MEM1_ENABLE 0x00000010U
|
2010-04-01 23:28:22 +08:00
|
|
|
#define EXT_MEM_ENABLE 0x00000004U
|
|
|
|
|
#define EDRAM1_ENABLE 0x00000002U
|
|
|
|
|
#define EDRAM0_ENABLE 0x00000001U
|
|
|
|
|
|
|
|
|
|
#define MA_INT_CAUSE 0x77e0
|
|
|
|
|
#define MEM_PERR_INT_CAUSE 0x00000002U
|
|
|
|
|
#define MEM_WRAP_INT_CAUSE 0x00000001U
|
|
|
|
|
|
|
|
|
|
#define MA_INT_WRAP_STATUS 0x77e4
|
|
|
|
|
#define MEM_WRAP_ADDRESS_MASK 0xfffffff0U
|
|
|
|
|
#define MEM_WRAP_ADDRESS_SHIFT 4
|
|
|
|
|
#define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
|
|
|
|
|
#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
|
|
|
|
|
#define MEM_WRAP_CLIENT_NUM_SHIFT 0
|
|
|
|
|
#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
|
2012-09-26 10:39:39 +08:00
|
|
|
#define MA_PCIE_FW 0x30b8
|
2010-04-01 23:28:22 +08:00
|
|
|
#define MA_PARITY_ERROR_STATUS 0x77f4
|
|
|
|
|
|
2013-03-14 13:08:47 +08:00
|
|
|
#define MA_EXT_MEMORY1_BAR 0x7808
|
2010-04-01 23:28:22 +08:00
|
|
|
#define EDC_0_BASE_ADDR 0x7900
|
|
|
|
|
|
|
|
|
|
#define EDC_BIST_CMD 0x7904
|
|
|
|
|
#define EDC_BIST_CMD_ADDR 0x7908
|
|
|
|
|
#define EDC_BIST_CMD_LEN 0x790c
|
|
|
|
|
#define EDC_BIST_DATA_PATTERN 0x7910
|
|
|
|
|
#define EDC_BIST_STATUS_RDATA 0x7928
|
|
|
|
|
#define EDC_INT_CAUSE 0x7978
|
|
|
|
|
#define ECC_UE_PAR 0x00000020U
|
|
|
|
|
#define ECC_CE_PAR 0x00000010U
|
|
|
|
|
#define PERR_PAR_CAUSE 0x00000008U
|
|
|
|
|
|
|
|
|
|
#define EDC_ECC_STATUS 0x797c
|
|
|
|
|
|
|
|
|
|
#define EDC_1_BASE_ADDR 0x7980
|
|
|
|
|
|
2010-06-18 18:05:27 +08:00
|
|
|
#define CIM_BOOT_CFG 0x7b00
|
|
|
|
|
#define BOOTADDR_MASK 0xffffff00U
|
2012-09-26 10:39:42 +08:00
|
|
|
#define UPCRST 0x1U
|
2010-06-18 18:05:27 +08:00
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define CIM_PF_MAILBOX_DATA 0x240
|
|
|
|
|
#define CIM_PF_MAILBOX_CTRL 0x280
|
|
|
|
|
#define MBMSGVALID 0x00000008U
|
|
|
|
|
#define MBINTREQ 0x00000004U
|
|
|
|
|
#define MBOWNER_MASK 0x00000003U
|
|
|
|
|
#define MBOWNER_SHIFT 0
|
|
|
|
|
#define MBOWNER(x) ((x) << MBOWNER_SHIFT)
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|
#define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
|
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|
|
|
2012-11-16 01:11:17 +08:00
|
|
|
#define CIM_PF_HOST_INT_ENABLE 0x288
|
|
|
|
|
#define MBMSGRDYINTEN(x) ((x) << 19)
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|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define CIM_PF_HOST_INT_CAUSE 0x28c
|
|
|
|
|
#define MBMSGRDYINT 0x00080000U
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|
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|
|
|
#define CIM_HOST_INT_CAUSE 0x7b2c
|
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|
|
|
#define TIEQOUTPARERRINT 0x00100000U
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|
|
|
#define TIEQINPARERRINT 0x00080000U
|
|
|
|
|
#define MBHOSTPARERR 0x00040000U
|
|
|
|
|
#define MBUPPARERR 0x00020000U
|
|
|
|
|
#define IBQPARERR 0x0001f800U
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|
|
|
#define IBQTP0PARERR 0x00010000U
|
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|
|
|
#define IBQTP1PARERR 0x00008000U
|
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|
|
|
#define IBQULPPARERR 0x00004000U
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|
|
|
#define IBQSGELOPARERR 0x00002000U
|
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|
|
|
#define IBQSGEHIPARERR 0x00001000U
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|
|
|
#define IBQNCSIPARERR 0x00000800U
|
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|
|
|
#define OBQPARERR 0x000007e0U
|
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|
|
|
#define OBQULP0PARERR 0x00000400U
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|
|
|
#define OBQULP1PARERR 0x00000200U
|
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|
|
|
#define OBQULP2PARERR 0x00000100U
|
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|
|
|
#define OBQULP3PARERR 0x00000080U
|
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|
|
|
#define OBQSGEPARERR 0x00000040U
|
|
|
|
|
#define OBQNCSIPARERR 0x00000020U
|
|
|
|
|
#define PREFDROPINT 0x00000002U
|
|
|
|
|
#define UPACCNONZERO 0x00000001U
|
|
|
|
|
|
|
|
|
|
#define CIM_HOST_UPACC_INT_CAUSE 0x7b34
|
|
|
|
|
#define EEPROMWRINT 0x40000000U
|
|
|
|
|
#define TIMEOUTMAINT 0x20000000U
|
|
|
|
|
#define TIMEOUTINT 0x10000000U
|
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|
|
|
#define RSPOVRLOOKUPINT 0x08000000U
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|
|
|
#define REQOVRLOOKUPINT 0x04000000U
|
|
|
|
|
#define BLKWRPLINT 0x02000000U
|
|
|
|
|
#define BLKRDPLINT 0x01000000U
|
|
|
|
|
#define SGLWRPLINT 0x00800000U
|
|
|
|
|
#define SGLRDPLINT 0x00400000U
|
|
|
|
|
#define BLKWRCTLINT 0x00200000U
|
|
|
|
|
#define BLKRDCTLINT 0x00100000U
|
|
|
|
|
#define SGLWRCTLINT 0x00080000U
|
|
|
|
|
#define SGLRDCTLINT 0x00040000U
|
|
|
|
|
#define BLKWREEPROMINT 0x00020000U
|
|
|
|
|
#define BLKRDEEPROMINT 0x00010000U
|
|
|
|
|
#define SGLWREEPROMINT 0x00008000U
|
|
|
|
|
#define SGLRDEEPROMINT 0x00004000U
|
|
|
|
|
#define BLKWRFLASHINT 0x00002000U
|
|
|
|
|
#define BLKRDFLASHINT 0x00001000U
|
|
|
|
|
#define SGLWRFLASHINT 0x00000800U
|
|
|
|
|
#define SGLRDFLASHINT 0x00000400U
|
|
|
|
|
#define BLKWRBOOTINT 0x00000200U
|
|
|
|
|
#define BLKRDBOOTINT 0x00000100U
|
|
|
|
|
#define SGLWRBOOTINT 0x00000080U
|
|
|
|
|
#define SGLRDBOOTINT 0x00000040U
|
|
|
|
|
#define ILLWRBEINT 0x00000020U
|
|
|
|
|
#define ILLRDBEINT 0x00000010U
|
|
|
|
|
#define ILLRDINT 0x00000008U
|
|
|
|
|
#define ILLWRINT 0x00000004U
|
|
|
|
|
#define ILLTRANSINT 0x00000002U
|
|
|
|
|
#define RSVDSPACEINT 0x00000001U
|
|
|
|
|
|
|
|
|
|
#define TP_OUT_CONFIG 0x7d04
|
|
|
|
|
#define VLANEXTENABLE_MASK 0x0000f000U
|
|
|
|
|
#define VLANEXTENABLE_SHIFT 12
|
|
|
|
|
|
2012-09-26 10:39:40 +08:00
|
|
|
#define TP_GLOBAL_CONFIG 0x7d08
|
|
|
|
|
#define FIVETUPLELOOKUP_SHIFT 17
|
|
|
|
|
#define FIVETUPLELOOKUP_MASK 0x00060000U
|
|
|
|
|
#define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT)
|
|
|
|
|
#define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \
|
|
|
|
|
FIVETUPLELOOKUP_SHIFT)
|
|
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define TP_PARA_REG2 0x7d68
|
|
|
|
|
#define MAXRXDATA_MASK 0xffff0000U
|
|
|
|
|
#define MAXRXDATA_SHIFT 16
|
|
|
|
|
#define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define TP_TIMER_RESOLUTION 0x7d90
|
|
|
|
|
#define TIMERRESOLUTION_MASK 0x00ff0000U
|
|
|
|
|
#define TIMERRESOLUTION_SHIFT 16
|
|
|
|
|
#define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
|
2012-09-26 10:39:39 +08:00
|
|
|
#define DELAYEDACKRESOLUTION_MASK 0x000000ffU
|
|
|
|
|
#define DELAYEDACKRESOLUTION_SHIFT 0
|
|
|
|
|
#define DELAYEDACKRESOLUTION_GET(x) \
|
|
|
|
|
(((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
|
2010-04-01 23:28:22 +08:00
|
|
|
|
|
|
|
|
#define TP_SHIFT_CNT 0x7dc0
|
2012-09-26 10:39:40 +08:00
|
|
|
#define SYNSHIFTMAX_SHIFT 24
|
|
|
|
|
#define SYNSHIFTMAX_MASK 0xff000000U
|
|
|
|
|
#define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT)
|
|
|
|
|
#define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \
|
|
|
|
|
SYNSHIFTMAX_SHIFT)
|
|
|
|
|
#define RXTSHIFTMAXR1_SHIFT 20
|
|
|
|
|
#define RXTSHIFTMAXR1_MASK 0x00f00000U
|
|
|
|
|
#define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT)
|
|
|
|
|
#define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \
|
|
|
|
|
RXTSHIFTMAXR1_SHIFT)
|
|
|
|
|
#define RXTSHIFTMAXR2_SHIFT 16
|
|
|
|
|
#define RXTSHIFTMAXR2_MASK 0x000f0000U
|
|
|
|
|
#define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT)
|
|
|
|
|
#define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \
|
|
|
|
|
RXTSHIFTMAXR2_SHIFT)
|
|
|
|
|
#define PERSHIFTBACKOFFMAX_SHIFT 12
|
|
|
|
|
#define PERSHIFTBACKOFFMAX_MASK 0x0000f000U
|
|
|
|
|
#define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT)
|
|
|
|
|
#define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \
|
|
|
|
|
PERSHIFTBACKOFFMAX_SHIFT)
|
|
|
|
|
#define PERSHIFTMAX_SHIFT 8
|
|
|
|
|
#define PERSHIFTMAX_MASK 0x00000f00U
|
|
|
|
|
#define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT)
|
|
|
|
|
#define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \
|
|
|
|
|
PERSHIFTMAX_SHIFT)
|
|
|
|
|
#define KEEPALIVEMAXR1_SHIFT 4
|
|
|
|
|
#define KEEPALIVEMAXR1_MASK 0x000000f0U
|
|
|
|
|
#define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT)
|
|
|
|
|
#define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \
|
|
|
|
|
KEEPALIVEMAXR1_SHIFT)
|
|
|
|
|
#define KEEPALIVEMAXR2_SHIFT 0
|
|
|
|
|
#define KEEPALIVEMAXR2_MASK 0x0000000fU
|
|
|
|
|
#define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT)
|
|
|
|
|
#define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \
|
|
|
|
|
KEEPALIVEMAXR2_SHIFT)
|
2010-04-01 23:28:22 +08:00
|
|
|
|
|
|
|
|
#define TP_CCTRL_TABLE 0x7ddc
|
|
|
|
|
#define TP_MTU_TABLE 0x7de4
|
|
|
|
|
#define MTUINDEX_MASK 0xff000000U
|
|
|
|
|
#define MTUINDEX_SHIFT 24
|
|
|
|
|
#define MTUINDEX(x) ((x) << MTUINDEX_SHIFT)
|
|
|
|
|
#define MTUWIDTH_MASK 0x000f0000U
|
|
|
|
|
#define MTUWIDTH_SHIFT 16
|
|
|
|
|
#define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT)
|
|
|
|
|
#define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
|
|
|
|
|
#define MTUVALUE_MASK 0x00003fffU
|
|
|
|
|
#define MTUVALUE_SHIFT 0
|
|
|
|
|
#define MTUVALUE(x) ((x) << MTUVALUE_SHIFT)
|
|
|
|
|
#define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define TP_RSS_LKP_TABLE 0x7dec
|
|
|
|
|
#define LKPTBLROWVLD 0x80000000U
|
|
|
|
|
#define LKPTBLQUEUE1_MASK 0x000ffc00U
|
|
|
|
|
#define LKPTBLQUEUE1_SHIFT 10
|
|
|
|
|
#define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT)
|
|
|
|
|
#define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
|
|
|
|
|
#define LKPTBLQUEUE0_MASK 0x000003ffU
|
|
|
|
|
#define LKPTBLQUEUE0_SHIFT 0
|
|
|
|
|
#define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT)
|
|
|
|
|
#define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define TP_PIO_ADDR 0x7e40
|
|
|
|
|
#define TP_PIO_DATA 0x7e44
|
|
|
|
|
#define TP_MIB_INDEX 0x7e50
|
|
|
|
|
#define TP_MIB_DATA 0x7e54
|
|
|
|
|
#define TP_INT_CAUSE 0x7e74
|
|
|
|
|
#define FLMTXFLSTEMPTY 0x40000000U
|
|
|
|
|
|
2012-09-26 10:39:40 +08:00
|
|
|
#define TP_VLAN_PRI_MAP 0x140
|
|
|
|
|
#define FRAGMENTATION_SHIFT 9
|
|
|
|
|
#define FRAGMENTATION_MASK 0x00000200U
|
|
|
|
|
#define MPSHITTYPE_MASK 0x00000100U
|
|
|
|
|
#define MACMATCH_MASK 0x00000080U
|
|
|
|
|
#define ETHERTYPE_MASK 0x00000040U
|
|
|
|
|
#define PROTOCOL_MASK 0x00000020U
|
|
|
|
|
#define TOS_MASK 0x00000010U
|
|
|
|
|
#define VLAN_MASK 0x00000008U
|
|
|
|
|
#define VNIC_ID_MASK 0x00000004U
|
|
|
|
|
#define PORT_MASK 0x00000002U
|
|
|
|
|
#define FCOE_SHIFT 0
|
|
|
|
|
#define FCOE_MASK 0x00000001U
|
|
|
|
|
|
2010-04-01 23:28:22 +08:00
|
|
|
#define TP_INGRESS_CONFIG 0x141
|
|
|
|
|
#define VNIC 0x00000800U
|
|
|
|
|
#define CSUM_HAS_PSEUDO_HDR 0x00000400U
|
|
|
|
|
#define RM_OVLAN 0x00000200U
|
|
|
|
|
#define LOOKUPEVERYPKT 0x00000100U
|
|
|
|
|
|
|
|
|
|
#define TP_MIB_MAC_IN_ERR_0 0x0
|
|
|
|
|
#define TP_MIB_TCP_OUT_RST 0xc
|
|
|
|
|
#define TP_MIB_TCP_IN_SEG_HI 0x10
|
|
|
|
|
#define TP_MIB_TCP_IN_SEG_LO 0x11
|
|
|
|
|
#define TP_MIB_TCP_OUT_SEG_HI 0x12
|
|
|
|
|
#define TP_MIB_TCP_OUT_SEG_LO 0x13
|
|
|
|
|
#define TP_MIB_TCP_RXT_SEG_HI 0x14
|
|
|
|
|
#define TP_MIB_TCP_RXT_SEG_LO 0x15
|
|
|
|
|
#define TP_MIB_TNL_CNG_DROP_0 0x18
|
|
|
|
|
#define TP_MIB_TCP_V6IN_ERR_0 0x28
|
|
|
|
|
#define TP_MIB_TCP_V6OUT_RST 0x2c
|
|
|
|
|
#define TP_MIB_OFD_ARP_DROP 0x36
|
|
|
|
|
#define TP_MIB_TNL_DROP_0 0x44
|
|
|
|
|
#define TP_MIB_OFD_VLN_DROP_0 0x58
|
|
|
|
|
|
|
|
|
|
#define ULP_TX_INT_CAUSE 0x8dcc
|
|
|
|
|
#define PBL_BOUND_ERR_CH3 0x80000000U
|
|
|
|
|
#define PBL_BOUND_ERR_CH2 0x40000000U
|
|
|
|
|
#define PBL_BOUND_ERR_CH1 0x20000000U
|
|
|
|
|
#define PBL_BOUND_ERR_CH0 0x10000000U
|
|
|
|
|
|
|
|
|
|
#define PM_RX_INT_CAUSE 0x8fdc
|
|
|
|
|
#define ZERO_E_CMD_ERROR 0x00400000U
|
|
|
|
|
#define PMRX_FRAMING_ERROR 0x003ffff0U
|
|
|
|
|
#define OCSPI_PAR_ERROR 0x00000008U
|
|
|
|
|
#define DB_OPTIONS_PAR_ERROR 0x00000004U
|
|
|
|
|
#define IESPI_PAR_ERROR 0x00000002U
|
|
|
|
|
#define E_PCMD_PAR_ERROR 0x00000001U
|
|
|
|
|
|
|
|
|
|
#define PM_TX_INT_CAUSE 0x8ffc
|
|
|
|
|
#define PCMD_LEN_OVFL0 0x80000000U
|
|
|
|
|
#define PCMD_LEN_OVFL1 0x40000000U
|
|
|
|
|
#define PCMD_LEN_OVFL2 0x20000000U
|
|
|
|
|
#define ZERO_C_CMD_ERROR 0x10000000U
|
|
|
|
|
#define PMTX_FRAMING_ERROR 0x0ffffff0U
|
|
|
|
|
#define OESPI_PAR_ERROR 0x00000008U
|
|
|
|
|
#define ICSPI_PAR_ERROR 0x00000002U
|
|
|
|
|
#define C_PCMD_PAR_ERROR 0x00000001U
|
|
|
|
|
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_64B_L 0x430
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_64B_H 0x434
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
|
|
|
|
|
#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
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#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
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#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
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#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
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#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
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#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
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#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
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#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
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#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
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#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
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#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
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#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
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#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
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#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
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#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
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#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
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#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
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#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
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#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
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#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
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#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
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#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
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#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
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#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
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#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
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#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
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#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
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#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
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#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
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#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
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#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
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#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
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#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
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#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
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#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
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#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
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#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
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#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
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#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
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#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
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#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
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#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
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#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
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#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
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#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
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#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
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#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
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#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
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#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
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#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
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#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
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#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
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#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
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#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
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#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
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#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
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#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
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#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
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#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
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#define MPS_PORT_STAT_RX_PORT_64B_L 0x590
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#define MPS_PORT_STAT_RX_PORT_64B_H 0x594
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#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
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#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
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#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
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#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
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#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
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#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
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#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
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#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
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#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
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#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
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#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
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#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
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#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
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#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
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#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
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#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
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#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
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#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
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#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
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#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
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#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
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#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
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#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
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#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
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#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
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#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
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#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
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#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
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#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
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#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
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#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
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#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
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2013-03-14 13:08:47 +08:00
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#define MAC_PORT_CFG2 0x818
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#define MAC_PORT_MAGIC_MACID_LO 0x824
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#define MAC_PORT_MAGIC_MACID_HI 0x828
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#define MAC_PORT_EPIO_DATA0 0x8c0
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#define MAC_PORT_EPIO_DATA1 0x8c4
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#define MAC_PORT_EPIO_DATA2 0x8c8
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#define MAC_PORT_EPIO_DATA3 0x8cc
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#define MAC_PORT_EPIO_OP 0x8d0
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2010-04-01 23:28:22 +08:00
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#define MPS_CMN_CTL 0x9000
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#define NUMPORTS_MASK 0x00000003U
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#define NUMPORTS_SHIFT 0
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#define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
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#define MPS_INT_CAUSE 0x9008
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#define STATINT 0x00000020U
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#define TXINT 0x00000010U
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#define RXINT 0x00000008U
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#define TRCINT 0x00000004U
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#define CLSINT 0x00000002U
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#define PLINT 0x00000001U
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#define MPS_TX_INT_CAUSE 0x9408
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#define PORTERR 0x00010000U
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#define FRMERR 0x00008000U
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#define SECNTERR 0x00004000U
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#define BUBBLE 0x00002000U
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#define TXDESCFIFO 0x00001e00U
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#define TXDATAFIFO 0x000001e0U
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#define NCSIFIFO 0x00000010U
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#define TPFIFO 0x0000000fU
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#define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
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#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
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#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
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#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
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#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
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#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
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#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
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#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
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#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
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#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
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#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
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#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
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#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
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#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
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#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
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#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
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#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
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#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
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#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
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#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
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#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
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#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
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#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
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#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
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#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
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#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
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#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
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#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
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#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
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#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
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#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
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#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
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#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
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#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
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#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
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#define MPS_TRC_CFG 0x9800
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#define TRCFIFOEMPTY 0x00000010U
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#define TRCIGNOREDROPINPUT 0x00000008U
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#define TRCKEEPDUPLICATES 0x00000004U
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#define TRCEN 0x00000002U
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#define TRCMULTIFILTER 0x00000001U
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#define MPS_TRC_RSS_CONTROL 0x9808
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#define RSSCONTROL_MASK 0x00ff0000U
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#define RSSCONTROL_SHIFT 16
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#define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT)
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#define QUEUENUMBER_MASK 0x0000ffffU
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#define QUEUENUMBER_SHIFT 0
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#define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT)
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#define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
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#define TFINVERTMATCH 0x01000000U
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#define TFPKTTOOLARGE 0x00800000U
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#define TFEN 0x00400000U
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#define TFPORT_MASK 0x003c0000U
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#define TFPORT_SHIFT 18
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#define TFPORT(x) ((x) << TFPORT_SHIFT)
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#define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
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#define TFDROP 0x00020000U
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#define TFSOPEOPERR 0x00010000U
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#define TFLENGTH_MASK 0x00001f00U
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#define TFLENGTH_SHIFT 8
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#define TFLENGTH(x) ((x) << TFLENGTH_SHIFT)
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#define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
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#define TFOFFSET_MASK 0x0000001fU
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#define TFOFFSET_SHIFT 0
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#define TFOFFSET(x) ((x) << TFOFFSET_SHIFT)
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#define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
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#define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
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#define TFMINPKTSIZE_MASK 0x01ff0000U
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#define TFMINPKTSIZE_SHIFT 16
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#define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT)
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#define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
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#define TFCAPTUREMAX_MASK 0x00003fffU
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#define TFCAPTUREMAX_SHIFT 0
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#define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT)
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#define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
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#define MPS_TRC_INT_CAUSE 0x985c
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#define MISCPERR 0x00000100U
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#define PKTFIFO 0x000000f0U
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#define FILTMEM 0x0000000fU
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#define MPS_TRC_FILTER0_MATCH 0x9c00
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#define MPS_TRC_FILTER0_DONT_CARE 0x9c80
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#define MPS_TRC_FILTER1_MATCH 0x9d00
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#define MPS_CLS_INT_CAUSE 0xd028
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#define PLERRENB 0x00000008U
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#define HASHSRAM 0x00000004U
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#define MATCHTCAM 0x00000002U
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#define MATCHSRAM 0x00000001U
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#define MPS_RX_PERR_INT_CAUSE 0x11074
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#define CPL_INTR_CAUSE 0x19054
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#define CIM_OP_MAP_PERR 0x00000020U
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#define CIM_OVFL_ERROR 0x00000010U
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#define TP_FRAMING_ERROR 0x00000008U
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#define SGE_FRAMING_ERROR 0x00000004U
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#define CIM_FRAMING_ERROR 0x00000002U
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#define ZERO_SWITCH_ERROR 0x00000001U
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#define SMB_INT_CAUSE 0x19090
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#define MSTTXFIFOPARINT 0x00200000U
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#define MSTRXFIFOPARINT 0x00100000U
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#define SLVFIFOPARINT 0x00080000U
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#define ULP_RX_INT_CAUSE 0x19158
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#define ULP_RX_ISCSI_TAGMASK 0x19164
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#define ULP_RX_ISCSI_PSZ 0x19168
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#define HPZ3_MASK 0x0f000000U
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#define HPZ3_SHIFT 24
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#define HPZ3(x) ((x) << HPZ3_SHIFT)
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#define HPZ2_MASK 0x000f0000U
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#define HPZ2_SHIFT 16
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#define HPZ2(x) ((x) << HPZ2_SHIFT)
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#define HPZ1_MASK 0x00000f00U
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#define HPZ1_SHIFT 8
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#define HPZ1(x) ((x) << HPZ1_SHIFT)
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#define HPZ0_MASK 0x0000000fU
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#define HPZ0_SHIFT 0
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#define HPZ0(x) ((x) << HPZ0_SHIFT)
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#define ULP_RX_TDDP_PSZ 0x19178
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#define SF_DATA 0x193f8
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#define SF_OP 0x193fc
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2012-11-16 01:11:17 +08:00
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#define SF_BUSY 0x80000000U
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2010-04-01 23:28:22 +08:00
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#define SF_LOCK 0x00000010U
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#define SF_CONT 0x00000008U
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#define BYTECNT_MASK 0x00000006U
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#define BYTECNT_SHIFT 1
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#define BYTECNT(x) ((x) << BYTECNT_SHIFT)
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#define OP_WR 0x00000001U
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#define PL_PF_INT_CAUSE 0x3c0
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#define PFSW 0x00000008U
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#define PFSGE 0x00000004U
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#define PFCIM 0x00000002U
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#define PFMPS 0x00000001U
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#define PL_PF_INT_ENABLE 0x3c4
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#define PL_PF_CTL 0x3c8
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#define SWINT 0x00000001U
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#define PL_WHOAMI 0x19400
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#define SOURCEPF_MASK 0x00000700U
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#define SOURCEPF_SHIFT 8
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#define SOURCEPF(x) ((x) << SOURCEPF_SHIFT)
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#define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
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#define ISVF 0x00000080U
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#define VFID_MASK 0x0000007fU
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#define VFID_SHIFT 0
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#define VFID(x) ((x) << VFID_SHIFT)
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#define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT)
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#define PL_INT_CAUSE 0x1940c
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#define ULP_TX 0x08000000U
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#define SGE 0x04000000U
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#define HMA 0x02000000U
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#define CPL_SWITCH 0x01000000U
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#define ULP_RX 0x00800000U
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#define PM_RX 0x00400000U
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#define PM_TX 0x00200000U
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#define MA 0x00100000U
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#define TP 0x00080000U
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#define LE 0x00040000U
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#define EDC1 0x00020000U
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#define EDC0 0x00010000U
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#define MC 0x00008000U
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#define PCIE 0x00004000U
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#define PMU 0x00002000U
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#define XGMAC_KR1 0x00001000U
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#define XGMAC_KR0 0x00000800U
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#define XGMAC1 0x00000400U
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#define XGMAC0 0x00000200U
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#define SMB 0x00000100U
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#define SF 0x00000080U
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#define PL 0x00000040U
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#define NCSI 0x00000020U
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#define MPS 0x00000010U
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#define MI 0x00000008U
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#define DBG 0x00000004U
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#define I2CM 0x00000002U
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#define CIM 0x00000001U
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2012-11-16 01:11:17 +08:00
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#define PL_INT_ENABLE 0x19410
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2010-04-01 23:28:22 +08:00
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#define PL_INT_MAP0 0x19414
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#define PL_RST 0x19428
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#define PIORST 0x00000002U
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#define PIORSTMODE 0x00000001U
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#define PL_PL_INT_CAUSE 0x19430
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#define FATALPERR 0x00000010U
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#define PERRVFID 0x00000001U
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#define PL_REV 0x1943c
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#define LE_DB_CONFIG 0x19c04
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#define HASHEN 0x00100000U
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#define LE_DB_SERVER_INDEX 0x19c18
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#define LE_DB_ACT_CNT_IPV4 0x19c20
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#define LE_DB_ACT_CNT_IPV6 0x19c24
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#define LE_DB_INT_CAUSE 0x19c3c
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#define REQQPARERR 0x00010000U
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#define UNKNOWNCMD 0x00008000U
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#define PARITYERR 0x00000040U
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#define LIPMISS 0x00000020U
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#define LIP0 0x00000010U
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#define LE_DB_TID_HASHBASE 0x19df8
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#define NCSI_INT_CAUSE 0x1a0d8
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#define CIM_DM_PRTY_ERR 0x00000100U
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#define MPS_DM_PRTY_ERR 0x00000080U
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#define TXFIFO_PRTY_ERR 0x00000002U
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#define RXFIFO_PRTY_ERR 0x00000001U
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#define XGMAC_PORT_CFG2 0x1018
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#define PATEN 0x00040000U
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#define MAGICEN 0x00020000U
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#define XGMAC_PORT_MAGIC_MACID_LO 0x1024
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#define XGMAC_PORT_MAGIC_MACID_HI 0x1028
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#define XGMAC_PORT_EPIO_DATA0 0x10c0
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#define XGMAC_PORT_EPIO_DATA1 0x10c4
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#define XGMAC_PORT_EPIO_DATA2 0x10c8
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#define XGMAC_PORT_EPIO_DATA3 0x10cc
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#define XGMAC_PORT_EPIO_OP 0x10d0
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#define EPIOWR 0x00000100U
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#define ADDRESS_MASK 0x000000ffU
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#define ADDRESS_SHIFT 0
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#define ADDRESS(x) ((x) << ADDRESS_SHIFT)
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|
2013-03-14 13:08:47 +08:00
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#define MAC_PORT_INT_CAUSE 0x8dc
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2010-04-01 23:28:22 +08:00
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#define XGMAC_PORT_INT_CAUSE 0x10dc
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2012-12-10 17:30:53 +08:00
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#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
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#define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
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#define S_TX_MOD_QUEUE_REQ_MAP 0
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#define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
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#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
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#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
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#define S_TX_MODQ_WEIGHT3 24
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#define M_TX_MODQ_WEIGHT3 0xffU
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#define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
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#define S_TX_MODQ_WEIGHT2 16
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#define M_TX_MODQ_WEIGHT2 0xffU
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#define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
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#define S_TX_MODQ_WEIGHT1 8
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#define M_TX_MODQ_WEIGHT1 0xffU
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#define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
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#define S_TX_MODQ_WEIGHT0 0
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#define M_TX_MODQ_WEIGHT0 0xffU
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#define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
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#define A_TP_TX_SCHED_HDR 0x23
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#define A_TP_TX_SCHED_FIFO 0x24
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#define A_TP_TX_SCHED_PCMD 0x25
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2012-12-10 17:30:54 +08:00
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#define S_PORT 1
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2012-12-10 17:30:56 +08:00
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#define V_PORT(x) ((x) << S_PORT)
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#define F_PORT V_PORT(1U)
|
2012-12-10 17:30:54 +08:00
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2013-03-14 13:08:47 +08:00
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#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
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#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
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#define T5_PORT0_BASE 0x30000
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#define T5_PORT_STRIDE 0x4000
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#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
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#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
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#define MC_0_BASE_ADDR 0x40000
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#define MC_1_BASE_ADDR 0x48000
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#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
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#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
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#define MC_P_BIST_CMD 0x41400
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#define MC_P_BIST_CMD_ADDR 0x41404
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#define MC_P_BIST_CMD_LEN 0x41408
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#define MC_P_BIST_DATA_PATTERN 0x4140c
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#define MC_P_BIST_STATUS_RDATA 0x41488
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#define EDC_T50_BASE_ADDR 0x50000
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#define EDC_H_BIST_CMD 0x50004
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#define EDC_H_BIST_CMD_ADDR 0x50008
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#define EDC_H_BIST_CMD_LEN 0x5000c
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#define EDC_H_BIST_DATA_PATTERN 0x50010
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#define EDC_H_BIST_STATUS_RDATA 0x50028
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#define EDC_T51_BASE_ADDR 0x50800
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#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
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#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
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2010-04-01 23:28:22 +08:00
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#endif /* __T4_REGS_H */
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