659 lines
40 KiB
C
659 lines
40 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ACP 6.3 Register Documentation
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*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*/
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#ifndef _acp_ip_OFFSET_HEADER
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#define _acp_ip_OFFSET_HEADER
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/* Registers from ACP_DMA block */
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#define ACP_DMA_CNTL_0 0x0000000
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#define ACP_DMA_CNTL_1 0x0000004
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#define ACP_DMA_CNTL_2 0x0000008
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#define ACP_DMA_CNTL_3 0x000000C
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#define ACP_DMA_CNTL_4 0x0000010
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#define ACP_DMA_CNTL_5 0x0000014
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#define ACP_DMA_CNTL_6 0x0000018
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#define ACP_DMA_CNTL_7 0x000001C
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#define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
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#define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
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#define ACP_DMA_DSCR_STRT_IDX_2 0x0000028
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#define ACP_DMA_DSCR_STRT_IDX_3 0x000002C
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#define ACP_DMA_DSCR_STRT_IDX_4 0x0000030
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#define ACP_DMA_DSCR_STRT_IDX_5 0x0000034
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#define ACP_DMA_DSCR_STRT_IDX_6 0x0000038
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#define ACP_DMA_DSCR_STRT_IDX_7 0x000003C
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#define ACP_DMA_DSCR_CNT_0 0x0000040
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#define ACP_DMA_DSCR_CNT_1 0x0000044
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#define ACP_DMA_DSCR_CNT_2 0x0000048
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#define ACP_DMA_DSCR_CNT_3 0x000004C
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#define ACP_DMA_DSCR_CNT_4 0x0000050
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#define ACP_DMA_DSCR_CNT_5 0x0000054
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#define ACP_DMA_DSCR_CNT_6 0x0000058
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#define ACP_DMA_DSCR_CNT_7 0x000005C
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#define ACP_DMA_PRIO_0 0x0000060
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#define ACP_DMA_PRIO_1 0x0000064
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#define ACP_DMA_PRIO_2 0x0000068
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#define ACP_DMA_PRIO_3 0x000006C
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#define ACP_DMA_PRIO_4 0x0000070
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#define ACP_DMA_PRIO_5 0x0000074
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#define ACP_DMA_PRIO_6 0x0000078
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#define ACP_DMA_PRIO_7 0x000007C
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#define ACP_DMA_CUR_DSCR_0 0x0000080
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#define ACP_DMA_CUR_DSCR_1 0x0000084
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#define ACP_DMA_CUR_DSCR_2 0x0000088
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#define ACP_DMA_CUR_DSCR_3 0x000008C
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#define ACP_DMA_CUR_DSCR_4 0x0000090
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#define ACP_DMA_CUR_DSCR_5 0x0000094
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#define ACP_DMA_CUR_DSCR_6 0x0000098
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#define ACP_DMA_CUR_DSCR_7 0x000009C
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#define ACP_DMA_CUR_TRANS_CNT_0 0x00000A0
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#define ACP_DMA_CUR_TRANS_CNT_1 0x00000A4
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#define ACP_DMA_CUR_TRANS_CNT_2 0x00000A8
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#define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC
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#define ACP_DMA_CUR_TRANS_CNT_4 0x00000B0
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#define ACP_DMA_CUR_TRANS_CNT_5 0x00000B4
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#define ACP_DMA_CUR_TRANS_CNT_6 0x00000B8
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#define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC
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#define ACP_DMA_ERR_STS_0 0x00000C0
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#define ACP_DMA_ERR_STS_1 0x00000C4
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#define ACP_DMA_ERR_STS_2 0x00000C8
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#define ACP_DMA_ERR_STS_3 0x00000CC
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#define ACP_DMA_ERR_STS_4 0x00000D0
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#define ACP_DMA_ERR_STS_5 0x00000D4
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#define ACP_DMA_ERR_STS_6 0x00000D8
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#define ACP_DMA_ERR_STS_7 0x00000DC
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#define ACP_DMA_DESC_BASE_ADDR 0x00000E0
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#define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E4
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#define ACP_DMA_CH_STS 0x00000E8
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#define ACP_DMA_CH_GROUP 0x00000EC
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#define ACP_DMA_CH_RST_STS 0x00000F0
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/* Registers from ACP_AXI2AXIATU block */
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C
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#define ACPAXI2AXI_ATU_CTRL 0x0000C40
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78
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#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C
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#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80
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/* Registers from ACP_CLKRST block */
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#define ACP_SOFT_RESET 0x0001000
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#define ACP_CONTROL 0x0001004
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#define ACP_STATUS 0x0001008
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#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010
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#define ACP_ZSC_DSP_CTRL 0x0001014
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#define ACP_ZSC_STS 0x0001018
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#define ACP_PGFSM_CONTROL 0x0001024
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#define ACP_PGFSM_STATUS 0x0001028
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#define ACP_CLKMUX_SEL 0x000102C
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/* Registers from ACP_AON block */
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#define ACP_PME_EN 0x0001400
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#define ACP_DEVICE_STATE 0x0001404
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#define AZ_DEVICE_STATE 0x0001408
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#define ACP_PIN_CONFIG 0x0001440
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#define ACP_PAD_PULLUP_CTRL 0x0001444
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#define ACP_PAD_PULLDOWN_CTRL 0x0001448
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#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C
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#define ACP_PAD_SCHMEN_CTRL 0x0001450
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#define ACP_SW_PAD_KEEPER_EN 0x0001454
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#define ACP_SW_WAKE_EN 0x0001458
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#define ACP_I2S_WAKE_EN 0x000145C
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#define ACP_SW1_WAKE_EN 0x0001460
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#define ACP_SW_I2S_ERROR_REASON 0x00018B4
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#define ACP_SW_POS_TRACK_I2S_TX_CTRL 0x00018B8
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#define ACP_SW_I2S_TX_DMA_POS 0x00018BC
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#define ACP_SW_POS_TRACK_BT_TX_CTRL 0x00018C0
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#define ACP_SW_BT_TX_DMA_POS 0x00018C4
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#define ACP_SW_POS_TRACK_HS_TX_CTRL 0x00018C8
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#define ACP_SW_HS_TX_DMA_POS 0x00018CC
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#define ACP_SW_POS_TRACK_I2S_RX_CTRL 0x00018D0
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#define ACP_SW_I2S_RX_DMA_POS 0x00018D4
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#define ACP_SW_POS_TRACK_BT_RX_CTRL 0x00018D8
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#define ACP_SW_BT_RX_DMA_POS 0x00018DC
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#define ACP_SW_POS_TRACK_HS_RX_CTRL 0x00018E0
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#define ACP_SW_HS_RX_DMA_POS 0x00018E4
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#define ACP_ERROR_INTR_MASK1 0X0001974
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#define ACP_ERROR_INTR_MASK2 0X0001978
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#define ACP_ERROR_INTR_MASK3 0X000197C
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/* Registers from ACP_P1_MISC block */
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#define ACP_EXTERNAL_INTR_ENB 0x0001A00
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#define ACP_EXTERNAL_INTR_CNTL 0x0001A04
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#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08
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#define ACP_EXTERNAL_INTR_STAT 0x0001A0C
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#define ACP_EXTERNAL_INTR_STAT1 0x0001A10
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#define ACP_ERROR_STATUS 0x0001A4C
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#define ACP_P1_SW_I2S_ERROR_REASON 0x0001A50
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#define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x0001A6C
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#define ACP_P1_SW_I2S_TX_DMA_POS 0x0001A70
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#define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x0001A74
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#define ACP_P1_SW_I2S_RX_DMA_POS 0x0001A78
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#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C
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#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80
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#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84
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#define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x0001A88
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#define ACP_P1_SW_BT_TX_DMA_POS 0x0001A8C
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#define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x0001A90
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#define ACP_P1_SW_HS_TX_DMA_POS 0x0001A94
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#define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x0001A98
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#define ACP_P1_SW_BT_RX_DMA_POS 0x0001A9C
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#define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x0001AA0
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#define ACP_P1_SW_HS_RX_DMA_POS 0x0001AA4
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#define ACP_ERROR_INTR_MASK4 0X0001AEC
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#define ACP_ERROR_INTR_MASK5 0X0001AF0
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/* Registers from ACP_AUDIO_BUFFERS block */
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#define ACP_I2S_RX_RINGBUFADDR 0x0002000
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#define ACP_I2S_RX_RINGBUFSIZE 0x0002004
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#define ACP_I2S_RX_LINKPOSITIONCNTR 0x0002008
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#define ACP_I2S_RX_FIFOADDR 0x000200C
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#define ACP_I2S_RX_FIFOSIZE 0x0002010
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#define ACP_I2S_RX_DMA_SIZE 0x0002014
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#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0002018
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#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x000201C
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#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x0002020
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#define ACP_I2S_TX_RINGBUFADDR 0x0002024
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#define ACP_I2S_TX_RINGBUFSIZE 0x0002028
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#define ACP_I2S_TX_LINKPOSITIONCNTR 0x000202C
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#define ACP_I2S_TX_FIFOADDR 0x0002030
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#define ACP_I2S_TX_FIFOSIZE 0x0002034
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#define ACP_I2S_TX_DMA_SIZE 0x0002038
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#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x000203C
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#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0002040
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#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x0002044
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#define ACP_BT_RX_RINGBUFADDR 0x0002048
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#define ACP_BT_RX_RINGBUFSIZE 0x000204C
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#define ACP_BT_RX_LINKPOSITIONCNTR 0x0002050
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#define ACP_BT_RX_FIFOADDR 0x0002054
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#define ACP_BT_RX_FIFOSIZE 0x0002058
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#define ACP_BT_RX_DMA_SIZE 0x000205C
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#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0002060
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#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x0002064
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#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x0002068
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#define ACP_BT_TX_RINGBUFADDR 0x000206C
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#define ACP_BT_TX_RINGBUFSIZE 0x0002070
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#define ACP_BT_TX_LINKPOSITIONCNTR 0x0002074
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#define ACP_BT_TX_FIFOADDR 0x0002078
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#define ACP_BT_TX_FIFOSIZE 0x000207C
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#define ACP_BT_TX_DMA_SIZE 0x0002080
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#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0002084
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#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x0002088
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#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x000208C
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#define ACP_HS_RX_RINGBUFADDR 0x0002090
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#define ACP_HS_RX_RINGBUFSIZE 0x0002094
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#define ACP_HS_RX_LINKPOSITIONCNTR 0x0002098
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#define ACP_HS_RX_FIFOADDR 0x000209C
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#define ACP_HS_RX_FIFOSIZE 0x00020A0
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#define ACP_HS_RX_DMA_SIZE 0x00020A4
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#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8
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#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x00020AC
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#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x00020B0
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#define ACP_HS_TX_RINGBUFADDR 0x00020B4
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#define ACP_HS_TX_RINGBUFSIZE 0x00020B8
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#define ACP_HS_TX_LINKPOSITIONCNTR 0x00020BC
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#define ACP_HS_TX_FIFOADDR 0x00020C0
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#define ACP_HS_TX_FIFOSIZE 0x00020C4
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#define ACP_HS_TX_DMA_SIZE 0x00020C8
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#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC
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#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x00020D0
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#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x00020D4
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#define ACP_AUDIO_RX_RINGBUFADDR ACP_I2S_RX_RINGBUFADDR
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#define ACP_AUDIO_RX_RINGBUFSIZE ACP_I2S_RX_RINGBUFSIZE
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#define ACP_AUDIO_RX_LINKPOSITIONCNTR ACP_I2S_RX_LINKPOSITIONCNTR
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#define ACP_AUDIO_RX_FIFOADDR ACP_I2S_RX_FIFOADDR
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#define ACP_AUDIO_RX_FIFOSIZE ACP_I2S_RX_FIFOSIZE
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#define ACP_AUDIO_RX_DMA_SIZE ACP_I2S_RX_DMA_SIZE
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#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH
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#define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_I2S_RX_LINEARPOSITIONCNTR_LOW
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#define ACP_AUDIO_RX_INTR_WATERMARK_SIZE ACP_I2S_RX_INTR_WATERMARK_SIZE
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#define ACP_AUDIO_TX_RINGBUFADDR ACP_I2S_TX_RINGBUFADDR
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#define ACP_AUDIO_TX_RINGBUFSIZE ACP_I2S_TX_RINGBUFSIZE
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#define ACP_AUDIO_TX_LINKPOSITIONCNTR ACP_I2S_TX_LINKPOSITIONCNTR
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#define ACP_AUDIO_TX_FIFOADDR ACP_I2S_TX_FIFOADDR
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#define ACP_AUDIO_TX_FIFOSIZE ACP_I2S_TX_FIFOSIZE
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#define ACP_AUDIO_TX_DMA_SIZE ACP_I2S_TX_DMA_SIZE
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#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH
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#define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_I2S_TX_LINEARPOSITIONCNTR_LOW
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#define ACP_AUDIO_TX_INTR_WATERMARK_SIZE ACP_I2S_TX_INTR_WATERMARK_SIZE
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/* Registers from ACP_I2S_TDM block */
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#define ACP_I2STDM_IER 0x0002400
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#define ACP_I2STDM_IRER 0x0002404
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#define ACP_I2STDM_RXFRMT 0x0002408
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#define ACP_I2STDM_ITER 0x000240C
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|
#define ACP_I2STDM_TXFRMT 0x0002410
|
||
|
|
#define ACP_I2STDM0_MSTRCLKGEN 0x0002414
|
||
|
|
#define ACP_I2STDM1_MSTRCLKGEN 0x0002418
|
||
|
|
#define ACP_I2STDM2_MSTRCLKGEN 0x000241C
|
||
|
|
#define ACP_I2STDM_REFCLKGEN 0x0002420
|
||
|
|
|
||
|
|
/* Registers from ACP_BT_TDM block */
|
||
|
|
#define ACP_BTTDM_IER 0x0002800
|
||
|
|
#define ACP_BTTDM_IRER 0x0002804
|
||
|
|
#define ACP_BTTDM_RXFRMT 0x0002808
|
||
|
|
#define ACP_BTTDM_ITER 0x000280C
|
||
|
|
#define ACP_BTTDM_TXFRMT 0x0002810
|
||
|
|
#define ACP_HSTDM_IER 0x0002814
|
||
|
|
#define ACP_HSTDM_IRER 0x0002818
|
||
|
|
#define ACP_HSTDM_RXFRMT 0x000281C
|
||
|
|
#define ACP_HSTDM_ITER 0x0002820
|
||
|
|
#define ACP_HSTDM_TXFRMT 0x0002824
|
||
|
|
|
||
|
|
/* Registers from ACP_WOV block */
|
||
|
|
#define ACP_WOV_PDM_ENABLE 0x0002C04
|
||
|
|
#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08
|
||
|
|
#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C
|
||
|
|
#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10
|
||
|
|
#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14
|
||
|
|
#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18
|
||
|
|
#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C
|
||
|
|
#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20
|
||
|
|
#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24
|
||
|
|
#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28
|
||
|
|
#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C
|
||
|
|
#define ACP_WOV_PDM_VAD_CTRL 0x0002C30
|
||
|
|
#define ACP_WOV_WAKE 0x0002C54
|
||
|
|
#define ACP_WOV_BUFFER_STATUS 0x0002C58
|
||
|
|
#define ACP_WOV_MISC_CTRL 0x0002C5C
|
||
|
|
#define ACP_WOV_CLK_CTRL 0x0002C60
|
||
|
|
#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64
|
||
|
|
#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68
|
||
|
|
#define ACP_PDM_CLKDIV 0x0002C6C
|
||
|
|
|
||
|
|
/* Registers from ACP_SW_SWCLK block */
|
||
|
|
#define ACP_SW_EN 0x0003000
|
||
|
|
#define ACP_SW_EN_STATUS 0x0003004
|
||
|
|
#define ACP_SW_FRAMESIZE 0x0003008
|
||
|
|
#define ACP_SW_SSP_COUNTER 0x000300C
|
||
|
|
#define ACP_SW_AUDIO_TX_EN 0x0003010
|
||
|
|
#define ACP_SW_AUDIO_TX_EN_STATUS 0x0003014
|
||
|
|
#define ACP_SW_AUDIO_TX_FRAME_FORMAT 0x0003018
|
||
|
|
#define ACP_SW_AUDIO_TX_SAMPLEINTERVAL 0x000301C
|
||
|
|
#define ACP_SW_AUDIO_TX_HCTRL_DP0 0x0003020
|
||
|
|
#define ACP_SW_AUDIO_TX_HCTRL_DP1 0x0003024
|
||
|
|
#define ACP_SW_AUDIO_TX_HCTRL_DP2 0x0003028
|
||
|
|
#define ACP_SW_AUDIO_TX_HCTRL_DP3 0x000302C
|
||
|
|
#define ACP_SW_AUDIO_TX_OFFSET_DP0 0x0003030
|
||
|
|
#define ACP_SW_AUDIO_TX_OFFSET_DP1 0x0003034
|
||
|
|
#define ACP_SW_AUDIO_TX_OFFSET_DP2 0x0003038
|
||
|
|
#define ACP_SW_AUDIO_TX_OFFSET_DP3 0x000303C
|
||
|
|
#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP0 0x0003040
|
||
|
|
#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP1 0x0003044
|
||
|
|
#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP2 0x0003048
|
||
|
|
#define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP3 0x000304C
|
||
|
|
#define ACP_SW_BT_TX_EN 0x0003050
|
||
|
|
#define ACP_SW_BT_TX_EN_STATUS 0x0003054
|
||
|
|
#define ACP_SW_BT_TX_FRAME_FORMAT 0x0003058
|
||
|
|
#define ACP_SW_BT_TX_SAMPLEINTERVAL 0x000305C
|
||
|
|
#define ACP_SW_BT_TX_HCTRL 0x0003060
|
||
|
|
#define ACP_SW_BT_TX_OFFSET 0x0003064
|
||
|
|
#define ACP_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003068
|
||
|
|
#define ACP_SW_HEADSET_TX_EN 0x000306C
|
||
|
|
#define ACP_SW_HEADSET_TX_EN_STATUS 0x0003070
|
||
|
|
#define ACP_SW_HEADSET_TX_FRAME_FORMAT 0x0003074
|
||
|
|
#define ACP_SW_HEADSET_TX_SAMPLEINTERVAL 0x0003078
|
||
|
|
#define ACP_SW_HEADSET_TX_HCTRL 0x000307C
|
||
|
|
#define ACP_SW_HEADSET_TX_OFFSET 0x0003080
|
||
|
|
#define ACP_SW_HEADSET_TX_CHANNEL_ENABLE_DP0 0x0003084
|
||
|
|
#define ACP_SW_AUDIO_RX_EN 0x0003088
|
||
|
|
#define ACP_SW_AUDIO_RX_EN_STATUS 0x000308C
|
||
|
|
#define ACP_SW_AUDIO_RX_FRAME_FORMAT 0x0003090
|
||
|
|
#define ACP_SW_AUDIO_RX_SAMPLEINTERVAL 0x0003094
|
||
|
|
#define ACP_SW_AUDIO_RX_HCTRL_DP0 0x0003098
|
||
|
|
#define ACP_SW_AUDIO_RX_HCTRL_DP1 0x000309C
|
||
|
|
#define ACP_SW_AUDIO_RX_HCTRL_DP2 0x0003100
|
||
|
|
#define ACP_SW_AUDIO_RX_HCTRL_DP3 0x0003104
|
||
|
|
#define ACP_SW_AUDIO_RX_OFFSET_DP0 0x0003108
|
||
|
|
#define ACP_SW_AUDIO_RX_OFFSET_DP1 0x000310C
|
||
|
|
#define ACP_SW_AUDIO_RX_OFFSET_DP2 0x0003110
|
||
|
|
#define ACP_SW_AUDIO_RX_OFFSET_DP3 0x0003114
|
||
|
|
#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP0 0x0003118
|
||
|
|
#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP1 0x000311C
|
||
|
|
#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP2 0x0003120
|
||
|
|
#define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP3 0x0003124
|
||
|
|
#define ACP_SW_BT_RX_EN 0x0003128
|
||
|
|
#define ACP_SW_BT_RX_EN_STATUS 0x000312C
|
||
|
|
#define ACP_SW_BT_RX_FRAME_FORMAT 0x0003130
|
||
|
|
#define ACP_SW_BT_RX_SAMPLEINTERVAL 0x0003134
|
||
|
|
#define ACP_SW_BT_RX_HCTRL 0x0003138
|
||
|
|
#define ACP_SW_BT_RX_OFFSET 0x000313C
|
||
|
|
#define ACP_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003140
|
||
|
|
#define ACP_SW_HEADSET_RX_EN 0x0003144
|
||
|
|
#define ACP_SW_HEADSET_RX_EN_STATUS 0x0003148
|
||
|
|
#define ACP_SW_HEADSET_RX_FRAME_FORMAT 0x000314C
|
||
|
|
#define ACP_SW_HEADSET_RX_SAMPLEINTERVAL 0x0003150
|
||
|
|
#define ACP_SW_HEADSET_RX_HCTRL 0x0003154
|
||
|
|
#define ACP_SW_HEADSET_RX_OFFSET 0x0003158
|
||
|
|
#define ACP_SW_HEADSET_RX_CHANNEL_ENABLE_DP0 0x000315C
|
||
|
|
#define ACP_SW_BPT_PORT_EN 0x0003160
|
||
|
|
#define ACP_SW_BPT_PORT_EN_STATUS 0x0003164
|
||
|
|
#define ACP_SW_BPT_PORT_FRAME_FORMAT 0x0003168
|
||
|
|
#define ACP_SW_BPT_PORT_SAMPLEINTERVAL 0x000316C
|
||
|
|
#define ACP_SW_BPT_PORT_HCTRL 0x0003170
|
||
|
|
#define ACP_SW_BPT_PORT_OFFSET 0x0003174
|
||
|
|
#define ACP_SW_BPT_PORT_CHANNEL_ENABLE 0x0003178
|
||
|
|
#define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR 0x000317C
|
||
|
|
#define ACP_SW_CLK_RESUME_CTRL 0x0003180
|
||
|
|
#define ACP_SW_CLK_RESUME_DELAY_CNTR 0x0003184
|
||
|
|
#define ACP_SW_BUS_RESET_CTRL 0x0003188
|
||
|
|
#define ACP_SW_PRBS_ERR_STATUS 0x000318C
|
||
|
|
#define SW_IMM_CMD_UPPER_WORD 0x0003230
|
||
|
|
#define SW_IMM_CMD_LOWER_QWORD 0x0003234
|
||
|
|
#define SW_IMM_RESP_UPPER_WORD 0x0003238
|
||
|
|
#define SW_IMM_RESP_LOWER_QWORD 0x000323C
|
||
|
|
#define SW_IMM_CMD_STS 0x0003240
|
||
|
|
#define SW_BRA_BASE_ADDRESS 0x0003244
|
||
|
|
#define SW_BRA_TRANSFER_SIZE 0x0003248
|
||
|
|
#define SW_BRA_DMA_BUSY 0x000324C
|
||
|
|
#define SW_BRA_RESP 0x0003250
|
||
|
|
#define SW_BRA_RESP_FRAME_ADDR 0x0003254
|
||
|
|
#define SW_BRA_CURRENT_TRANSFER_SIZE 0x0003258
|
||
|
|
#define SW_STATE_CHANGE_STATUS_0TO7 0x000325C
|
||
|
|
#define SW_STATE_CHANGE_STATUS_8TO11 0x0003260
|
||
|
|
#define SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003264
|
||
|
|
#define SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003268
|
||
|
|
#define SW_CLK_FREQUENCY_CTRL 0x000326C
|
||
|
|
#define SW_ERROR_INTR_MASK 0x0003270
|
||
|
|
#define SW_PHY_TEST_MODE_DATA_OFF 0x0003274
|
||
|
|
|
||
|
|
/* Registers from ACP_P1_AUDIO_BUFFERS block */
|
||
|
|
#define ACP_P1_I2S_RX_RINGBUFADDR 0x0003A00
|
||
|
|
#define ACP_P1_I2S_RX_RINGBUFSIZE 0x0003A04
|
||
|
|
#define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x0003A08
|
||
|
|
#define ACP_P1_I2S_RX_FIFOADDR 0x0003A0C
|
||
|
|
#define ACP_P1_I2S_RX_FIFOSIZE 0x0003A10
|
||
|
|
#define ACP_P1_I2S_RX_DMA_SIZE 0x0003A14
|
||
|
|
#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18
|
||
|
|
#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C
|
||
|
|
#define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x0003A20
|
||
|
|
#define ACP_P1_I2S_TX_RINGBUFADDR 0x0003A24
|
||
|
|
#define ACP_P1_I2S_TX_RINGBUFSIZE 0x0003A28
|
||
|
|
#define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x0003A2C
|
||
|
|
#define ACP_P1_I2S_TX_FIFOADDR 0x0003A30
|
||
|
|
#define ACP_P1_I2S_TX_FIFOSIZE 0x0003A34
|
||
|
|
#define ACP_P1_I2S_TX_DMA_SIZE 0x0003A38
|
||
|
|
#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C
|
||
|
|
#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0003A40
|
||
|
|
#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x0003A44
|
||
|
|
#define ACP_P1_BT_RX_RINGBUFADDR 0x0003A48
|
||
|
|
#define ACP_P1_BT_RX_RINGBUFSIZE 0x0003A4C
|
||
|
|
#define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x0003A50
|
||
|
|
#define ACP_P1_BT_RX_FIFOADDR 0x0003A54
|
||
|
|
#define ACP_P1_BT_RX_FIFOSIZE 0x0003A58
|
||
|
|
#define ACP_P1_BT_RX_DMA_SIZE 0x0003A5C
|
||
|
|
#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60
|
||
|
|
#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x0003A64
|
||
|
|
#define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x0003A68
|
||
|
|
#define ACP_P1_BT_TX_RINGBUFADDR 0x0003A6C
|
||
|
|
#define ACP_P1_BT_TX_RINGBUFSIZE 0x0003A70
|
||
|
|
#define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x0003A74
|
||
|
|
#define ACP_P1_BT_TX_FIFOADDR 0x0003A78
|
||
|
|
#define ACP_P1_BT_TX_FIFOSIZE 0x0003A7C
|
||
|
|
#define ACP_P1_BT_TX_DMA_SIZE 0x0003A80
|
||
|
|
#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84
|
||
|
|
#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x0003A88
|
||
|
|
#define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x0003A8C
|
||
|
|
#define ACP_P1_HS_RX_RINGBUFADDR 0x0003A90
|
||
|
|
#define ACP_P1_HS_RX_RINGBUFSIZE 0x0003A94
|
||
|
|
#define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x0003A98
|
||
|
|
#define ACP_P1_HS_RX_FIFOADDR 0x0003A9C
|
||
|
|
#define ACP_P1_HS_RX_FIFOSIZE 0x0003AA0
|
||
|
|
#define ACP_P1_HS_RX_DMA_SIZE 0x0003AA4
|
||
|
|
#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8
|
||
|
|
#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC
|
||
|
|
#define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x0003AB0
|
||
|
|
#define ACP_P1_HS_TX_RINGBUFADDR 0x0003AB4
|
||
|
|
#define ACP_P1_HS_TX_RINGBUFSIZE 0x0003AB8
|
||
|
|
#define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x0003ABC
|
||
|
|
#define ACP_P1_HS_TX_FIFOADDR 0x0003AC0
|
||
|
|
#define ACP_P1_HS_TX_FIFOSIZE 0x0003AC4
|
||
|
|
#define ACP_P1_HS_TX_DMA_SIZE 0x0003AC8
|
||
|
|
#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC
|
||
|
|
#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0
|
||
|
|
#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x0003AD4
|
||
|
|
#define ACP_P1_AUDIO_RX_RINGBUFADDR ACP_P1_I2S_RX_RINGBUFADDR
|
||
|
|
#define ACP_P1_AUDIO_RX_RINGBUFSIZE ACP_P1_I2S_RX_RINGBUFSIZE
|
||
|
|
#define ACP_P1_AUDIO_RX_LINKPOSITIONCNTR ACP_P1_I2S_RX_LINKPOSITIONCNTR
|
||
|
|
#define ACP_P1_AUDIO_RX_FIFOADDR ACP_P1_I2S_RX_FIFOADDR
|
||
|
|
#define ACP_P1_AUDIO_RX_FIFOSIZE ACP_P1_I2S_RX_FIFOSIZE
|
||
|
|
#define ACP_P1_AUDIO_RX_DMA_SIZE ACP_P1_I2S_RX_DMA_SIZE
|
||
|
|
#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH
|
||
|
|
#define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW
|
||
|
|
#define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE ACP_P1_I2S_RX_INTR_WATERMARK_SIZE
|
||
|
|
#define ACP_P1_AUDIO_TX_RINGBUFADDR ACP_P1_I2S_TX_RINGBUFADDR
|
||
|
|
#define ACP_P1_AUDIO_TX_RINGBUFSIZE ACP_P1_I2S_TX_RINGBUFSIZE
|
||
|
|
#define ACP_P1_AUDIO_TX_LINKPOSITIONCNTR ACP_P1_I2S_TX_LINKPOSITIONCNTR
|
||
|
|
#define ACP_P1_AUDIO_TX_FIFOADDR ACP_P1_I2S_TX_FIFOADDR
|
||
|
|
#define ACP_P1_AUDIO_TX_FIFOSIZE ACP_P1_I2S_TX_FIFOSIZE
|
||
|
|
#define ACP_P1_AUDIO_TX_DMA_SIZE ACP_P1_I2S_TX_DMA_SIZE
|
||
|
|
#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH
|
||
|
|
#define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW
|
||
|
|
#define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE ACP_P1_I2S_TX_INTR_WATERMARK_SIZE
|
||
|
|
|
||
|
|
/* Registers from ACP_P1_SW_SWCLK block */
|
||
|
|
#define ACP_P1_SW_EN 0x0003C00
|
||
|
|
#define ACP_P1_SW_EN_STATUS 0x0003C04
|
||
|
|
#define ACP_P1_SW_FRAMESIZE 0x0003C08
|
||
|
|
#define ACP_P1_SW_SSP_COUNTER 0x0003C0C
|
||
|
|
#define ACP_P1_SW_BT_TX_EN 0x0003C50
|
||
|
|
#define ACP_P1_SW_BT_TX_EN_STATUS 0x0003C54
|
||
|
|
#define ACP_P1_SW_BT_TX_FRAME_FORMAT 0x0003C58
|
||
|
|
#define ACP_P1_SW_BT_TX_SAMPLEINTERVAL 0x0003C5C
|
||
|
|
#define ACP_P1_SW_BT_TX_HCTRL 0x0003C60
|
||
|
|
#define ACP_P1_SW_BT_TX_OFFSET 0x0003C64
|
||
|
|
#define ACP_P1_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003C68
|
||
|
|
#define ACP_P1_SW_BT_RX_EN 0x0003D28
|
||
|
|
#define ACP_P1_SW_BT_RX_EN_STATUS 0x0003D2C
|
||
|
|
#define ACP_P1_SW_BT_RX_FRAME_FORMAT 0x0003D30
|
||
|
|
#define ACP_P1_SW_BT_RX_SAMPLEINTERVAL 0x0003D34
|
||
|
|
#define ACP_P1_SW_BT_RX_HCTRL 0x0003D38
|
||
|
|
#define ACP_P1_SW_BT_RX_OFFSET 0x0003D3C
|
||
|
|
#define ACP_P1_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003D40
|
||
|
|
#define ACP_P1_SW_BPT_PORT_EN 0x0003D60
|
||
|
|
#define ACP_P1_SW_BPT_PORT_EN_STATUS 0x0003D64
|
||
|
|
#define ACP_P1_SW_BPT_PORT_FRAME_FORMAT 0x0003D68
|
||
|
|
#define ACP_P1_SW_BPT_PORT_SAMPLEINTERVAL 0x0003D6C
|
||
|
|
#define ACP_P1_SW_BPT_PORT_HCTRL 0x0003D70
|
||
|
|
#define ACP_P1_SW_BPT_PORT_OFFSET 0x0003D74
|
||
|
|
#define ACP_P1_SW_BPT_PORT_CHANNEL_ENABLE 0x0003D78
|
||
|
|
#define ACP_P1_SW_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C
|
||
|
|
#define ACP_P1_SW_CLK_RESUME_CTRL 0x0003D80
|
||
|
|
#define ACP_P1_SW_CLK_RESUME_DELAY_CNTR 0x0003D84
|
||
|
|
#define ACP_P1_SW_BUS_RESET_CTRL 0x0003D88
|
||
|
|
#define ACP_P1_SW_PRBS_ERR_STATUS 0x0003D8C
|
||
|
|
|
||
|
|
/* Registers from ACP_P1_SW_ACLK block */
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#define P1_SW_CORB_BASE_ADDRESS 0x0003E00
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#define P1_SW_CORB_WRITE_POINTER 0x0003E04
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#define P1_SW_CORB_READ_POINTER 0x0003E08
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#define P1_SW_CORB_CONTROL 0x0003E0C
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#define P1_SW_CORB_SIZE 0x0003E14
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#define P1_SW_RIRB_BASE_ADDRESS 0x0003E18
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#define P1_SW_RIRB_WRITE_POINTER 0x0003E1C
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#define P1_SW_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20
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#define P1_SW_RIRB_CONTROL 0x0003E24
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#define P1_SW_RIRB_SIZE 0x0003E28
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#define P1_SW_RIRB_FIFO_MIN_THDL 0x0003E2C
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#define P1_SW_IMM_CMD_UPPER_WORD 0x0003E30
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#define P1_SW_IMM_CMD_LOWER_QWORD 0x0003E34
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#define P1_SW_IMM_RESP_UPPER_WORD 0x0003E38
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#define P1_SW_IMM_RESP_LOWER_QWORD 0x0003E3C
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#define P1_SW_IMM_CMD_STS 0x0003E40
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#define P1_SW_BRA_BASE_ADDRESS 0x0003E44
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#define P1_SW_BRA_TRANSFER_SIZE 0x0003E48
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#define P1_SW_BRA_DMA_BUSY 0x0003E4C
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#define P1_SW_BRA_RESP 0x0003E50
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#define P1_SW_BRA_RESP_FRAME_ADDR 0x0003E54
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#define P1_SW_BRA_CURRENT_TRANSFER_SIZE 0x0003E58
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#define P1_SW_STATE_CHANGE_STATUS_0TO7 0x0003E5C
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#define P1_SW_STATE_CHANGE_STATUS_8TO11 0x0003E60
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#define P1_SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003E64
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#define P1_SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003E68
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#define P1_SW_CLK_FREQUENCY_CTRL 0x0003E6C
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#define P1_SW_ERROR_INTR_MASK 0x0003E70
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#define P1_SW_PHY_TEST_MODE_DATA_OFF 0x0003E74
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/* Registers from ACP_SCRATCH block */
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#define ACP_SCRATCH_REG_0 0x0010000
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#define ACP_SCRATCH_REG_1 0x0010004
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#define ACP_SCRATCH_REG_2 0x0010008
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#define ACP_SCRATCH_REG_3 0x001000C
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#define ACP_SCRATCH_REG_4 0x0010010
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#define ACP_SCRATCH_REG_5 0x0010014
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#define ACP_SCRATCH_REG_6 0x0010018
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#define ACP_SCRATCH_REG_7 0x001001C
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#define ACP_SCRATCH_REG_8 0x0010020
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#define ACP_SCRATCH_REG_9 0x0010024
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#define ACP_SCRATCH_REG_10 0x0010028
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#define ACP_SCRATCH_REG_11 0x001002C
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#define ACP_SCRATCH_REG_12 0x0010030
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#define ACP_SCRATCH_REG_13 0x0010034
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#define ACP_SCRATCH_REG_14 0x0010038
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#define ACP_SCRATCH_REG_15 0x001003C
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#define ACP_SCRATCH_REG_16 0x0010040
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#define ACP_SCRATCH_REG_17 0x0010044
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#define ACP_SCRATCH_REG_18 0x0010048
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#define ACP_SCRATCH_REG_19 0x001004C
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#define ACP_SCRATCH_REG_20 0x0010050
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#define ACP_SCRATCH_REG_21 0x0010054
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#define ACP_SCRATCH_REG_22 0x0010058
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#define ACP_SCRATCH_REG_23 0x001005C
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#define ACP_SCRATCH_REG_24 0x0010060
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#define ACP_SCRATCH_REG_25 0x0010064
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#define ACP_SCRATCH_REG_26 0x0010068
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#define ACP_SCRATCH_REG_27 0x001006C
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#define ACP_SCRATCH_REG_28 0x0010070
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#define ACP_SCRATCH_REG_29 0x0010074
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#define ACP_SCRATCH_REG_30 0x0010078
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#define ACP_SCRATCH_REG_31 0x001007C
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#define ACP_SCRATCH_REG_32 0x0010080
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#define ACP_SCRATCH_REG_33 0x0010084
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#define ACP_SCRATCH_REG_34 0x0010088
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#define ACP_SCRATCH_REG_35 0x001008C
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#define ACP_SCRATCH_REG_36 0x0010090
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#define ACP_SCRATCH_REG_37 0x0010094
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#define ACP_SCRATCH_REG_38 0x0010098
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#define ACP_SCRATCH_REG_39 0x001009C
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#define ACP_SCRATCH_REG_40 0x00100A0
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#define ACP_SCRATCH_REG_41 0x00100A4
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#define ACP_SCRATCH_REG_42 0x00100A8
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#define ACP_SCRATCH_REG_43 0x00100AC
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|
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#define ACP_SCRATCH_REG_44 0x00100B0
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#define ACP_SCRATCH_REG_45 0x00100B4
|
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|
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#define ACP_SCRATCH_REG_46 0x00100B8
|
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|
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#define ACP_SCRATCH_REG_47 0x00100BC
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|
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#define ACP_SCRATCH_REG_48 0x00100C0
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|
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#define ACP_SCRATCH_REG_49 0x00100C4
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|
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#define ACP_SCRATCH_REG_50 0x00100C8
|
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|
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#define ACP_SCRATCH_REG_51 0x00100CC
|
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|
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#define ACP_SCRATCH_REG_52 0x00100D0
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|
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#define ACP_SCRATCH_REG_53 0x00100D4
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|
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#define ACP_SCRATCH_REG_54 0x00100D8
|
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|
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#define ACP_SCRATCH_REG_55 0x00100DC
|
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|
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#define ACP_SCRATCH_REG_56 0x00100E0
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|
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#define ACP_SCRATCH_REG_57 0x00100E4
|
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|
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#define ACP_SCRATCH_REG_58 0x00100E8
|
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|
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#define ACP_SCRATCH_REG_59 0x00100EC
|
||
|
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#define ACP_SCRATCH_REG_60 0x00100F0
|
||
|
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#define ACP_SCRATCH_REG_61 0x00100F4
|
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|
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#define ACP_SCRATCH_REG_62 0x00100F8
|
||
|
|
#define ACP_SCRATCH_REG_63 0x00100FC
|
||
|
|
#define ACP_SCRATCH_REG_64 0x0010100
|
||
|
|
#define ACP_SCRATCH_REG_65 0x0010104
|
||
|
|
#define ACP_SCRATCH_REG_66 0x0010108
|
||
|
|
#define ACP_SCRATCH_REG_67 0x001010C
|
||
|
|
#define ACP_SCRATCH_REG_68 0x0010110
|
||
|
|
#define ACP_SCRATCH_REG_69 0x0010114
|
||
|
|
#define ACP_SCRATCH_REG_70 0x0010118
|
||
|
|
#define ACP_SCRATCH_REG_71 0x001011C
|
||
|
|
#define ACP_SCRATCH_REG_72 0x0010120
|
||
|
|
#define ACP_SCRATCH_REG_73 0x0010124
|
||
|
|
#define ACP_SCRATCH_REG_74 0x0010128
|
||
|
|
#define ACP_SCRATCH_REG_75 0x001012C
|
||
|
|
#define ACP_SCRATCH_REG_76 0x0010130
|
||
|
|
#define ACP_SCRATCH_REG_77 0x0010134
|
||
|
|
#define ACP_SCRATCH_REG_78 0x0010138
|
||
|
|
#define ACP_SCRATCH_REG_79 0x001013C
|
||
|
|
#define ACP_SCRATCH_REG_80 0x0010140
|
||
|
|
#define ACP_SCRATCH_REG_81 0x0010144
|
||
|
|
#define ACP_SCRATCH_REG_82 0x0010148
|
||
|
|
#define ACP_SCRATCH_REG_83 0x001014C
|
||
|
|
#define ACP_SCRATCH_REG_84 0x0010150
|
||
|
|
#define ACP_SCRATCH_REG_85 0x0010154
|
||
|
|
#define ACP_SCRATCH_REG_86 0x0010158
|
||
|
|
#define ACP_SCRATCH_REG_87 0x001015C
|
||
|
|
#define ACP_SCRATCH_REG_88 0x0010160
|
||
|
|
#define ACP_SCRATCH_REG_89 0x0010164
|
||
|
|
#define ACP_SCRATCH_REG_90 0x0010168
|
||
|
|
#define ACP_SCRATCH_REG_91 0x001016C
|
||
|
|
#define ACP_SCRATCH_REG_92 0x0010170
|
||
|
|
#define ACP_SCRATCH_REG_93 0x0010174
|
||
|
|
#define ACP_SCRATCH_REG_94 0x0010178
|
||
|
|
#define ACP_SCRATCH_REG_95 0x001017C
|
||
|
|
#define ACP_SCRATCH_REG_96 0x0010180
|
||
|
|
#define ACP_SCRATCH_REG_97 0x0010184
|
||
|
|
#define ACP_SCRATCH_REG_98 0x0010188
|
||
|
|
#define ACP_SCRATCH_REG_99 0x001018C
|
||
|
|
#define ACP_SCRATCH_REG_100 0x0010190
|
||
|
|
#define ACP_SCRATCH_REG_101 0x0010194
|
||
|
|
#define ACP_SCRATCH_REG_102 0x0010198
|
||
|
|
#define ACP_SCRATCH_REG_103 0x001019C
|
||
|
|
#define ACP_SCRATCH_REG_104 0x00101A0
|
||
|
|
#define ACP_SCRATCH_REG_105 0x00101A4
|
||
|
|
#define ACP_SCRATCH_REG_106 0x00101A8
|
||
|
|
#define ACP_SCRATCH_REG_107 0x00101AC
|
||
|
|
#define ACP_SCRATCH_REG_108 0x00101B0
|
||
|
|
#define ACP_SCRATCH_REG_109 0x00101B4
|
||
|
|
#define ACP_SCRATCH_REG_110 0x00101B8
|
||
|
|
#define ACP_SCRATCH_REG_111 0x00101BC
|
||
|
|
#define ACP_SCRATCH_REG_112 0x00101C0
|
||
|
|
#define ACP_SCRATCH_REG_113 0x00101C4
|
||
|
|
#define ACP_SCRATCH_REG_114 0x00101C8
|
||
|
|
#define ACP_SCRATCH_REG_115 0x00101CC
|
||
|
|
#define ACP_SCRATCH_REG_116 0x00101D0
|
||
|
|
#define ACP_SCRATCH_REG_117 0x00101D4
|
||
|
|
#define ACP_SCRATCH_REG_118 0x00101D8
|
||
|
|
#define ACP_SCRATCH_REG_119 0x00101DC
|
||
|
|
#define ACP_SCRATCH_REG_120 0x00101E0
|
||
|
|
#define ACP_SCRATCH_REG_121 0x00101E4
|
||
|
|
#define ACP_SCRATCH_REG_122 0x00101E8
|
||
|
|
#define ACP_SCRATCH_REG_123 0x00101EC
|
||
|
|
#define ACP_SCRATCH_REG_124 0x00101F0
|
||
|
|
#define ACP_SCRATCH_REG_125 0x00101F4
|
||
|
|
#define ACP_SCRATCH_REG_126 0x00101F8
|
||
|
|
#define ACP_SCRATCH_REG_127 0x00101FC
|
||
|
|
#define ACP_SCRATCH_REG_128 0x0010200
|
||
|
|
#endif
|