2008-04-27 19:55:59 +08:00
|
|
|
/****************************************************************************
|
2013-08-30 06:32:48 +08:00
|
|
|
* Driver for Solarflare network controllers and boards
|
2008-04-27 19:55:59 +08:00
|
|
|
* Copyright 2005-2006 Fen Systems Ltd.
|
2013-08-30 06:32:48 +08:00
|
|
|
* Copyright 2006-2013 Solarflare Communications Inc.
|
2008-04-27 19:55:59 +08:00
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
|
* under the terms of the GNU General Public License version 2 as published
|
|
|
|
|
* by the Free Software Foundation, incorporated herein by reference.
|
|
|
|
|
*/
|
|
|
|
|
|
2009-11-29 23:12:08 +08:00
|
|
|
#ifndef EFX_NIC_H
|
|
|
|
|
#define EFX_NIC_H
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2012-09-03 18:09:36 +08:00
|
|
|
#include <linux/net_tstamp.h>
|
2009-11-24 00:05:28 +08:00
|
|
|
#include <linux/i2c-algo-bit.h>
|
2008-04-27 19:55:59 +08:00
|
|
|
#include "net_driver.h"
|
2008-12-13 13:50:08 +08:00
|
|
|
#include "efx.h"
|
2009-11-29 23:15:41 +08:00
|
|
|
#include "mcdi.h"
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2009-11-28 13:36:04 +08:00
|
|
|
enum {
|
2017-05-13 00:18:50 +08:00
|
|
|
/* Revisions 0-2 were Falcon A0, A1 and B0 respectively.
|
|
|
|
|
* They are not supported by this driver but these revision numbers
|
|
|
|
|
* form part of the ethtool API for register dumping.
|
|
|
|
|
*/
|
|
|
|
|
EFX_REV_SIENA_A0 = 3,
|
|
|
|
|
EFX_REV_HUNT_A0 = 4,
|
2008-04-27 19:55:59 +08:00
|
|
|
};
|
|
|
|
|
|
2009-11-28 13:36:04 +08:00
|
|
|
static inline int efx_nic_rev(struct efx_nic *efx)
|
2008-05-17 04:16:10 +08:00
|
|
|
{
|
2009-11-28 13:36:04 +08:00
|
|
|
return efx->type->revision;
|
2008-05-17 04:16:10 +08:00
|
|
|
}
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
u32 efx_farch_fpga_ver(struct efx_nic *efx);
|
2009-11-29 11:43:56 +08:00
|
|
|
|
2013-08-22 02:51:04 +08:00
|
|
|
/* Read the current event from the event queue */
|
|
|
|
|
static inline efx_qword_t *efx_event(struct efx_channel *channel,
|
|
|
|
|
unsigned int index)
|
|
|
|
|
{
|
|
|
|
|
return ((efx_qword_t *) (channel->eventq.buf.addr)) +
|
|
|
|
|
(index & channel->eventq_mask);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* See if an event is present
|
|
|
|
|
*
|
|
|
|
|
* We check both the high and low dword of the event for all ones. We
|
|
|
|
|
* wrote all ones when we cleared the event, and no valid event can
|
|
|
|
|
* have all ones in either its high or low dwords. This approach is
|
|
|
|
|
* robust against reordering.
|
|
|
|
|
*
|
|
|
|
|
* Note that using a single 64-bit comparison is incorrect; even
|
|
|
|
|
* though the CPU read will be atomic, the DMA write may not be.
|
|
|
|
|
*/
|
|
|
|
|
static inline int efx_event_present(efx_qword_t *event)
|
|
|
|
|
{
|
|
|
|
|
return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
|
|
|
|
|
EFX_DWORD_IS_ALL_ONES(event->dword[1]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Returns a pointer to the specified transmit descriptor in the TX
|
|
|
|
|
* descriptor queue belonging to the specified channel.
|
|
|
|
|
*/
|
|
|
|
|
static inline efx_qword_t *
|
|
|
|
|
efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
|
|
|
|
|
{
|
|
|
|
|
return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-17 22:32:25 +08:00
|
|
|
/* Get partner of a TX queue, seen as part of the same net core queue */
|
|
|
|
|
static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
|
|
|
|
|
{
|
|
|
|
|
if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
|
|
|
|
|
return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
|
|
|
|
|
else
|
|
|
|
|
return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Report whether this TX queue would be empty for the given write_count.
|
|
|
|
|
* May return false negative.
|
2013-06-29 04:47:15 +08:00
|
|
|
*/
|
|
|
|
|
static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
|
|
|
|
|
unsigned int write_count)
|
|
|
|
|
{
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 05:07:29 +08:00
|
|
|
unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count);
|
2013-06-29 04:47:15 +08:00
|
|
|
|
|
|
|
|
if (empty_read_count == 0)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-14 05:20:14 +08:00
|
|
|
/* Report whether the NIC considers this TX queue empty, using
|
|
|
|
|
* packet_write_count (the write count recorded for the last completable
|
|
|
|
|
* doorbell push). May return false negative. EF10 only, which is OK
|
|
|
|
|
* because only EF10 supports PIO.
|
|
|
|
|
*/
|
|
|
|
|
static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue)
|
|
|
|
|
{
|
|
|
|
|
EFX_WARN_ON_ONCE_PARANOID(!tx_queue->efx->type->option_descriptors);
|
|
|
|
|
return __efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count);
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-17 22:32:25 +08:00
|
|
|
/* Decide whether we can use TX PIO, ie. write packet data directly into
|
|
|
|
|
* a buffer on the device. This can reduce latency at the expense of
|
|
|
|
|
* throughput, so we only do this if both hardware and software TX rings
|
|
|
|
|
* are empty. This also ensures that only one packet at a time can be
|
|
|
|
|
* using the PIO buffer.
|
|
|
|
|
*/
|
|
|
|
|
static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue)
|
2013-06-29 04:47:15 +08:00
|
|
|
{
|
2014-10-17 22:32:25 +08:00
|
|
|
struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue);
|
2017-01-14 05:20:14 +08:00
|
|
|
|
|
|
|
|
return tx_queue->piobuf && efx_nic_tx_is_empty(tx_queue) &&
|
|
|
|
|
efx_nic_tx_is_empty(partner);
|
2013-06-29 04:47:15 +08:00
|
|
|
}
|
|
|
|
|
|
2013-08-22 02:51:04 +08:00
|
|
|
/* Decide whether to push a TX descriptor to the NIC vs merely writing
|
|
|
|
|
* the doorbell. This can reduce latency when we are adding a single
|
|
|
|
|
* descriptor to an empty queue, but is otherwise pointless. Further,
|
|
|
|
|
* Falcon and Siena have hardware bugs (SF bug 33851) that may be
|
|
|
|
|
* triggered if we don't check this.
|
2014-10-17 22:32:25 +08:00
|
|
|
* We use the write_count used for the last doorbell push, to get the
|
|
|
|
|
* NIC's view of the tx queue.
|
2013-08-22 02:51:04 +08:00
|
|
|
*/
|
|
|
|
|
static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
|
|
|
|
|
unsigned int write_count)
|
|
|
|
|
{
|
2013-06-29 04:47:15 +08:00
|
|
|
bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
|
2013-08-22 02:51:04 +08:00
|
|
|
|
|
|
|
|
tx_queue->empty_read_count = 0;
|
2013-06-29 04:47:15 +08:00
|
|
|
return was_empty && tx_queue->write_count - write_count == 1;
|
2013-08-22 02:51:04 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Returns a pointer to the specified descriptor in the RX descriptor queue */
|
|
|
|
|
static inline efx_qword_t *
|
|
|
|
|
efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
|
|
|
|
|
{
|
|
|
|
|
return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
|
|
|
|
|
}
|
|
|
|
|
|
2009-11-29 23:08:55 +08:00
|
|
|
enum {
|
|
|
|
|
PHY_TYPE_NONE = 0,
|
|
|
|
|
PHY_TYPE_TXC43128 = 1,
|
|
|
|
|
PHY_TYPE_88E1111 = 2,
|
|
|
|
|
PHY_TYPE_SFX7101 = 3,
|
|
|
|
|
PHY_TYPE_QT2022C2 = 4,
|
|
|
|
|
PHY_TYPE_PM8358 = 6,
|
|
|
|
|
PHY_TYPE_SFT9001A = 8,
|
|
|
|
|
PHY_TYPE_QT2025C = 9,
|
|
|
|
|
PHY_TYPE_SFT9001B = 10,
|
|
|
|
|
};
|
|
|
|
|
|
2012-02-03 05:21:15 +08:00
|
|
|
/* Alignment of PCIe DMA boundaries (4KB) */
|
|
|
|
|
#define EFX_PAGE_SIZE 4096
|
|
|
|
|
/* Size and alignment of buffer table entries (same) */
|
|
|
|
|
#define EFX_BUF_SIZE EFX_PAGE_SIZE
|
|
|
|
|
|
2014-07-15 18:58:12 +08:00
|
|
|
/* NIC-generic software stats */
|
|
|
|
|
enum {
|
|
|
|
|
GENERIC_STAT_rx_noskb_drops,
|
|
|
|
|
GENERIC_STAT_rx_nodesc_trunc,
|
|
|
|
|
GENERIC_STAT_COUNT
|
|
|
|
|
};
|
|
|
|
|
|
2012-12-15 05:52:56 +08:00
|
|
|
enum {
|
2014-07-15 18:58:12 +08:00
|
|
|
SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
|
2012-12-15 05:52:56 +08:00
|
|
|
SIENA_STAT_tx_good_bytes,
|
|
|
|
|
SIENA_STAT_tx_bad_bytes,
|
|
|
|
|
SIENA_STAT_tx_packets,
|
|
|
|
|
SIENA_STAT_tx_bad,
|
|
|
|
|
SIENA_STAT_tx_pause,
|
|
|
|
|
SIENA_STAT_tx_control,
|
|
|
|
|
SIENA_STAT_tx_unicast,
|
|
|
|
|
SIENA_STAT_tx_multicast,
|
|
|
|
|
SIENA_STAT_tx_broadcast,
|
|
|
|
|
SIENA_STAT_tx_lt64,
|
|
|
|
|
SIENA_STAT_tx_64,
|
|
|
|
|
SIENA_STAT_tx_65_to_127,
|
|
|
|
|
SIENA_STAT_tx_128_to_255,
|
|
|
|
|
SIENA_STAT_tx_256_to_511,
|
|
|
|
|
SIENA_STAT_tx_512_to_1023,
|
|
|
|
|
SIENA_STAT_tx_1024_to_15xx,
|
|
|
|
|
SIENA_STAT_tx_15xx_to_jumbo,
|
|
|
|
|
SIENA_STAT_tx_gtjumbo,
|
|
|
|
|
SIENA_STAT_tx_collision,
|
|
|
|
|
SIENA_STAT_tx_single_collision,
|
|
|
|
|
SIENA_STAT_tx_multiple_collision,
|
|
|
|
|
SIENA_STAT_tx_excessive_collision,
|
|
|
|
|
SIENA_STAT_tx_deferred,
|
|
|
|
|
SIENA_STAT_tx_late_collision,
|
|
|
|
|
SIENA_STAT_tx_excessive_deferred,
|
|
|
|
|
SIENA_STAT_tx_non_tcpudp,
|
|
|
|
|
SIENA_STAT_tx_mac_src_error,
|
|
|
|
|
SIENA_STAT_tx_ip_src_error,
|
|
|
|
|
SIENA_STAT_rx_bytes,
|
|
|
|
|
SIENA_STAT_rx_good_bytes,
|
|
|
|
|
SIENA_STAT_rx_bad_bytes,
|
|
|
|
|
SIENA_STAT_rx_packets,
|
|
|
|
|
SIENA_STAT_rx_good,
|
|
|
|
|
SIENA_STAT_rx_bad,
|
|
|
|
|
SIENA_STAT_rx_pause,
|
|
|
|
|
SIENA_STAT_rx_control,
|
|
|
|
|
SIENA_STAT_rx_unicast,
|
|
|
|
|
SIENA_STAT_rx_multicast,
|
|
|
|
|
SIENA_STAT_rx_broadcast,
|
|
|
|
|
SIENA_STAT_rx_lt64,
|
|
|
|
|
SIENA_STAT_rx_64,
|
|
|
|
|
SIENA_STAT_rx_65_to_127,
|
|
|
|
|
SIENA_STAT_rx_128_to_255,
|
|
|
|
|
SIENA_STAT_rx_256_to_511,
|
|
|
|
|
SIENA_STAT_rx_512_to_1023,
|
|
|
|
|
SIENA_STAT_rx_1024_to_15xx,
|
|
|
|
|
SIENA_STAT_rx_15xx_to_jumbo,
|
|
|
|
|
SIENA_STAT_rx_gtjumbo,
|
|
|
|
|
SIENA_STAT_rx_bad_gtjumbo,
|
|
|
|
|
SIENA_STAT_rx_overflow,
|
|
|
|
|
SIENA_STAT_rx_false_carrier,
|
|
|
|
|
SIENA_STAT_rx_symbol_error,
|
|
|
|
|
SIENA_STAT_rx_align_error,
|
|
|
|
|
SIENA_STAT_rx_length_error,
|
|
|
|
|
SIENA_STAT_rx_internal_error,
|
|
|
|
|
SIENA_STAT_rx_nodesc_drop_cnt,
|
|
|
|
|
SIENA_STAT_COUNT
|
|
|
|
|
};
|
|
|
|
|
|
2009-11-29 23:15:41 +08:00
|
|
|
/**
|
|
|
|
|
* struct siena_nic_data - Siena NIC state
|
2014-11-05 20:16:18 +08:00
|
|
|
* @efx: Pointer back to main interface structure
|
2009-11-29 23:15:41 +08:00
|
|
|
* @wol_filter_id: Wake-on-LAN packet filter id
|
2012-12-15 05:52:56 +08:00
|
|
|
* @stats: Hardware statistics
|
2015-05-06 07:55:36 +08:00
|
|
|
* @vf: Array of &struct siena_vf objects
|
2014-11-05 20:16:18 +08:00
|
|
|
* @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
|
|
|
|
|
* @vfdi_status: Common VFDI status page to be dmad to VF address space.
|
|
|
|
|
* @local_addr_list: List of local addresses. Protected by %local_lock.
|
|
|
|
|
* @local_page_list: List of DMA addressable pages used to broadcast
|
|
|
|
|
* %local_addr_list. Protected by %local_lock.
|
|
|
|
|
* @local_lock: Mutex protecting %local_addr_list and %local_page_list.
|
|
|
|
|
* @peer_work: Work item to broadcast peer addresses to VMs.
|
2009-11-29 23:15:41 +08:00
|
|
|
*/
|
|
|
|
|
struct siena_nic_data {
|
2014-11-05 20:16:18 +08:00
|
|
|
struct efx_nic *efx;
|
2009-11-29 23:15:41 +08:00
|
|
|
int wol_filter_id;
|
2012-12-15 05:52:56 +08:00
|
|
|
u64 stats[SIENA_STAT_COUNT];
|
2014-11-05 20:16:18 +08:00
|
|
|
#ifdef CONFIG_SFC_SRIOV
|
2015-05-06 07:55:36 +08:00
|
|
|
struct siena_vf *vf;
|
2014-11-05 20:16:18 +08:00
|
|
|
struct efx_channel *vfdi_channel;
|
|
|
|
|
unsigned vf_buftbl_base;
|
|
|
|
|
struct efx_buffer vfdi_status;
|
|
|
|
|
struct list_head local_addr_list;
|
|
|
|
|
struct list_head local_page_list;
|
|
|
|
|
struct mutex local_lock;
|
|
|
|
|
struct work_struct peer_work;
|
|
|
|
|
#endif
|
2009-11-29 23:15:41 +08:00
|
|
|
};
|
|
|
|
|
|
2013-08-30 02:19:29 +08:00
|
|
|
enum {
|
2015-06-02 18:38:34 +08:00
|
|
|
EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
|
|
|
|
|
EF10_STAT_port_tx_packets,
|
|
|
|
|
EF10_STAT_port_tx_pause,
|
|
|
|
|
EF10_STAT_port_tx_control,
|
|
|
|
|
EF10_STAT_port_tx_unicast,
|
|
|
|
|
EF10_STAT_port_tx_multicast,
|
|
|
|
|
EF10_STAT_port_tx_broadcast,
|
|
|
|
|
EF10_STAT_port_tx_lt64,
|
|
|
|
|
EF10_STAT_port_tx_64,
|
|
|
|
|
EF10_STAT_port_tx_65_to_127,
|
|
|
|
|
EF10_STAT_port_tx_128_to_255,
|
|
|
|
|
EF10_STAT_port_tx_256_to_511,
|
|
|
|
|
EF10_STAT_port_tx_512_to_1023,
|
|
|
|
|
EF10_STAT_port_tx_1024_to_15xx,
|
|
|
|
|
EF10_STAT_port_tx_15xx_to_jumbo,
|
|
|
|
|
EF10_STAT_port_rx_bytes,
|
|
|
|
|
EF10_STAT_port_rx_bytes_minus_good_bytes,
|
|
|
|
|
EF10_STAT_port_rx_good_bytes,
|
|
|
|
|
EF10_STAT_port_rx_bad_bytes,
|
|
|
|
|
EF10_STAT_port_rx_packets,
|
|
|
|
|
EF10_STAT_port_rx_good,
|
|
|
|
|
EF10_STAT_port_rx_bad,
|
|
|
|
|
EF10_STAT_port_rx_pause,
|
|
|
|
|
EF10_STAT_port_rx_control,
|
|
|
|
|
EF10_STAT_port_rx_unicast,
|
|
|
|
|
EF10_STAT_port_rx_multicast,
|
|
|
|
|
EF10_STAT_port_rx_broadcast,
|
|
|
|
|
EF10_STAT_port_rx_lt64,
|
|
|
|
|
EF10_STAT_port_rx_64,
|
|
|
|
|
EF10_STAT_port_rx_65_to_127,
|
|
|
|
|
EF10_STAT_port_rx_128_to_255,
|
|
|
|
|
EF10_STAT_port_rx_256_to_511,
|
|
|
|
|
EF10_STAT_port_rx_512_to_1023,
|
|
|
|
|
EF10_STAT_port_rx_1024_to_15xx,
|
|
|
|
|
EF10_STAT_port_rx_15xx_to_jumbo,
|
|
|
|
|
EF10_STAT_port_rx_gtjumbo,
|
|
|
|
|
EF10_STAT_port_rx_bad_gtjumbo,
|
|
|
|
|
EF10_STAT_port_rx_overflow,
|
|
|
|
|
EF10_STAT_port_rx_align_error,
|
|
|
|
|
EF10_STAT_port_rx_length_error,
|
|
|
|
|
EF10_STAT_port_rx_nodesc_drops,
|
|
|
|
|
EF10_STAT_port_rx_pm_trunc_bb_overflow,
|
|
|
|
|
EF10_STAT_port_rx_pm_discard_bb_overflow,
|
|
|
|
|
EF10_STAT_port_rx_pm_trunc_vfifo_full,
|
|
|
|
|
EF10_STAT_port_rx_pm_discard_vfifo_full,
|
|
|
|
|
EF10_STAT_port_rx_pm_trunc_qbb,
|
|
|
|
|
EF10_STAT_port_rx_pm_discard_qbb,
|
|
|
|
|
EF10_STAT_port_rx_pm_discard_mapping,
|
|
|
|
|
EF10_STAT_port_rx_dp_q_disabled_packets,
|
|
|
|
|
EF10_STAT_port_rx_dp_di_dropped_packets,
|
|
|
|
|
EF10_STAT_port_rx_dp_streaming_packets,
|
|
|
|
|
EF10_STAT_port_rx_dp_hlb_fetch,
|
|
|
|
|
EF10_STAT_port_rx_dp_hlb_wait,
|
2015-06-02 18:39:06 +08:00
|
|
|
EF10_STAT_rx_unicast,
|
|
|
|
|
EF10_STAT_rx_unicast_bytes,
|
|
|
|
|
EF10_STAT_rx_multicast,
|
|
|
|
|
EF10_STAT_rx_multicast_bytes,
|
|
|
|
|
EF10_STAT_rx_broadcast,
|
|
|
|
|
EF10_STAT_rx_broadcast_bytes,
|
|
|
|
|
EF10_STAT_rx_bad,
|
|
|
|
|
EF10_STAT_rx_bad_bytes,
|
|
|
|
|
EF10_STAT_rx_overflow,
|
|
|
|
|
EF10_STAT_tx_unicast,
|
|
|
|
|
EF10_STAT_tx_unicast_bytes,
|
|
|
|
|
EF10_STAT_tx_multicast,
|
|
|
|
|
EF10_STAT_tx_multicast_bytes,
|
|
|
|
|
EF10_STAT_tx_broadcast,
|
|
|
|
|
EF10_STAT_tx_broadcast_bytes,
|
|
|
|
|
EF10_STAT_tx_bad,
|
|
|
|
|
EF10_STAT_tx_bad_bytes,
|
|
|
|
|
EF10_STAT_tx_overflow,
|
2017-12-21 17:00:36 +08:00
|
|
|
EF10_STAT_V1_COUNT,
|
|
|
|
|
EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
|
|
|
|
|
EF10_STAT_fec_corrected_errors,
|
|
|
|
|
EF10_STAT_fec_corrected_symbols_lane0,
|
|
|
|
|
EF10_STAT_fec_corrected_symbols_lane1,
|
|
|
|
|
EF10_STAT_fec_corrected_symbols_lane2,
|
|
|
|
|
EF10_STAT_fec_corrected_symbols_lane3,
|
2017-12-21 17:00:41 +08:00
|
|
|
EF10_STAT_ctpio_dmabuf_start,
|
|
|
|
|
EF10_STAT_ctpio_vi_busy_fallback,
|
|
|
|
|
EF10_STAT_ctpio_long_write_success,
|
|
|
|
|
EF10_STAT_ctpio_missing_dbell_fail,
|
|
|
|
|
EF10_STAT_ctpio_overflow_fail,
|
|
|
|
|
EF10_STAT_ctpio_underflow_fail,
|
|
|
|
|
EF10_STAT_ctpio_timeout_fail,
|
|
|
|
|
EF10_STAT_ctpio_noncontig_wr_fail,
|
|
|
|
|
EF10_STAT_ctpio_frm_clobber_fail,
|
|
|
|
|
EF10_STAT_ctpio_invalid_wr_fail,
|
|
|
|
|
EF10_STAT_ctpio_vi_clobber_fallback,
|
|
|
|
|
EF10_STAT_ctpio_unqualified_fallback,
|
|
|
|
|
EF10_STAT_ctpio_runt_fallback,
|
|
|
|
|
EF10_STAT_ctpio_success,
|
|
|
|
|
EF10_STAT_ctpio_fallback,
|
|
|
|
|
EF10_STAT_ctpio_poison,
|
|
|
|
|
EF10_STAT_ctpio_erase,
|
2013-08-30 02:19:29 +08:00
|
|
|
EF10_STAT_COUNT
|
|
|
|
|
};
|
|
|
|
|
|
2013-06-29 04:47:12 +08:00
|
|
|
/* Maximum number of TX PIO buffers we may allocate to a function.
|
|
|
|
|
* This matches the total number of buffers on each SFC9100-family
|
|
|
|
|
* controller.
|
|
|
|
|
*/
|
|
|
|
|
#define EF10_TX_PIOBUF_COUNT 16
|
|
|
|
|
|
2013-08-30 02:19:29 +08:00
|
|
|
/**
|
|
|
|
|
* struct efx_ef10_nic_data - EF10 architecture NIC state
|
|
|
|
|
* @mcdi_buf: DMA buffer for MCDI
|
|
|
|
|
* @warm_boot_count: Last seen MC warm boot count
|
|
|
|
|
* @vi_base: Absolute index of first VI in this function
|
|
|
|
|
* @n_allocated_vis: Number of VIs allocated to this function
|
|
|
|
|
* @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
|
|
|
|
|
* @must_restore_filters: Flag: filters have yet to be restored after MC reboot
|
2013-06-29 04:47:12 +08:00
|
|
|
* @n_piobufs: Number of PIO buffers allocated to this function
|
|
|
|
|
* @wc_membase: Base address of write-combining mapping of the memory BAR
|
|
|
|
|
* @pio_write_base: Base address for writing PIO buffers
|
|
|
|
|
* @pio_write_vi_base: Relative VI number for @pio_write_base
|
|
|
|
|
* @piobuf_handle: Handle of each PIO buffer allocated
|
2017-01-14 05:20:29 +08:00
|
|
|
* @piobuf_size: size of a single PIO buffer
|
2013-06-29 04:47:12 +08:00
|
|
|
* @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
|
|
|
|
|
* reboot
|
2013-08-30 02:19:29 +08:00
|
|
|
* @rx_rss_context: Firmware handle for our RSS context
|
2015-05-06 07:59:38 +08:00
|
|
|
* @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared
|
2013-08-30 02:19:29 +08:00
|
|
|
* @stats: Hardware statistics
|
|
|
|
|
* @workaround_35388: Flag: firmware supports workaround for bug 35388
|
2015-07-21 22:09:18 +08:00
|
|
|
* @workaround_26807: Flag: firmware supports workaround for bug 26807
|
2016-08-11 20:02:09 +08:00
|
|
|
* @workaround_61265: Flag: firmware supports workaround for bug 61265
|
2013-09-06 05:51:55 +08:00
|
|
|
* @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
|
|
|
|
|
* after MC reboot
|
2013-08-30 02:19:29 +08:00
|
|
|
* @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
|
|
|
|
|
* %MC_CMD_GET_CAPABILITIES response)
|
2016-08-11 20:01:35 +08:00
|
|
|
* @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
|
|
|
|
|
* %MC_CMD_GET_CAPABILITIES response)
|
2015-05-06 07:56:55 +08:00
|
|
|
* @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
|
|
|
|
|
* @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
|
2015-05-06 07:57:14 +08:00
|
|
|
* @vport_id: The function's vport ID, only relevant for PFs
|
2015-05-06 07:57:34 +08:00
|
|
|
* @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
|
2015-05-06 07:57:53 +08:00
|
|
|
* @pf_index: The number for this PF, or the parent PF if this is a VF
|
2015-05-06 07:58:31 +08:00
|
|
|
#ifdef CONFIG_SFC_SRIOV
|
|
|
|
|
* @vf: Pointer to VF data structure
|
|
|
|
|
#endif
|
2016-06-16 00:48:14 +08:00
|
|
|
* @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
|
|
|
|
|
* @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
|
|
|
|
|
* @vlan_lock: Lock to serialize access to vlan_list.
|
2017-02-09 00:52:10 +08:00
|
|
|
* @udp_tunnels: UDP tunnel port numbers and types.
|
|
|
|
|
* @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
|
|
|
|
|
* @udp_tunnels to hardware and thus the push must be re-done.
|
|
|
|
|
* @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
|
2013-08-30 02:19:29 +08:00
|
|
|
*/
|
|
|
|
|
struct efx_ef10_nic_data {
|
|
|
|
|
struct efx_buffer mcdi_buf;
|
|
|
|
|
u16 warm_boot_count;
|
|
|
|
|
unsigned int vi_base;
|
|
|
|
|
unsigned int n_allocated_vis;
|
|
|
|
|
bool must_realloc_vis;
|
|
|
|
|
bool must_restore_filters;
|
2013-06-29 04:47:12 +08:00
|
|
|
unsigned int n_piobufs;
|
|
|
|
|
void __iomem *wc_membase, *pio_write_base;
|
|
|
|
|
unsigned int pio_write_vi_base;
|
|
|
|
|
unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
|
2017-01-14 05:20:29 +08:00
|
|
|
u16 piobuf_size;
|
2013-06-29 04:47:12 +08:00
|
|
|
bool must_restore_piobufs;
|
2013-08-30 02:19:29 +08:00
|
|
|
u32 rx_rss_context;
|
2015-05-06 07:59:38 +08:00
|
|
|
bool rx_rss_context_exclusive;
|
2013-08-30 02:19:29 +08:00
|
|
|
u64 stats[EF10_STAT_COUNT];
|
|
|
|
|
bool workaround_35388;
|
2015-07-21 22:09:18 +08:00
|
|
|
bool workaround_26807;
|
2016-08-11 20:02:09 +08:00
|
|
|
bool workaround_61265;
|
2013-09-06 05:51:55 +08:00
|
|
|
bool must_check_datapath_caps;
|
2013-08-30 02:19:29 +08:00
|
|
|
u32 datapath_caps;
|
2016-08-11 20:01:35 +08:00
|
|
|
u32 datapath_caps2;
|
2015-05-06 07:56:55 +08:00
|
|
|
unsigned int rx_dpcpu_fw_id;
|
|
|
|
|
unsigned int tx_dpcpu_fw_id;
|
2015-05-06 07:57:14 +08:00
|
|
|
unsigned int vport_id;
|
2015-05-06 07:57:34 +08:00
|
|
|
bool must_probe_vswitching;
|
2015-05-06 07:57:53 +08:00
|
|
|
unsigned int pf_index;
|
2015-06-02 18:38:16 +08:00
|
|
|
u8 port_id[ETH_ALEN];
|
2015-05-06 07:58:31 +08:00
|
|
|
#ifdef CONFIG_SFC_SRIOV
|
2015-05-20 18:09:15 +08:00
|
|
|
unsigned int vf_index;
|
2015-05-06 07:58:31 +08:00
|
|
|
struct ef10_vf *vf;
|
|
|
|
|
#endif
|
|
|
|
|
u8 vport_mac[ETH_ALEN];
|
2016-06-16 00:48:14 +08:00
|
|
|
struct list_head vlan_list;
|
|
|
|
|
struct mutex vlan_lock;
|
2017-02-09 00:52:10 +08:00
|
|
|
struct efx_udp_tunnel udp_tunnels[16];
|
|
|
|
|
bool udp_tunnels_dirty;
|
|
|
|
|
struct mutex udp_tunnels_lock;
|
2013-08-30 02:19:29 +08:00
|
|
|
};
|
|
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_init_sriov(void);
|
|
|
|
|
void efx_fini_sriov(void);
|
sfc: Add SR-IOV back-end support for SFC9000 family
On the SFC9000 family, each port has 1024 Virtual Interfaces (VIs),
each with an RX queue, a TX queue, an event queue and a mailbox
register. These may be assigned to up to 127 SR-IOV virtual functions
per port, with up to 64 VIs per VF.
We allocate an extra channel (IRQ and event queue only) to receive
requests from VF drivers.
There is a per-port limit of 4 concurrent RX queue flushes, and queue
flushes may be initiated by the MC in response to a Function Level
Reset (FLR) of a VF. Therefore, when SR-IOV is in use, we submit all
flush requests via the MC.
The RSS indirection table is shared with VFs, so the number of RX
queues used in the PF is limited to the number of VIs per VF.
This is almost entirely the work of Steve Hodgson, formerly
shodgson@solarflare.com.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
2012-02-14 08:48:07 +08:00
|
|
|
|
2012-09-03 18:09:36 +08:00
|
|
|
struct ethtool_ts_info;
|
2013-10-16 00:54:56 +08:00
|
|
|
int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
|
|
|
|
|
void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
|
|
|
|
|
void efx_ptp_remove(struct efx_nic *efx);
|
2013-11-14 09:26:21 +08:00
|
|
|
int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
|
|
|
|
|
int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
|
|
|
|
|
bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
|
2013-11-22 01:11:25 +08:00
|
|
|
int efx_ptp_get_mode(struct efx_nic *efx);
|
|
|
|
|
int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
|
|
|
|
|
unsigned int new_mode);
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
|
|
|
|
|
void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
|
2013-12-11 10:36:08 +08:00
|
|
|
size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings);
|
|
|
|
|
size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats);
|
2013-11-18 20:54:41 +08:00
|
|
|
void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
|
|
|
|
|
void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
|
|
|
|
|
struct sk_buff *skb);
|
|
|
|
|
static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
|
|
|
|
|
struct sk_buff *skb)
|
|
|
|
|
{
|
|
|
|
|
if (channel->sync_events_state == SYNC_EVENTS_VALID)
|
|
|
|
|
__efx_rx_skb_attach_timestamp(channel, skb);
|
|
|
|
|
}
|
2013-11-08 18:20:31 +08:00
|
|
|
void efx_ptp_start_datapath(struct efx_nic *efx);
|
|
|
|
|
void efx_ptp_stop_datapath(struct efx_nic *efx);
|
2018-01-26 01:24:56 +08:00
|
|
|
bool efx_ptp_use_mac_tx_timestamps(struct efx_nic *efx);
|
2018-01-26 01:24:43 +08:00
|
|
|
ktime_t efx_ptp_nic_to_kernel_time(struct efx_tx_queue *tx_queue);
|
2012-09-03 18:09:36 +08:00
|
|
|
|
2011-04-14 13:50:12 +08:00
|
|
|
extern const struct efx_nic_type falcon_a1_nic_type;
|
|
|
|
|
extern const struct efx_nic_type falcon_b0_nic_type;
|
|
|
|
|
extern const struct efx_nic_type siena_a0_nic_type;
|
2013-08-30 02:19:29 +08:00
|
|
|
extern const struct efx_nic_type efx_hunt_a0_nic_type;
|
2015-05-06 07:58:14 +08:00
|
|
|
extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
|
2008-04-27 19:55:59 +08:00
|
|
|
|
|
|
|
|
/**************************************************************************
|
|
|
|
|
*
|
|
|
|
|
* Externs
|
|
|
|
|
*
|
|
|
|
|
**************************************************************************
|
|
|
|
|
*/
|
|
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
|
2009-10-23 16:29:51 +08:00
|
|
|
|
2008-04-27 19:55:59 +08:00
|
|
|
/* TX data path */
|
2013-08-22 02:51:04 +08:00
|
|
|
static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
|
|
|
|
|
{
|
|
|
|
|
return tx_queue->efx->type->tx_probe(tx_queue);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
|
|
|
|
|
{
|
|
|
|
|
tx_queue->efx->type->tx_init(tx_queue);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
|
|
|
|
|
{
|
|
|
|
|
tx_queue->efx->type->tx_remove(tx_queue);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
|
|
|
|
|
{
|
|
|
|
|
tx_queue->efx->type->tx_write(tx_queue);
|
|
|
|
|
}
|
2008-04-27 19:55:59 +08:00
|
|
|
|
|
|
|
|
/* RX data path */
|
2013-08-22 02:51:04 +08:00
|
|
|
static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
|
|
|
|
|
{
|
|
|
|
|
return rx_queue->efx->type->rx_probe(rx_queue);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
|
|
|
|
|
{
|
|
|
|
|
rx_queue->efx->type->rx_init(rx_queue);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
|
|
|
|
|
{
|
|
|
|
|
rx_queue->efx->type->rx_remove(rx_queue);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
|
|
|
|
|
{
|
|
|
|
|
rx_queue->efx->type->rx_write(rx_queue);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
|
|
|
|
|
{
|
|
|
|
|
rx_queue->efx->type->rx_defer_refill(rx_queue);
|
|
|
|
|
}
|
2008-04-27 19:55:59 +08:00
|
|
|
|
|
|
|
|
/* Event data path */
|
2013-08-22 02:51:04 +08:00
|
|
|
static inline int efx_nic_probe_eventq(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
return channel->efx->type->ev_probe(channel);
|
|
|
|
|
}
|
2013-04-16 01:51:54 +08:00
|
|
|
static inline int efx_nic_init_eventq(struct efx_channel *channel)
|
2013-08-22 02:51:04 +08:00
|
|
|
{
|
2013-04-16 01:51:54 +08:00
|
|
|
return channel->efx->type->ev_init(channel);
|
2013-08-22 02:51:04 +08:00
|
|
|
}
|
|
|
|
|
static inline void efx_nic_fini_eventq(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
channel->efx->type->ev_fini(channel);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_remove_eventq(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
channel->efx->type->ev_remove(channel);
|
|
|
|
|
}
|
|
|
|
|
static inline int
|
|
|
|
|
efx_nic_process_eventq(struct efx_channel *channel, int quota)
|
|
|
|
|
{
|
|
|
|
|
return channel->efx->type->ev_process(channel, quota);
|
|
|
|
|
}
|
|
|
|
|
static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
|
|
|
|
|
{
|
|
|
|
|
channel->efx->type->ev_read_ack(channel);
|
|
|
|
|
}
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_nic_event_test_start(struct efx_channel *channel);
|
2013-08-22 02:51:04 +08:00
|
|
|
|
|
|
|
|
/* Falcon/Siena queue operations */
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
|
|
|
|
|
void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
|
2016-11-17 18:51:54 +08:00
|
|
|
unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
|
|
|
|
|
dma_addr_t dma_addr, unsigned int len);
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
|
|
|
|
|
void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
|
|
|
|
|
int efx_farch_ev_probe(struct efx_channel *channel);
|
|
|
|
|
int efx_farch_ev_init(struct efx_channel *channel);
|
|
|
|
|
void efx_farch_ev_fini(struct efx_channel *channel);
|
|
|
|
|
void efx_farch_ev_remove(struct efx_channel *channel);
|
|
|
|
|
int efx_farch_ev_process(struct efx_channel *channel, int quota);
|
|
|
|
|
void efx_farch_ev_read_ack(struct efx_channel *channel);
|
|
|
|
|
void efx_farch_ev_test_generate(struct efx_channel *channel);
|
2013-08-22 02:51:04 +08:00
|
|
|
|
2012-11-08 09:46:53 +08:00
|
|
|
/* Falcon/Siena filter operations */
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_filter_table_probe(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_filter_table_restore(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_filter_table_remove(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
|
|
|
|
|
s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
|
|
|
|
|
bool replace);
|
|
|
|
|
int efx_farch_filter_remove_safe(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority,
|
|
|
|
|
u32 filter_id);
|
|
|
|
|
int efx_farch_filter_get_safe(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority, u32 filter_id,
|
|
|
|
|
struct efx_filter_spec *);
|
2013-11-22 03:15:03 +08:00
|
|
|
int efx_farch_filter_clear_rx(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority);
|
2013-09-24 02:37:59 +08:00
|
|
|
u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority);
|
|
|
|
|
u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
|
|
|
|
|
s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
|
|
|
|
|
enum efx_filter_priority priority, u32 *buf,
|
|
|
|
|
u32 size);
|
2012-11-08 09:46:53 +08:00
|
|
|
#ifdef CONFIG_RFS_ACCEL
|
2013-09-24 02:37:59 +08:00
|
|
|
s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
|
|
|
|
|
struct efx_filter_spec *spec);
|
|
|
|
|
bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
|
|
|
|
|
unsigned int index);
|
2012-11-08 09:46:53 +08:00
|
|
|
#endif
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
|
2012-11-08 09:46:53 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
bool efx_nic_event_present(struct efx_channel *channel);
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2012-07-05 05:25:07 +08:00
|
|
|
/* Some statistics are computed as A - B where A and B each increase
|
|
|
|
|
* linearly with some hardware counter(s) and the counters are read
|
|
|
|
|
* asynchronously. If the counters contributing to B are always read
|
|
|
|
|
* after those contributing to A, the computed value may be lower than
|
|
|
|
|
* the true value by some variable amount, and may decrease between
|
|
|
|
|
* subsequent computations.
|
|
|
|
|
*
|
|
|
|
|
* We should never allow statistics to decrease or to exceed the true
|
|
|
|
|
* value. Since the computed value will never be greater than the
|
|
|
|
|
* true value, we can achieve this by only storing the computed value
|
|
|
|
|
* when it increases.
|
|
|
|
|
*/
|
|
|
|
|
static inline void efx_update_diff_stat(u64 *stat, u64 diff)
|
|
|
|
|
{
|
|
|
|
|
if ((s64)(diff - *stat) > 0)
|
|
|
|
|
*stat = diff;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-22 02:51:04 +08:00
|
|
|
/* Interrupts */
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_nic_init_interrupt(struct efx_nic *efx);
|
2016-08-26 22:13:30 +08:00
|
|
|
int efx_nic_irq_test_start(struct efx_nic *efx);
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_nic_fini_interrupt(struct efx_nic *efx);
|
2013-08-22 02:51:04 +08:00
|
|
|
|
|
|
|
|
/* Falcon/Siena interrupts */
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_irq_enable_master(struct efx_nic *efx);
|
2016-08-26 22:13:30 +08:00
|
|
|
int efx_farch_irq_test_generate(struct efx_nic *efx);
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_irq_disable_master(struct efx_nic *efx);
|
|
|
|
|
irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
|
|
|
|
|
irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
|
|
|
|
|
irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
|
2009-11-29 11:43:56 +08:00
|
|
|
|
2012-02-29 07:37:35 +08:00
|
|
|
static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
|
|
|
|
|
{
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 05:07:29 +08:00
|
|
|
return READ_ONCE(channel->event_test_cpu);
|
2012-02-29 07:37:35 +08:00
|
|
|
}
|
|
|
|
|
static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
|
|
|
|
|
{
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 05:07:29 +08:00
|
|
|
return READ_ONCE(efx->last_irq_cpu);
|
2012-02-29 07:37:35 +08:00
|
|
|
}
|
|
|
|
|
|
2008-04-27 19:55:59 +08:00
|
|
|
/* Global Resources */
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_nic_flush_queues(struct efx_nic *efx);
|
|
|
|
|
void siena_prepare_flush(struct efx_nic *efx);
|
|
|
|
|
int efx_farch_fini_dmaq(struct efx_nic *efx);
|
sfc:On MCDI timeout, issue an FLR (and mark MCDI to fail-fast)
When an MCDI command times out (whether or not we find it
completed when we poll), call efx_mcdi_abandon(), which tells
all subsequent MCDI calls to fail-fast, and queues up an FLR.
Because an FLR doesn't lead to receiving any reboot even from
the MC (unlike most other types of reset), we have to call
efx_ef10_reset_mc_allocations.
In efx_start_all(), if a reset (of any kind) is pending, we
bail out.
Without this, attempts to reconfigure (e.g. change mtu) can
cause driver/mc state inconsistency if the first MCDI call
triggers an FLR.
For similar reasons, on EF10, in
efx_reset_down(method=RESET_TYPE_MCDI_TIMEOUT), set the number
of active queues to zero before calling efx_stop_all().
And, on farch, in efx_reset_up(method=RESET_TYPE_MCDI_TIMEOUT),
set active_queues and flushes pending & outstanding to zero.
efx_mcdi_mode_{poll,event}() should not take us out of fail-fast
mode. Instead, this is done by efx_mcdi_reset() after the FLR
completes.
The new FLR reset_type RESET_TYPE_MCDI_TIMEOUT doesn't really
fit into the hierarchy of reset 'scopes' whereby efx_reset()
decides some resets subsume others. Thus, it uses separate logic.
Also, fixed up some inconsistency around RESET_TYPE_MC_BIST,
which was in the wrong place in that hierarchy.
Signed-off-by: Shradha Shah <sshah@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-04-17 02:27:48 +08:00
|
|
|
void efx_farch_finish_flr(struct efx_nic *efx);
|
2013-09-24 02:37:59 +08:00
|
|
|
void siena_finish_flush(struct efx_nic *efx);
|
|
|
|
|
void falcon_start_nic_stats(struct efx_nic *efx);
|
|
|
|
|
void falcon_stop_nic_stats(struct efx_nic *efx);
|
|
|
|
|
int falcon_reset_xaui(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
|
|
|
|
|
void efx_farch_init_common(struct efx_nic *efx);
|
|
|
|
|
void efx_ef10_handle_drain_event(struct efx_nic *efx);
|
|
|
|
|
void efx_farch_rx_push_indir_table(struct efx_nic *efx);
|
2017-01-17 20:02:12 +08:00
|
|
|
void efx_farch_rx_pull_indir_table(struct efx_nic *efx);
|
2009-11-29 11:43:56 +08:00
|
|
|
|
|
|
|
|
int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
|
2012-09-19 04:59:52 +08:00
|
|
|
unsigned int len, gfp_t gfp_flags);
|
2009-11-29 11:43:56 +08:00
|
|
|
void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2008-09-01 19:49:02 +08:00
|
|
|
/* Tests */
|
2013-08-22 02:51:04 +08:00
|
|
|
struct efx_farch_register_test {
|
2009-11-29 11:43:56 +08:00
|
|
|
unsigned address;
|
|
|
|
|
efx_oword_t mask;
|
|
|
|
|
};
|
2013-09-24 02:37:59 +08:00
|
|
|
int efx_farch_test_registers(struct efx_nic *efx,
|
|
|
|
|
const struct efx_farch_register_test *regs,
|
|
|
|
|
size_t n_regs);
|
2008-09-01 19:49:02 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
size_t efx_nic_get_regs_len(struct efx_nic *efx);
|
|
|
|
|
void efx_nic_get_regs(struct efx_nic *efx, void *buf);
|
2010-06-21 11:06:53 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
|
|
|
|
|
const unsigned long *mask, u8 *names);
|
|
|
|
|
void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
|
|
|
|
|
const unsigned long *mask, u64 *stats,
|
|
|
|
|
const void *dma_buf, bool accumulate);
|
2013-10-01 00:36:50 +08:00
|
|
|
void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
|
2012-12-15 05:52:56 +08:00
|
|
|
|
2012-09-13 08:11:31 +08:00
|
|
|
#define EFX_MAX_FLUSH_TIME 5000
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2013-09-24 02:37:59 +08:00
|
|
|
void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
|
|
|
|
|
efx_qword_t *event);
|
2008-04-27 19:55:59 +08:00
|
|
|
|
2009-11-29 23:12:08 +08:00
|
|
|
#endif /* EFX_NIC_H */
|