2009-06-05 20:42:42 +08:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2009-06-05 20:42:42 +08:00
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#include <drm/drmP.h>
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#include "radeon.h"
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2010-03-12 05:19:17 +08:00
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#include "radeon_asic.h"
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2009-10-01 16:20:52 +08:00
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#include "rs400d.h"
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2009-06-05 20:42:42 +08:00
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2009-10-01 16:20:52 +08:00
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/* This files gather functions specifics to : rs400,rs480 */
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static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
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2009-06-05 20:42:42 +08:00
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void rs400_gart_adjust_size(struct radeon_device *rdev)
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{
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/* Check gart size */
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switch (rdev->mc.gtt_size/(1024*1024)) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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case 1024:
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case 2048:
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break;
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default:
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DRM_ERROR("Unable to use IGP GART size %uM\n",
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2009-09-08 08:10:24 +08:00
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(unsigned)(rdev->mc.gtt_size >> 20));
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2009-06-05 20:42:42 +08:00
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DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
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DRM_ERROR("Forcing to 32M GART size\n");
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rdev->mc.gtt_size = 32 * 1024 * 1024;
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return;
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}
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}
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void rs400_gart_tlb_flush(struct radeon_device *rdev)
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{
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uint32_t tmp;
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unsigned int timeout = rdev->usec_timeout;
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WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
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do {
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tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
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if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
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break;
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DRM_UDELAY(1);
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timeout--;
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} while (timeout > 0);
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WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
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}
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2009-09-15 00:29:49 +08:00
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int rs400_gart_init(struct radeon_device *rdev)
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2009-06-05 20:42:42 +08:00
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{
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int r;
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2011-11-03 23:16:49 +08:00
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if (rdev->gart.ptr) {
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2010-10-31 05:08:30 +08:00
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WARN(1, "RS400 GART already initialized\n");
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2009-09-15 00:29:49 +08:00
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return 0;
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}
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/* Check gart size */
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switch(rdev->mc.gtt_size / (1024 * 1024)) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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case 1024:
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case 2048:
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break;
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default:
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return -EINVAL;
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}
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2009-06-05 20:42:42 +08:00
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/* Initialize common gart structure */
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r = radeon_gart_init(rdev);
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2009-09-15 00:29:49 +08:00
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if (r)
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2009-06-05 20:42:42 +08:00
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return r;
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2009-09-15 00:29:49 +08:00
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if (rs400_debugfs_pcie_gart_info_init(rdev))
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2009-06-05 20:42:42 +08:00
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DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
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2009-09-15 00:29:49 +08:00
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rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
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return radeon_gart_table_ram_alloc(rdev);
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}
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int rs400_gart_enable(struct radeon_device *rdev)
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{
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uint32_t size_reg;
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uint32_t tmp;
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2009-06-05 20:42:42 +08:00
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
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/* Check gart size */
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switch(rdev->mc.gtt_size / (1024 * 1024)) {
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case 32:
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size_reg = RS480_VA_SIZE_32MB;
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break;
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case 64:
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size_reg = RS480_VA_SIZE_64MB;
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break;
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case 128:
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size_reg = RS480_VA_SIZE_128MB;
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break;
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case 256:
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size_reg = RS480_VA_SIZE_256MB;
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break;
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case 512:
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size_reg = RS480_VA_SIZE_512MB;
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break;
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case 1024:
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size_reg = RS480_VA_SIZE_1GB;
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break;
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case 2048:
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size_reg = RS480_VA_SIZE_2GB;
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break;
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default:
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return -EINVAL;
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}
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/* It should be fine to program it to max value */
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if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
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WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
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WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
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} else {
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WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
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WREG32(RS480_AGP_BASE_2, 0);
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}
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drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18 05:54:29 +08:00
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tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
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tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
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2009-06-05 20:42:42 +08:00
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if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
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WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
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tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
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WREG32(RADEON_BUS_CNTL, tmp);
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} else {
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WREG32(RADEON_MC_AGP_LOCATION, tmp);
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tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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WREG32(RADEON_BUS_CNTL, tmp);
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}
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/* Table should be in 32bits address space so ignore bits above. */
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2009-06-29 16:29:11 +08:00
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tmp = (u32)rdev->gart.table_addr & 0xfffff000;
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tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
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2009-06-05 20:42:42 +08:00
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WREG32_MC(RS480_GART_BASE, tmp);
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/* TODO: more tweaking here */
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WREG32_MC(RS480_GART_FEATURE_ID,
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(RS480_TLB_ENABLE |
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RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
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/* Disable snooping */
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WREG32_MC(RS480_AGP_MODE_CNTL,
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(1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
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/* Disable AGP mode */
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/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
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* AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
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if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
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2013-08-27 05:52:12 +08:00
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tmp = RREG32_MC(RS480_MC_MISC_CNTL);
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tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
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WREG32_MC(RS480_MC_MISC_CNTL, tmp);
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2009-06-05 20:42:42 +08:00
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} else {
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2013-08-27 05:52:12 +08:00
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tmp = RREG32_MC(RS480_MC_MISC_CNTL);
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tmp |= RS480_GART_INDEX_REG_EN;
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WREG32_MC(RS480_MC_MISC_CNTL, tmp);
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2009-06-05 20:42:42 +08:00
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}
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/* Enable gart */
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WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
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rs400_gart_tlb_flush(rdev);
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2011-09-01 05:54:07 +08:00
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DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
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(unsigned)(rdev->mc.gtt_size >> 20),
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(unsigned long long)rdev->gart.table_addr);
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2009-06-05 20:42:42 +08:00
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rdev->gart.ready = true;
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return 0;
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}
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void rs400_gart_disable(struct radeon_device *rdev)
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{
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uint32_t tmp;
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
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WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
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}
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2009-09-15 00:29:49 +08:00
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void rs400_gart_fini(struct radeon_device *rdev)
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{
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2010-03-17 22:44:29 +08:00
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radeon_gart_fini(rdev);
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2009-09-15 00:29:49 +08:00
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rs400_gart_disable(rdev);
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radeon_gart_table_ram_free(rdev);
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}
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2014-07-17 18:01:07 +08:00
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#define RS400_PTE_UNSNOOPED (1 << 0)
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2011-01-25 12:24:59 +08:00
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#define RS400_PTE_WRITEABLE (1 << 2)
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#define RS400_PTE_READABLE (1 << 3)
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2015-01-21 16:36:35 +08:00
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uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
|
2009-06-05 20:42:42 +08:00
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{
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2009-06-29 16:29:11 +08:00
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uint32_t entry;
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entry = (lower_32_bits(addr) & PAGE_MASK) |
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2014-07-17 18:01:07 +08:00
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((upper_32_bits(addr) & 0xff) << 4);
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if (flags & RADEON_GART_PAGE_READ)
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2014-09-19 09:22:46 +08:00
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entry |= RS400_PTE_READABLE;
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2014-07-17 18:01:07 +08:00
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if (flags & RADEON_GART_PAGE_WRITE)
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2014-09-19 09:22:46 +08:00
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entry |= RS400_PTE_WRITEABLE;
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2014-07-17 18:01:07 +08:00
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if (!(flags & RADEON_GART_PAGE_SNOOP))
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entry |= RS400_PTE_UNSNOOPED;
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2015-01-21 16:36:35 +08:00
|
|
|
return entry;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
|
|
|
|
|
uint64_t entry)
|
|
|
|
|
{
|
|
|
|
|
u32 *gtt = rdev->gart.ptr;
|
|
|
|
|
gtt[i] = cpu_to_le32(lower_32_bits(entry));
|
2009-06-05 20:42:42 +08:00
|
|
|
}
|
|
|
|
|
|
2010-02-05 11:41:54 +08:00
|
|
|
int rs400_mc_wait_for_idle(struct radeon_device *rdev)
|
|
|
|
|
{
|
|
|
|
|
unsigned i;
|
|
|
|
|
uint32_t tmp;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < rdev->usec_timeout; i++) {
|
|
|
|
|
/* read MC_STATUS */
|
2011-01-25 12:24:59 +08:00
|
|
|
tmp = RREG32(RADEON_MC_STATUS);
|
|
|
|
|
if (tmp & RADEON_MC_IDLE) {
|
2010-02-05 11:41:54 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
DRM_UDELAY(1);
|
|
|
|
|
}
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
2012-09-01 01:43:50 +08:00
|
|
|
static void rs400_gpu_init(struct radeon_device *rdev)
|
2009-06-05 20:42:42 +08:00
|
|
|
{
|
|
|
|
|
/* FIXME: is this correct ? */
|
|
|
|
|
r420_pipes_init(rdev);
|
2010-02-05 11:41:54 +08:00
|
|
|
if (rs400_mc_wait_for_idle(rdev)) {
|
2017-02-28 20:55:52 +08:00
|
|
|
pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n",
|
|
|
|
|
RREG32(RADEON_MC_STATUS));
|
2009-06-05 20:42:42 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-09-01 01:43:50 +08:00
|
|
|
static void rs400_mc_init(struct radeon_device *rdev)
|
2009-06-05 20:42:42 +08:00
|
|
|
{
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18 05:54:29 +08:00
|
|
|
u64 base;
|
|
|
|
|
|
2009-06-05 20:42:42 +08:00
|
|
|
rs400_gart_adjust_size(rdev);
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18 05:54:29 +08:00
|
|
|
rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
|
2009-06-05 20:42:42 +08:00
|
|
|
/* DDR for all card after R300 & IGP */
|
|
|
|
|
rdev->mc.vram_is_ddr = true;
|
|
|
|
|
rdev->mc.vram_width = 128;
|
2009-07-11 02:44:47 +08:00
|
|
|
r100_vram_init_sizes(rdev);
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18 05:54:29 +08:00
|
|
|
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
|
|
|
|
|
radeon_vram_location(rdev, &rdev->mc, base);
|
2010-07-15 22:51:10 +08:00
|
|
|
rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18 05:54:29 +08:00
|
|
|
radeon_gtt_location(rdev, &rdev->mc);
|
2010-03-21 23:09:24 +08:00
|
|
|
radeon_update_bandwidth_info(rdev);
|
2009-06-05 20:42:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
|
|
|
{
|
2013-09-04 07:00:09 +08:00
|
|
|
unsigned long flags;
|
2009-06-05 20:42:42 +08:00
|
|
|
uint32_t r;
|
|
|
|
|
|
2013-09-04 07:00:09 +08:00
|
|
|
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
|
2009-06-05 20:42:42 +08:00
|
|
|
WREG32(RS480_NB_MC_INDEX, reg & 0xff);
|
|
|
|
|
r = RREG32(RS480_NB_MC_DATA);
|
|
|
|
|
WREG32(RS480_NB_MC_INDEX, 0xff);
|
2013-09-04 07:00:09 +08:00
|
|
|
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
|
2009-06-05 20:42:42 +08:00
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
|
|
|
{
|
2013-09-04 07:00:09 +08:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
|
2009-06-05 20:42:42 +08:00
|
|
|
WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
|
|
|
|
|
WREG32(RS480_NB_MC_DATA, (v));
|
|
|
|
|
WREG32(RS480_NB_MC_INDEX, 0xff);
|
2013-09-04 07:00:09 +08:00
|
|
|
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
|
2009-06-05 20:42:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
|
static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
uint32_t tmp;
|
|
|
|
|
|
|
|
|
|
tmp = RREG32(RADEON_HOST_PATH_CNTL);
|
|
|
|
|
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32(RADEON_BUS_CNTL);
|
|
|
|
|
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
|
|
|
|
|
seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
|
|
|
|
|
if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
|
|
|
|
|
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
|
|
|
|
|
seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
|
|
|
|
|
seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
|
|
|
|
|
seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
|
2011-01-25 12:24:59 +08:00
|
|
|
tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
|
2009-06-05 20:42:42 +08:00
|
|
|
seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
|
2011-01-25 12:24:59 +08:00
|
|
|
tmp = RREG32(RS690_HDP_FB_LOCATION);
|
2009-06-05 20:42:42 +08:00
|
|
|
seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
|
|
|
|
|
} else {
|
|
|
|
|
tmp = RREG32(RADEON_AGP_BASE);
|
|
|
|
|
seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32(RS480_AGP_BASE_2);
|
|
|
|
|
seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32(RADEON_MC_AGP_LOCATION);
|
|
|
|
|
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
|
|
|
|
|
}
|
|
|
|
|
tmp = RREG32_MC(RS480_GART_BASE);
|
|
|
|
|
seq_printf(m, "GART_BASE 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS480_GART_FEATURE_ID);
|
|
|
|
|
seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
|
|
|
|
|
seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS480_MC_MISC_CNTL);
|
|
|
|
|
seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x5F);
|
|
|
|
|
seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
|
|
|
|
|
seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
|
|
|
|
|
seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x3B);
|
|
|
|
|
seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x3C);
|
|
|
|
|
seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x30);
|
|
|
|
|
seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x31);
|
|
|
|
|
seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x32);
|
|
|
|
|
seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x33);
|
|
|
|
|
seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x34);
|
|
|
|
|
seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x35);
|
|
|
|
|
seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x36);
|
|
|
|
|
seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
|
|
|
|
|
tmp = RREG32_MC(0x37);
|
|
|
|
|
seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct drm_info_list rs400_gart_info_list[] = {
|
|
|
|
|
{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
|
|
|
|
|
};
|
|
|
|
|
#endif
|
|
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
|
2009-06-05 20:42:42 +08:00
|
|
|
{
|
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
|
return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
|
|
|
|
|
#else
|
|
|
|
|
return 0;
|
|
|
|
|
#endif
|
|
|
|
|
}
|
2009-10-01 16:20:52 +08:00
|
|
|
|
2012-09-01 01:43:50 +08:00
|
|
|
static void rs400_mc_program(struct radeon_device *rdev)
|
2009-10-01 16:20:52 +08:00
|
|
|
{
|
|
|
|
|
struct r100_mc_save save;
|
|
|
|
|
|
|
|
|
|
/* Stops all mc clients */
|
|
|
|
|
r100_mc_stop(rdev, &save);
|
|
|
|
|
|
|
|
|
|
/* Wait for mc idle */
|
2010-02-05 11:41:54 +08:00
|
|
|
if (rs400_mc_wait_for_idle(rdev))
|
|
|
|
|
dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
|
2009-10-01 16:20:52 +08:00
|
|
|
WREG32(R_000148_MC_FB_LOCATION,
|
|
|
|
|
S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
|
|
|
|
|
S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
|
|
|
|
|
|
|
|
|
|
r100_mc_resume(rdev, &save);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rs400_startup(struct radeon_device *rdev)
|
|
|
|
|
{
|
|
|
|
|
int r;
|
|
|
|
|
|
2010-03-31 11:42:50 +08:00
|
|
|
r100_set_common_regs(rdev);
|
|
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
rs400_mc_program(rdev);
|
|
|
|
|
/* Resume clock */
|
|
|
|
|
r300_clock_startup(rdev);
|
|
|
|
|
/* Initialize GPU configuration (# pipes, ...) */
|
|
|
|
|
rs400_gpu_init(rdev);
|
2009-11-05 13:36:53 +08:00
|
|
|
r100_enable_bm(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
/* Initialize GART (initialize after TTM so we can allocate
|
|
|
|
|
* memory through TTM but finalize after TTM) */
|
|
|
|
|
r = rs400_gart_enable(rdev);
|
|
|
|
|
if (r)
|
|
|
|
|
return r;
|
2010-08-28 06:25:25 +08:00
|
|
|
|
|
|
|
|
/* allocate wb buffer */
|
|
|
|
|
r = radeon_wb_init(rdev);
|
|
|
|
|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
|
2011-11-21 04:45:34 +08:00
|
|
|
r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
|
|
|
|
if (r) {
|
|
|
|
|
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
/* Enable IRQ */
|
radeon: Fix system hang issue when using KMS with older cards
The current radeon driver initialization routines, when using KMS, are written
so that the IRQ installation routine is called before initializing the WB buffer
and the CP rings. With some ASICs, though, the IRQ routine tries to access the
GFX_INDEX ring causing a call to RREG32 with the value of -1 in
radeon_fence_read. This, in turn causes the system to completely hang with some
cards, requiring a hard reset.
A call stack that can cause such a hang looks like this (using rv515 ASIC for the
example here):
* rv515_init (rv515.c)
* radeon_irq_kms_init (radeon_irq_kms.c)
* drm_irq_install (drm_irq.c)
* radeon_driver_irq_preinstall_kms (radeon_irq_kms.c)
* rs600_irq_process (rs600.c)
* radeon_fence_process - due to SW interrupt (radeon_fence.c)
* radeon_fence_read (radeon_fence.c)
* hang due to RREG32(-1)
The patch moves the IRQ installation to the card startup routine, after the ring
has been initialized, but before the IRQ has been set. This fixes the issue, but
requires a check to see if the IRQ is already installed, as is the case in the
system resume codepath.
I have tested the patch on three machines using the rv515, the rv770 and the
evergreen ASIC. They worked without issues.
This seems to be a known issue and has been reported on several bug tracking
sites by various distributions (see links below). Most of reports recommend
booting the system with KMS disabled and then enabling KMS by reloading the
radeon module. For some reason, this was indeed a usable workaround, however,
UMS is now deprecated and disabled by default.
Bug reports:
https://bugzilla.redhat.com/show_bug.cgi?id=845745
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/561789
https://bbs.archlinux.org/viewtopic.php?id=156964
Signed-off-by: Adis Hamzić <adis@hamzadis.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-06-02 22:47:54 +08:00
|
|
|
if (!rdev->irq.installed) {
|
|
|
|
|
r = radeon_irq_kms_init(rdev);
|
|
|
|
|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
r100_irq_set(rdev);
|
2010-01-07 19:39:21 +08:00
|
|
|
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
2009-10-01 16:20:52 +08:00
|
|
|
/* 1M ring buffer */
|
|
|
|
|
r = r100_cp_init(rdev, 1024 * 1024);
|
|
|
|
|
if (r) {
|
2011-01-29 06:32:04 +08:00
|
|
|
dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
|
2009-10-01 16:20:52 +08:00
|
|
|
return r;
|
|
|
|
|
}
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
|
|
|
|
2012-07-05 17:55:34 +08:00
|
|
|
r = radeon_ib_pool_init(rdev);
|
|
|
|
|
if (r) {
|
|
|
|
|
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
|
|
|
return r;
|
2012-07-05 17:55:34 +08:00
|
|
|
}
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int rs400_resume(struct radeon_device *rdev)
|
|
|
|
|
{
|
2012-02-21 06:57:20 +08:00
|
|
|
int r;
|
|
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
/* Make sur GART are not working */
|
|
|
|
|
rs400_gart_disable(rdev);
|
|
|
|
|
/* Resume clock before doing reset */
|
|
|
|
|
r300_clock_startup(rdev);
|
2009-10-27 08:57:53 +08:00
|
|
|
/* setup MC before calling post tables */
|
|
|
|
|
rs400_mc_program(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
2010-03-09 22:45:11 +08:00
|
|
|
if (radeon_asic_reset(rdev)) {
|
2009-10-01 16:20:52 +08:00
|
|
|
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
|
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
|
|
|
RREG32(R_0007C0_CP_STAT));
|
|
|
|
|
}
|
|
|
|
|
/* post */
|
|
|
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
|
|
|
/* Resume clock after posting */
|
|
|
|
|
r300_clock_startup(rdev);
|
2009-12-09 12:15:38 +08:00
|
|
|
/* Initialize surface registers */
|
|
|
|
|
radeon_surface_init(rdev);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
|
|
|
|
|
|
|
|
rdev->accel_working = true;
|
2012-02-21 06:57:20 +08:00
|
|
|
r = rs400_startup(rdev);
|
|
|
|
|
if (r) {
|
|
|
|
|
rdev->accel_working = false;
|
|
|
|
|
}
|
|
|
|
|
return r;
|
2009-10-01 16:20:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int rs400_suspend(struct radeon_device *rdev)
|
|
|
|
|
{
|
2013-12-19 03:07:14 +08:00
|
|
|
radeon_pm_suspend(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
r100_cp_disable(rdev);
|
2010-08-28 06:25:25 +08:00
|
|
|
radeon_wb_disable(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
r100_irq_disable(rdev);
|
|
|
|
|
rs400_gart_disable(rdev);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void rs400_fini(struct radeon_device *rdev)
|
|
|
|
|
{
|
2013-12-19 03:07:14 +08:00
|
|
|
radeon_pm_fini(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
r100_cp_fini(rdev);
|
2010-08-28 06:25:25 +08:00
|
|
|
radeon_wb_fini(rdev);
|
2012-07-05 17:55:34 +08:00
|
|
|
radeon_ib_pool_fini(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
radeon_gem_fini(rdev);
|
|
|
|
|
rs400_gart_fini(rdev);
|
|
|
|
|
radeon_irq_kms_fini(rdev);
|
|
|
|
|
radeon_fence_driver_fini(rdev);
|
2009-11-20 21:29:23 +08:00
|
|
|
radeon_bo_fini(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
radeon_atombios_fini(rdev);
|
|
|
|
|
kfree(rdev->bios);
|
|
|
|
|
rdev->bios = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int rs400_init(struct radeon_device *rdev)
|
|
|
|
|
{
|
|
|
|
|
int r;
|
|
|
|
|
|
|
|
|
|
/* Disable VGA */
|
|
|
|
|
r100_vga_render_disable(rdev);
|
|
|
|
|
/* Initialize scratch registers */
|
|
|
|
|
radeon_scratch_init(rdev);
|
|
|
|
|
/* Initialize surface registers */
|
|
|
|
|
radeon_surface_init(rdev);
|
|
|
|
|
/* TODO: disable VGA need to use VGA request */
|
2010-07-15 10:13:50 +08:00
|
|
|
/* restore some register to sane defaults */
|
|
|
|
|
r100_restore_sanity(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
/* BIOS*/
|
|
|
|
|
if (!radeon_get_bios(rdev)) {
|
|
|
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
if (rdev->is_atom_bios) {
|
|
|
|
|
dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
} else {
|
|
|
|
|
r = radeon_combios_init(rdev);
|
|
|
|
|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
2010-03-09 22:45:11 +08:00
|
|
|
if (radeon_asic_reset(rdev)) {
|
2009-10-01 16:20:52 +08:00
|
|
|
dev_warn(rdev->dev,
|
|
|
|
|
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
|
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
|
|
|
RREG32(R_0007C0_CP_STAT));
|
|
|
|
|
}
|
|
|
|
|
/* check if cards are posted or not */
|
2009-12-01 12:06:31 +08:00
|
|
|
if (radeon_boot_test_post_card(rdev) == false)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
/* Initialize clocks */
|
|
|
|
|
radeon_get_clock_info(rdev->ddev);
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18 05:54:29 +08:00
|
|
|
/* initialize memory controller */
|
|
|
|
|
rs400_mc_init(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
/* Fence driver */
|
2011-11-21 04:45:34 +08:00
|
|
|
r = radeon_fence_driver_init(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
/* Memory manager */
|
2009-11-20 21:29:23 +08:00
|
|
|
r = radeon_bo_init(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
r = rs400_gart_init(rdev);
|
|
|
|
|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
r300_set_reg_safe(rdev);
|
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
|
|
|
|
2013-12-19 03:07:14 +08:00
|
|
|
/* Initialize power management */
|
|
|
|
|
radeon_pm_init(rdev);
|
|
|
|
|
|
2009-10-01 16:20:52 +08:00
|
|
|
rdev->accel_working = true;
|
|
|
|
|
r = rs400_startup(rdev);
|
|
|
|
|
if (r) {
|
|
|
|
|
/* Somethings want wront with the accel init stop accel */
|
|
|
|
|
dev_err(rdev->dev, "Disabling GPU acceleration\n");
|
|
|
|
|
r100_cp_fini(rdev);
|
2010-08-28 06:25:25 +08:00
|
|
|
radeon_wb_fini(rdev);
|
2012-07-05 17:55:34 +08:00
|
|
|
radeon_ib_pool_fini(rdev);
|
2009-10-01 16:20:52 +08:00
|
|
|
rs400_gart_fini(rdev);
|
|
|
|
|
radeon_irq_kms_fini(rdev);
|
|
|
|
|
rdev->accel_working = false;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|