2015-01-22 08:35:44 +08:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* DOC: atomic modeset support
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*
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* The functions here implement the state management and hardware programming
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* dispatch required by the atomic modeset infrastructure.
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* See intel_atomic_plane.c for the plane-specific atomic functionality.
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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2019-01-26 20:25:24 +08:00
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#include <drm/drm_fourcc.h>
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2015-01-22 08:35:44 +08:00
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#include <drm/drm_plane_helper.h>
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2019-01-26 20:25:24 +08:00
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2019-04-29 20:53:31 +08:00
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#include "intel_atomic.h"
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2019-08-06 19:39:33 +08:00
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#include "intel_display_types.h"
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2019-04-05 19:00:13 +08:00
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#include "intel_hdcp.h"
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2019-04-05 19:00:24 +08:00
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#include "intel_sprite.h"
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2015-01-22 08:35:44 +08:00
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2017-05-01 21:37:57 +08:00
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/**
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* intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
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* @connector: Connector to get the property for.
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* @state: Connector state to retrieve the property from.
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* @property: Property to retrieve.
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* @val: Return value for the property.
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*
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* Returns the atomic property value for a digital connector.
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*/
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int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
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const struct drm_connector_state *state,
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struct drm_property *property,
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2019-01-16 17:15:19 +08:00
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u64 *val)
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2017-05-01 21:37:57 +08:00
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{
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struct drm_device *dev = connector->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_digital_connector_state *intel_conn_state =
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to_intel_digital_connector_state(state);
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if (property == dev_priv->force_audio_property)
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*val = intel_conn_state->force_audio;
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else if (property == dev_priv->broadcast_rgb_property)
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*val = intel_conn_state->broadcast_rgb;
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else {
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2018-06-12 03:34:03 +08:00
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DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
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property->base.id, property->name);
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2017-05-01 21:37:57 +08:00
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return -EINVAL;
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}
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return 0;
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}
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/**
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* intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property.
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* @connector: Connector to set the property for.
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* @state: Connector state to set the property on.
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* @property: Property to set.
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* @val: New value for the property.
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*
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* Sets the atomic property value for a digital connector.
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*/
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int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
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struct drm_connector_state *state,
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struct drm_property *property,
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2019-01-16 17:15:19 +08:00
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u64 val)
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2017-05-01 21:37:57 +08:00
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{
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struct drm_device *dev = connector->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_digital_connector_state *intel_conn_state =
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to_intel_digital_connector_state(state);
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if (property == dev_priv->force_audio_property) {
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intel_conn_state->force_audio = val;
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return 0;
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}
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if (property == dev_priv->broadcast_rgb_property) {
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intel_conn_state->broadcast_rgb = val;
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return 0;
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}
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2018-06-12 03:34:03 +08:00
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DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
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property->base.id, property->name);
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2017-05-01 21:37:57 +08:00
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return -EINVAL;
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}
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2019-05-16 22:10:14 +08:00
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static bool blob_equal(const struct drm_property_blob *a,
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const struct drm_property_blob *b)
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{
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if (a && b)
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return a->length == b->length &&
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!memcmp(a->data, b->data, a->length);
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return !a == !b;
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}
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2017-05-01 21:37:57 +08:00
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int intel_digital_connector_atomic_check(struct drm_connector *conn,
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2019-06-12 00:08:18 +08:00
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struct drm_atomic_state *state)
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2017-05-01 21:37:57 +08:00
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{
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2019-06-12 00:08:18 +08:00
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struct drm_connector_state *new_state =
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drm_atomic_get_new_connector_state(state, conn);
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2017-05-01 21:37:57 +08:00
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struct intel_digital_connector_state *new_conn_state =
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to_intel_digital_connector_state(new_state);
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struct drm_connector_state *old_state =
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2019-06-12 00:08:18 +08:00
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drm_atomic_get_old_connector_state(state, conn);
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2017-05-01 21:37:57 +08:00
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struct intel_digital_connector_state *old_conn_state =
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to_intel_digital_connector_state(old_state);
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struct drm_crtc_state *crtc_state;
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2018-01-09 03:55:39 +08:00
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intel_hdcp_atomic_check(conn, old_state, new_state);
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2017-05-01 21:37:57 +08:00
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if (!new_state->crtc)
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return 0;
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2019-06-12 00:08:18 +08:00
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crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
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2017-05-01 21:37:57 +08:00
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/*
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* These properties are handled by fastset, and might not end
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* up in a modeset.
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*/
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if (new_conn_state->force_audio != old_conn_state->force_audio ||
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new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
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2019-02-20 01:13:01 +08:00
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new_conn_state->base.colorspace != old_conn_state->base.colorspace ||
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2017-05-01 21:37:57 +08:00
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new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
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2018-05-15 21:59:28 +08:00
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new_conn_state->base.content_type != old_conn_state->base.content_type ||
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2019-05-16 22:10:14 +08:00
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new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
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!blob_equal(new_conn_state->base.hdr_output_metadata,
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old_conn_state->base.hdr_output_metadata))
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2017-05-01 21:37:57 +08:00
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crtc_state->mode_changed = true;
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return 0;
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}
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/**
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* intel_digital_connector_duplicate_state - duplicate connector state
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* @connector: digital connector
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*
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* Allocates and returns a copy of the connector state (both common and
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* digital connector specific) for the specified connector.
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*
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* Returns: The newly allocated connector state, or NULL on failure.
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*/
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struct drm_connector_state *
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intel_digital_connector_duplicate_state(struct drm_connector *connector)
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{
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struct intel_digital_connector_state *state;
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state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
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if (!state)
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return NULL;
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__drm_atomic_helper_connector_duplicate_state(connector, &state->base);
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return &state->base;
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}
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/**
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2015-01-22 08:35:47 +08:00
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* intel_crtc_duplicate_state - duplicate crtc state
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* @crtc: drm crtc
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*
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* Allocates and returns a copy of the crtc state (both common and
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* Intel-specific) for the specified crtc.
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*
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* Returns: The newly allocated crtc state, or NULL on failure.
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*/
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struct drm_crtc_state *
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intel_crtc_duplicate_state(struct drm_crtc *crtc)
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{
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2019-10-31 19:26:00 +08:00
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const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
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2015-03-03 21:21:55 +08:00
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struct intel_crtc_state *crtc_state;
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2015-01-22 08:35:47 +08:00
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2019-10-31 19:26:00 +08:00
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crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
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2015-04-21 22:12:58 +08:00
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if (!crtc_state)
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return NULL;
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2019-10-31 19:26:03 +08:00
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__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
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2015-04-21 22:12:58 +08:00
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2015-08-27 21:44:05 +08:00
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crtc_state->update_pipe = false;
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2015-09-25 06:53:12 +08:00
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crtc_state->disable_lp_wm = false;
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2015-11-19 23:07:14 +08:00
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crtc_state->disable_cxsr = false;
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2016-03-10 01:07:25 +08:00
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crtc_state->update_wm_pre = false;
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crtc_state->update_wm_post = false;
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2017-03-03 01:14:58 +08:00
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crtc_state->fifo_changed = false;
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drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 09:20:13 +08:00
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crtc_state->wm.need_postvbl_update = false;
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2016-03-09 17:35:44 +08:00
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crtc_state->fb_bits = 0;
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2018-11-28 00:37:42 +08:00
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crtc_state->update_planes = 0;
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2015-08-27 21:44:05 +08:00
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2019-10-31 19:26:03 +08:00
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return &crtc_state->uapi;
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2015-01-22 08:35:47 +08:00
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}
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/**
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* intel_crtc_destroy_state - destroy crtc state
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* @crtc: drm crtc
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2018-02-14 21:49:21 +08:00
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* @state: the state to destroy
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2015-01-22 08:35:47 +08:00
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*
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* Destroys the crtc state (both common and Intel-specific) for the
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* specified crtc.
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*/
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void
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intel_crtc_destroy_state(struct drm_crtc *crtc,
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2018-02-14 21:49:21 +08:00
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struct drm_crtc_state *state)
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2015-01-22 08:35:47 +08:00
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{
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2019-10-31 19:26:00 +08:00
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struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
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2019-10-31 19:26:03 +08:00
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__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
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2019-10-31 19:26:00 +08:00
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kfree(crtc_state);
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2015-01-22 08:35:47 +08:00
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}
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2015-04-10 07:42:46 +08:00
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2018-09-21 22:44:37 +08:00
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static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
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int num_scalers_need, struct intel_crtc *intel_crtc,
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const char *name, int idx,
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struct intel_plane_state *plane_state,
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int *scaler_id)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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int j;
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u32 mode;
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if (*scaler_id < 0) {
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/* find a free scaler */
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for (j = 0; j < intel_crtc->num_scalers; j++) {
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if (scaler_state->scalers[j].in_use)
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continue;
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*scaler_id = j;
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scaler_state->scalers[*scaler_id].in_use = 1;
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break;
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}
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}
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if (WARN(*scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx))
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return;
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/* set scaler mode */
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if (plane_state && plane_state->base.fb &&
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plane_state->base.fb->format->is_yuv &&
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plane_state->base.fb->format->num_planes > 1) {
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2019-03-13 08:38:31 +08:00
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struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
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drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
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- IS_GEN3(e)
+ IS_GEN(e, 3)
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- IS_GEN4(e)
+ IS_GEN(e, 4)
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- IS_GEN5(e)
+ IS_GEN(e, 5)
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- IS_GEN6(e)
+ IS_GEN(e, 6)
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- IS_GEN7(e)
+ IS_GEN(e, 7)
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- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
|
|
|
if (IS_GEN(dev_priv, 9) &&
|
2018-10-18 19:51:31 +08:00
|
|
|
!IS_GEMINILAKE(dev_priv)) {
|
2018-09-21 22:44:37 +08:00
|
|
|
mode = SKL_PS_SCALER_MODE_NV12;
|
2019-03-13 08:38:31 +08:00
|
|
|
} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
|
2018-10-18 19:51:31 +08:00
|
|
|
/*
|
|
|
|
* On gen11+'s HDR planes we only use the scaler for
|
|
|
|
* scaling. They have a dedicated chroma upsampler, so
|
|
|
|
* we don't need the scaler to upsample the UV plane.
|
|
|
|
*/
|
|
|
|
mode = PS_SCALER_MODE_NORMAL;
|
|
|
|
} else {
|
2019-09-20 19:42:20 +08:00
|
|
|
struct intel_plane *linked =
|
|
|
|
plane_state->planar_linked_plane;
|
|
|
|
|
2018-09-21 22:44:37 +08:00
|
|
|
mode = PS_SCALER_MODE_PLANAR;
|
|
|
|
|
2019-09-20 19:42:20 +08:00
|
|
|
if (linked)
|
|
|
|
mode |= PS_PLANE_Y_SEL(linked->id);
|
2018-10-18 19:51:31 +08:00
|
|
|
}
|
2018-09-21 22:44:37 +08:00
|
|
|
} else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
|
2018-10-18 19:51:31 +08:00
|
|
|
mode = PS_SCALER_MODE_NORMAL;
|
2018-09-21 22:44:37 +08:00
|
|
|
} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
|
|
|
|
/*
|
|
|
|
* when only 1 scaler is in use on a pipe with 2 scalers
|
|
|
|
* scaler 0 operates in high quality (HQ) mode.
|
|
|
|
* In this case use scaler 0 to take advantage of HQ mode
|
|
|
|
*/
|
|
|
|
scaler_state->scalers[*scaler_id].in_use = 0;
|
|
|
|
*scaler_id = 0;
|
|
|
|
scaler_state->scalers[0].in_use = 1;
|
|
|
|
mode = SKL_PS_SCALER_MODE_HQ;
|
|
|
|
} else {
|
|
|
|
mode = SKL_PS_SCALER_MODE_DYN;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
|
|
|
|
intel_crtc->pipe, *scaler_id, name, idx);
|
|
|
|
scaler_state->scalers[*scaler_id].mode = mode;
|
|
|
|
}
|
|
|
|
|
2015-04-10 07:42:46 +08:00
|
|
|
/**
|
|
|
|
* intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
|
2017-02-23 15:15:59 +08:00
|
|
|
* @dev_priv: i915 device
|
2018-02-14 21:49:21 +08:00
|
|
|
* @intel_crtc: intel crtc
|
2015-04-10 07:42:46 +08:00
|
|
|
* @crtc_state: incoming crtc_state to validate and setup scalers
|
|
|
|
*
|
|
|
|
* This function sets up scalers based on staged scaling requests for
|
|
|
|
* a @crtc and its planes. It is called from crtc level check path. If request
|
|
|
|
* is a supportable request, it attaches scalers to requested planes and crtc.
|
|
|
|
*
|
|
|
|
* This function takes into account the current scaler(s) in use by any planes
|
|
|
|
* not being part of this atomic state
|
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* 0 - scalers were setup succesfully
|
|
|
|
* error code - otherwise
|
|
|
|
*/
|
2017-02-23 15:15:59 +08:00
|
|
|
int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
2015-04-10 07:42:46 +08:00
|
|
|
{
|
|
|
|
struct drm_plane *plane = NULL;
|
|
|
|
struct intel_plane *intel_plane;
|
|
|
|
struct intel_plane_state *plane_state = NULL;
|
2015-07-13 22:30:15 +08:00
|
|
|
struct intel_crtc_scaler_state *scaler_state =
|
|
|
|
&crtc_state->scaler_state;
|
2019-10-31 19:26:03 +08:00
|
|
|
struct drm_atomic_state *drm_state = crtc_state->uapi.state;
|
2018-04-09 20:46:53 +08:00
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
|
2015-04-10 07:42:46 +08:00
|
|
|
int num_scalers_need;
|
2018-09-21 22:44:37 +08:00
|
|
|
int i;
|
2015-04-10 07:42:46 +08:00
|
|
|
|
|
|
|
num_scalers_need = hweight32(scaler_state->scaler_users);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* High level flow:
|
|
|
|
* - staged scaler requests are already in scaler_state->scaler_users
|
|
|
|
* - check whether staged scaling requests can be supported
|
|
|
|
* - add planes using scalers that aren't in current transaction
|
|
|
|
* - assign scalers to requested users
|
|
|
|
* - as part of plane commit, scalers will be committed
|
|
|
|
* (i.e., either attached or detached) to respective planes in hw
|
|
|
|
* - as part of crtc_commit, scaler will be either attached or detached
|
|
|
|
* to crtc in hw
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* fail if required scalers > available scalers */
|
|
|
|
if (num_scalers_need > intel_crtc->num_scalers){
|
|
|
|
DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
|
|
|
|
num_scalers_need, intel_crtc->num_scalers);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* walkthrough scaler_users bits and start assigning scalers */
|
|
|
|
for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
|
|
|
|
int *scaler_id;
|
2015-06-15 18:33:39 +08:00
|
|
|
const char *name;
|
|
|
|
int idx;
|
2015-04-10 07:42:46 +08:00
|
|
|
|
|
|
|
/* skip if scaler not required */
|
|
|
|
if (!(scaler_state->scaler_users & (1 << i)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (i == SKL_CRTC_INDEX) {
|
2015-06-15 18:33:39 +08:00
|
|
|
name = "CRTC";
|
|
|
|
idx = intel_crtc->base.base.id;
|
|
|
|
|
2015-04-10 07:42:46 +08:00
|
|
|
/* panel fitter case: assign as a crtc scaler */
|
|
|
|
scaler_id = &scaler_state->scaler_id;
|
|
|
|
} else {
|
2015-06-15 18:33:39 +08:00
|
|
|
name = "PLANE";
|
|
|
|
|
2015-04-10 07:42:46 +08:00
|
|
|
/* plane scaler case: assign as a plane scaler */
|
|
|
|
/* find the plane that set the bit as scaler_user */
|
2016-06-02 06:06:33 +08:00
|
|
|
plane = drm_state->planes[i].ptr;
|
2015-04-10 07:42:46 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* to enable/disable hq mode, add planes that are using scaler
|
|
|
|
* into this transaction
|
|
|
|
*/
|
|
|
|
if (!plane) {
|
|
|
|
struct drm_plane_state *state;
|
2019-09-20 19:42:21 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* GLK+ scalers don't have a HQ mode so it
|
|
|
|
* isn't necessary to change between HQ and dyn mode
|
|
|
|
* on those platforms.
|
|
|
|
*/
|
|
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
|
|
|
|
continue;
|
|
|
|
|
2017-02-23 15:15:59 +08:00
|
|
|
plane = drm_plane_from_index(&dev_priv->drm, i);
|
2015-04-10 07:42:46 +08:00
|
|
|
state = drm_atomic_get_plane_state(drm_state, plane);
|
|
|
|
if (IS_ERR(state)) {
|
|
|
|
DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
|
|
|
|
plane->base.id);
|
|
|
|
return PTR_ERR(state);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_plane = to_intel_plane(plane);
|
2015-07-07 00:19:24 +08:00
|
|
|
idx = plane->base.id;
|
2015-04-10 07:42:46 +08:00
|
|
|
|
|
|
|
/* plane on different crtc cannot be a scaler user of this crtc */
|
2018-09-21 22:44:37 +08:00
|
|
|
if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
|
2015-04-10 07:42:46 +08:00
|
|
|
continue;
|
|
|
|
|
2018-04-09 20:46:53 +08:00
|
|
|
plane_state = intel_atomic_get_new_plane_state(intel_state,
|
|
|
|
intel_plane);
|
2015-04-10 07:42:46 +08:00
|
|
|
scaler_id = &plane_state->scaler_id;
|
|
|
|
}
|
|
|
|
|
2018-09-21 22:44:37 +08:00
|
|
|
intel_atomic_setup_scaler(scaler_state, num_scalers_need,
|
|
|
|
intel_crtc, name, idx,
|
|
|
|
plane_state, scaler_id);
|
2015-04-10 07:42:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2015-06-04 16:21:28 +08:00
|
|
|
|
|
|
|
struct drm_atomic_state *
|
|
|
|
intel_atomic_state_alloc(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
|
|
|
|
kfree(state);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return &state->base;
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_atomic_state_clear(struct drm_atomic_state *s)
|
|
|
|
{
|
|
|
|
struct intel_atomic_state *state = to_intel_atomic_state(s);
|
|
|
|
drm_atomic_state_default_clear(&state->base);
|
2015-12-10 19:33:57 +08:00
|
|
|
state->dpll_set = state->modeset = false;
|
2019-10-16 03:30:24 +08:00
|
|
|
state->global_state_changed = false;
|
|
|
|
state->active_pipes = 0;
|
|
|
|
memset(&state->min_cdclk, 0, sizeof(state->min_cdclk));
|
|
|
|
memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level));
|
|
|
|
memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical));
|
|
|
|
memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual));
|
|
|
|
state->cdclk.pipe = INVALID_PIPE;
|
2015-06-04 16:21:28 +08:00
|
|
|
}
|
2019-04-29 20:53:31 +08:00
|
|
|
|
|
|
|
struct intel_crtc_state *
|
|
|
|
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
|
|
|
|
struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_crtc_state *crtc_state;
|
|
|
|
crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
|
|
|
|
if (IS_ERR(crtc_state))
|
|
|
|
return ERR_CAST(crtc_state);
|
|
|
|
|
|
|
|
return to_intel_crtc_state(crtc_state);
|
|
|
|
}
|
2019-10-16 03:30:24 +08:00
|
|
|
|
|
|
|
int intel_atomic_lock_global_state(struct intel_atomic_state *state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
|
|
|
struct intel_crtc *crtc;
|
|
|
|
|
|
|
|
state->global_state_changed = true;
|
|
|
|
|
|
|
|
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = drm_modeset_lock(&crtc->base.mutex,
|
|
|
|
state->base.acquire_ctx);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
|
|
|
struct intel_crtc *crtc;
|
|
|
|
|
|
|
|
state->global_state_changed = true;
|
|
|
|
|
|
|
|
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
|
|
|
struct intel_crtc_state *crtc_state;
|
|
|
|
|
|
|
|
crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
|
|
|
|
if (IS_ERR(crtc_state))
|
|
|
|
return PTR_ERR(crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|