2012-11-06 14:09:04 +08:00
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/*
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* Samsung's Exynos4212 SoC device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2013-06-17 23:02:08 +08:00
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#include "exynos4x12.dtsi"
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2012-11-06 14:09:04 +08:00
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/ {
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2014-03-21 01:17:22 +08:00
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compatible = "samsung,exynos4212", "samsung,exynos4";
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2012-11-06 14:09:04 +08:00
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2014-09-25 16:40:14 +08:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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2015-01-30 07:26:02 +08:00
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cpu0: cpu@A00 {
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2014-09-25 16:40:14 +08:00
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA00>;
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2015-01-30 07:26:02 +08:00
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cooling-min-level = <13>;
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cooling-max-level = <7>;
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#cooling-cells = <2>; /* min followed by max */
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2014-09-25 16:40:14 +08:00
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};
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cpu@A01 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA01>;
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};
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};
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2014-03-18 05:25:59 +08:00
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combiner: interrupt-controller@10440000 {
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samsung,combiner-nr = <18>;
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2012-11-06 14:09:04 +08:00
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};
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2013-03-09 15:12:35 +08:00
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2014-03-18 05:25:59 +08:00
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gic: interrupt-controller@10490000 {
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cpu-offset = <0x8000>;
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2013-04-12 21:15:58 +08:00
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};
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2012-11-06 14:09:04 +08:00
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};
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