2010-08-24 11:24:12 +08:00
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/*
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* Linux network driver for Brocade Converged Network Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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/*
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* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*/
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#include "cna.h"
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#include <linux/netdevice.h>
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#include <linux/skbuff.h>
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#include <linux/ethtool.h>
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#include <linux/rtnetlink.h>
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#include "bna.h"
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#include "bnad.h"
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#define BNAD_NUM_TXF_COUNTERS 12
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#define BNAD_NUM_RXF_COUNTERS 10
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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#define BNAD_NUM_CQ_COUNTERS (3 + 5)
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2010-08-24 11:24:12 +08:00
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#define BNAD_NUM_RXQ_COUNTERS 6
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#define BNAD_NUM_TXQ_COUNTERS 5
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#define BNAD_ETHTOOL_STATS_NUM \
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2010-09-03 03:45:02 +08:00
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(sizeof(struct rtnl_link_stats64) / sizeof(u64) + \
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2010-08-24 11:24:12 +08:00
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sizeof(struct bnad_drv_stats) / sizeof(u64) + \
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
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offsetof(struct bfi_enet_stats, rxf_stats[0]) / sizeof(u64))
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2010-08-24 11:24:12 +08:00
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2012-01-04 21:02:23 +08:00
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static const char *bnad_net_stats_strings[BNAD_ETHTOOL_STATS_NUM] = {
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2010-08-24 11:24:12 +08:00
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"rx_packets",
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"tx_packets",
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"rx_bytes",
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"tx_bytes",
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"rx_errors",
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"tx_errors",
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"rx_dropped",
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"tx_dropped",
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"multicast",
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"collisions",
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"rx_length_errors",
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"rx_over_errors",
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"rx_crc_errors",
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"rx_frame_errors",
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"rx_fifo_errors",
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"rx_missed_errors",
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"tx_aborted_errors",
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"tx_carrier_errors",
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"tx_fifo_errors",
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"tx_heartbeat_errors",
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"tx_window_errors",
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"rx_compressed",
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"tx_compressed",
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"netif_queue_stop",
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"netif_queue_wakeup",
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2010-12-24 05:45:05 +08:00
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"netif_queue_stopped",
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2010-08-24 11:24:12 +08:00
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"tso4",
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"tso6",
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"tso_err",
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"tcpcsum_offload",
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"udpcsum_offload",
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"csum_help",
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2011-08-30 23:27:43 +08:00
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"tx_skb_too_short",
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"tx_skb_stopping",
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"tx_skb_max_vectors",
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"tx_skb_mss_too_long",
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"tx_skb_tso_too_short",
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"tx_skb_tso_prepare",
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"tx_skb_non_tso_too_long",
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"tx_skb_tcp_hdr",
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"tx_skb_udp_hdr",
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"tx_skb_csum_err",
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"tx_skb_headlen_too_long",
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"tx_skb_headlen_zero",
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"tx_skb_frag_zero",
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"tx_skb_len_mismatch",
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2010-08-24 11:24:12 +08:00
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"hw_stats_updates",
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"netif_rx_dropped",
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"link_toggle",
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2011-08-30 23:27:43 +08:00
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"cee_toggle",
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2010-08-24 11:24:12 +08:00
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"rxp_info_alloc_failed",
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"mbox_intr_disabled",
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"mbox_intr_enabled",
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"tx_unmap_q_alloc_failed",
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"rx_unmap_q_alloc_failed",
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"rxbuf_alloc_failed",
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2012-12-11 20:24:55 +08:00
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"mac_stats_clr_cnt",
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2010-08-24 11:24:12 +08:00
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"mac_frame_64",
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"mac_frame_65_127",
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"mac_frame_128_255",
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"mac_frame_256_511",
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"mac_frame_512_1023",
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"mac_frame_1024_1518",
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"mac_frame_1518_1522",
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"mac_rx_bytes",
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"mac_rx_packets",
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"mac_rx_fcs_error",
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"mac_rx_multicast",
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"mac_rx_broadcast",
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"mac_rx_control_frames",
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"mac_rx_pause",
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"mac_rx_unknown_opcode",
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"mac_rx_alignment_error",
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"mac_rx_frame_length_error",
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"mac_rx_code_error",
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"mac_rx_carrier_sense_error",
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"mac_rx_undersize",
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"mac_rx_oversize",
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"mac_rx_fragments",
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"mac_rx_jabber",
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"mac_rx_drop",
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"mac_tx_bytes",
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"mac_tx_packets",
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"mac_tx_multicast",
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"mac_tx_broadcast",
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"mac_tx_pause",
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"mac_tx_deferral",
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"mac_tx_excessive_deferral",
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"mac_tx_single_collision",
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"mac_tx_muliple_collision",
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"mac_tx_late_collision",
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"mac_tx_excessive_collision",
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"mac_tx_total_collision",
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"mac_tx_pause_honored",
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"mac_tx_drop",
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"mac_tx_jabber",
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"mac_tx_fcs_error",
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"mac_tx_control_frame",
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"mac_tx_oversize",
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"mac_tx_undersize",
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"mac_tx_fragments",
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"bpc_tx_pause_0",
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"bpc_tx_pause_1",
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"bpc_tx_pause_2",
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"bpc_tx_pause_3",
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"bpc_tx_pause_4",
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"bpc_tx_pause_5",
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"bpc_tx_pause_6",
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"bpc_tx_pause_7",
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"bpc_tx_zero_pause_0",
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"bpc_tx_zero_pause_1",
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"bpc_tx_zero_pause_2",
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"bpc_tx_zero_pause_3",
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"bpc_tx_zero_pause_4",
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"bpc_tx_zero_pause_5",
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"bpc_tx_zero_pause_6",
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"bpc_tx_zero_pause_7",
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"bpc_tx_first_pause_0",
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"bpc_tx_first_pause_1",
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"bpc_tx_first_pause_2",
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"bpc_tx_first_pause_3",
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"bpc_tx_first_pause_4",
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"bpc_tx_first_pause_5",
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"bpc_tx_first_pause_6",
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"bpc_tx_first_pause_7",
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"bpc_rx_pause_0",
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"bpc_rx_pause_1",
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"bpc_rx_pause_2",
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"bpc_rx_pause_3",
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"bpc_rx_pause_4",
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"bpc_rx_pause_5",
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"bpc_rx_pause_6",
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"bpc_rx_pause_7",
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"bpc_rx_zero_pause_0",
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"bpc_rx_zero_pause_1",
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"bpc_rx_zero_pause_2",
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"bpc_rx_zero_pause_3",
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"bpc_rx_zero_pause_4",
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"bpc_rx_zero_pause_5",
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"bpc_rx_zero_pause_6",
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"bpc_rx_zero_pause_7",
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"bpc_rx_first_pause_0",
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"bpc_rx_first_pause_1",
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"bpc_rx_first_pause_2",
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"bpc_rx_first_pause_3",
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"bpc_rx_first_pause_4",
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"bpc_rx_first_pause_5",
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"bpc_rx_first_pause_6",
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"bpc_rx_first_pause_7",
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"rad_rx_frames",
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"rad_rx_octets",
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"rad_rx_vlan_frames",
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"rad_rx_ucast",
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"rad_rx_ucast_octets",
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"rad_rx_ucast_vlan",
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"rad_rx_mcast",
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"rad_rx_mcast_octets",
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"rad_rx_mcast_vlan",
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"rad_rx_bcast",
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"rad_rx_bcast_octets",
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"rad_rx_bcast_vlan",
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"rad_rx_drops",
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2011-08-30 23:27:43 +08:00
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"rlb_rad_rx_frames",
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"rlb_rad_rx_octets",
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"rlb_rad_rx_vlan_frames",
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"rlb_rad_rx_ucast",
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"rlb_rad_rx_ucast_octets",
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"rlb_rad_rx_ucast_vlan",
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"rlb_rad_rx_mcast",
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"rlb_rad_rx_mcast_octets",
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"rlb_rad_rx_mcast_vlan",
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"rlb_rad_rx_bcast",
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"rlb_rad_rx_bcast_octets",
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"rlb_rad_rx_bcast_vlan",
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"rlb_rad_rx_drops",
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2010-08-24 11:24:12 +08:00
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"fc_rx_ucast_octets",
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"fc_rx_ucast",
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"fc_rx_ucast_vlan",
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"fc_rx_mcast_octets",
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"fc_rx_mcast",
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"fc_rx_mcast_vlan",
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"fc_rx_bcast_octets",
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"fc_rx_bcast",
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"fc_rx_bcast_vlan",
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"fc_tx_ucast_octets",
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"fc_tx_ucast",
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"fc_tx_ucast_vlan",
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"fc_tx_mcast_octets",
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"fc_tx_mcast",
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"fc_tx_mcast_vlan",
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"fc_tx_bcast_octets",
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"fc_tx_bcast",
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"fc_tx_bcast_vlan",
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"fc_tx_parity_errors",
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"fc_tx_timeout",
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"fc_tx_fid_parity_errors",
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};
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static int
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bnad_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
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{
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cmd->supported = SUPPORTED_10000baseT_Full;
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cmd->advertising = ADVERTISED_10000baseT_Full;
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cmd->autoneg = AUTONEG_DISABLE;
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cmd->supported |= SUPPORTED_FIBRE;
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cmd->advertising |= ADVERTISED_FIBRE;
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cmd->port = PORT_FIBRE;
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cmd->phy_address = 0;
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if (netif_carrier_ok(netdev)) {
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2011-04-28 02:32:40 +08:00
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ethtool_cmd_speed_set(cmd, SPEED_10000);
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2010-08-24 11:24:12 +08:00
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cmd->duplex = DUPLEX_FULL;
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} else {
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2014-06-06 20:17:00 +08:00
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ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
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cmd->duplex = DUPLEX_UNKNOWN;
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2010-08-24 11:24:12 +08:00
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}
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cmd->transceiver = XCVR_EXTERNAL;
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cmd->maxtxpkt = 0;
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cmd->maxrxpkt = 0;
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return 0;
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}
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static int
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bnad_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
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|
|
|
{
|
|
|
|
/* 10G full duplex setting supported only */
|
|
|
|
if (cmd->autoneg == AUTONEG_ENABLE)
|
|
|
|
return -EOPNOTSUPP; else {
|
2011-04-28 02:32:39 +08:00
|
|
|
if ((ethtool_cmd_speed(cmd) == SPEED_10000)
|
|
|
|
&& (cmd->duplex == DUPLEX_FULL))
|
2010-08-24 11:24:12 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bnad_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
struct bfa_ioc_attr *ioc_attr;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2011-11-07 21:29:27 +08:00
|
|
|
strlcpy(drvinfo->driver, BNAD_NAME, sizeof(drvinfo->driver));
|
|
|
|
strlcpy(drvinfo->version, BNAD_VERSION, sizeof(drvinfo->version));
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
ioc_attr = kzalloc(sizeof(*ioc_attr), GFP_KERNEL);
|
|
|
|
if (ioc_attr) {
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bfa_nw_ioc_get_attr(&bnad->bna.ioceth.ioc, ioc_attr);
|
2010-08-24 11:24:12 +08:00
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
|
2011-11-07 21:29:27 +08:00
|
|
|
strlcpy(drvinfo->fw_version, ioc_attr->adapter_attr.fw_ver,
|
|
|
|
sizeof(drvinfo->fw_version));
|
2010-08-24 11:24:12 +08:00
|
|
|
kfree(ioc_attr);
|
|
|
|
}
|
|
|
|
|
2011-11-07 21:29:27 +08:00
|
|
|
strlcpy(drvinfo->bus_info, pci_name(bnad->pcidev),
|
|
|
|
sizeof(drvinfo->bus_info));
|
2010-08-24 11:24:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bnad_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wolinfo)
|
|
|
|
{
|
|
|
|
wolinfo->supported = 0;
|
|
|
|
wolinfo->wolopts = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
/* Lock rqd. to access bnad->bna_lock */
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
|
|
|
coalesce->use_adaptive_rx_coalesce =
|
|
|
|
(bnad->cfg_flags & BNAD_CF_DIM_ENABLED) ? true : false;
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
|
|
|
|
coalesce->rx_coalesce_usecs = bnad->rx_coalescing_timeo *
|
|
|
|
BFI_COALESCING_TIMER_UNIT;
|
|
|
|
coalesce->tx_coalesce_usecs = bnad->tx_coalescing_timeo *
|
|
|
|
BFI_COALESCING_TIMER_UNIT;
|
|
|
|
coalesce->tx_max_coalesced_frames = BFI_TX_INTERPKT_COUNT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
unsigned long flags;
|
2011-08-30 23:27:43 +08:00
|
|
|
int to_del = 0;
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
if (coalesce->rx_coalesce_usecs == 0 ||
|
|
|
|
coalesce->rx_coalesce_usecs >
|
|
|
|
BFI_MAX_COALESCING_TIMEO * BFI_COALESCING_TIMER_UNIT)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (coalesce->tx_coalesce_usecs == 0 ||
|
|
|
|
coalesce->tx_coalesce_usecs >
|
|
|
|
BFI_MAX_COALESCING_TIMEO * BFI_COALESCING_TIMER_UNIT)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&bnad->conf_mutex);
|
|
|
|
/*
|
|
|
|
* Do not need to store rx_coalesce_usecs here
|
|
|
|
* Every time DIM is disabled, we can get it from the
|
|
|
|
* stack.
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
|
|
|
if (coalesce->use_adaptive_rx_coalesce) {
|
|
|
|
if (!(bnad->cfg_flags & BNAD_CF_DIM_ENABLED)) {
|
|
|
|
bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
|
|
|
|
bnad_dim_timer_start(bnad);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) {
|
|
|
|
bnad->cfg_flags &= ~BNAD_CF_DIM_ENABLED;
|
2011-08-30 23:27:43 +08:00
|
|
|
if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
|
|
|
|
test_bit(BNAD_RF_DIM_TIMER_RUNNING,
|
|
|
|
&bnad->run_flags)) {
|
2010-08-24 11:24:12 +08:00
|
|
|
clear_bit(BNAD_RF_DIM_TIMER_RUNNING,
|
|
|
|
&bnad->run_flags);
|
2011-08-30 23:27:43 +08:00
|
|
|
to_del = 1;
|
2010-08-24 11:24:12 +08:00
|
|
|
}
|
2011-08-30 23:27:43 +08:00
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
if (to_del)
|
|
|
|
del_timer_sync(&bnad->dim_timer);
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
2010-08-24 11:24:12 +08:00
|
|
|
bnad_rx_coalescing_timeo_set(bnad);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (bnad->tx_coalescing_timeo != coalesce->tx_coalesce_usecs /
|
|
|
|
BFI_COALESCING_TIMER_UNIT) {
|
|
|
|
bnad->tx_coalescing_timeo = coalesce->tx_coalesce_usecs /
|
|
|
|
BFI_COALESCING_TIMER_UNIT;
|
|
|
|
bnad_tx_coalescing_timeo_set(bnad);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (bnad->rx_coalescing_timeo != coalesce->rx_coalesce_usecs /
|
|
|
|
BFI_COALESCING_TIMER_UNIT) {
|
|
|
|
bnad->rx_coalescing_timeo = coalesce->rx_coalesce_usecs /
|
|
|
|
BFI_COALESCING_TIMER_UNIT;
|
|
|
|
|
|
|
|
if (!(bnad->cfg_flags & BNAD_CF_DIM_ENABLED))
|
|
|
|
bnad_rx_coalescing_timeo_set(bnad);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Add Tx Inter-pkt DMA count? */
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bnad_get_ringparam(struct net_device *netdev,
|
|
|
|
struct ethtool_ringparam *ringparam)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
|
2011-08-30 23:27:46 +08:00
|
|
|
ringparam->rx_max_pending = BNAD_MAX_RXQ_DEPTH;
|
|
|
|
ringparam->tx_max_pending = BNAD_MAX_TXQ_DEPTH;
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
ringparam->rx_pending = bnad->rxq_depth;
|
|
|
|
ringparam->tx_pending = bnad->txq_depth;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_set_ringparam(struct net_device *netdev,
|
|
|
|
struct ethtool_ringparam *ringparam)
|
|
|
|
{
|
|
|
|
int i, current_err, err = 0;
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
2011-08-30 23:27:43 +08:00
|
|
|
unsigned long flags;
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
mutex_lock(&bnad->conf_mutex);
|
|
|
|
if (ringparam->rx_pending == bnad->rxq_depth &&
|
|
|
|
ringparam->tx_pending == bnad->txq_depth) {
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ringparam->rx_pending < BNAD_MIN_Q_DEPTH ||
|
2011-08-30 23:27:46 +08:00
|
|
|
ringparam->rx_pending > BNAD_MAX_RXQ_DEPTH ||
|
2010-08-24 11:24:12 +08:00
|
|
|
!BNA_POWER_OF_2(ringparam->rx_pending)) {
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
if (ringparam->tx_pending < BNAD_MIN_Q_DEPTH ||
|
2011-08-30 23:27:46 +08:00
|
|
|
ringparam->tx_pending > BNAD_MAX_TXQ_DEPTH ||
|
2010-08-24 11:24:12 +08:00
|
|
|
!BNA_POWER_OF_2(ringparam->tx_pending)) {
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ringparam->rx_pending != bnad->rxq_depth) {
|
|
|
|
bnad->rxq_depth = ringparam->rx_pending;
|
2011-08-30 23:27:43 +08:00
|
|
|
if (!netif_running(netdev)) {
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-24 11:24:12 +08:00
|
|
|
for (i = 0; i < bnad->num_rx; i++) {
|
|
|
|
if (!bnad->rx_info[i].rx)
|
|
|
|
continue;
|
2012-04-04 13:44:14 +08:00
|
|
|
bnad_destroy_rx(bnad, i);
|
2010-08-24 11:24:12 +08:00
|
|
|
current_err = bnad_setup_rx(bnad, i);
|
|
|
|
if (current_err && !err)
|
|
|
|
err = current_err;
|
2011-08-30 23:27:43 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!err && bnad->rx_info[0].rx) {
|
|
|
|
/* restore rx configuration */
|
2011-09-16 23:06:47 +08:00
|
|
|
bnad_restore_vlans(bnad, 0);
|
2011-08-30 23:27:43 +08:00
|
|
|
bnad_enable_default_bcast(bnad);
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
|
|
|
bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
2011-09-16 23:06:47 +08:00
|
|
|
bnad->cfg_flags &= ~(BNAD_CF_ALLMULTI |
|
|
|
|
BNAD_CF_PROMISC);
|
2011-08-30 23:27:43 +08:00
|
|
|
bnad_set_rx_mode(netdev);
|
2010-08-24 11:24:12 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (ringparam->tx_pending != bnad->txq_depth) {
|
|
|
|
bnad->txq_depth = ringparam->tx_pending;
|
2011-08-30 23:27:43 +08:00
|
|
|
if (!netif_running(netdev)) {
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-24 11:24:12 +08:00
|
|
|
for (i = 0; i < bnad->num_tx; i++) {
|
|
|
|
if (!bnad->tx_info[i].tx)
|
|
|
|
continue;
|
2012-04-04 13:44:14 +08:00
|
|
|
bnad_destroy_tx(bnad, i);
|
2010-08-24 11:24:12 +08:00
|
|
|
current_err = bnad_setup_tx(bnad, i);
|
|
|
|
if (current_err && !err)
|
|
|
|
err = current_err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bnad_get_pauseparam(struct net_device *netdev,
|
|
|
|
struct ethtool_pauseparam *pauseparam)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
|
|
|
|
pauseparam->autoneg = 0;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
pauseparam->rx_pause = bnad->bna.enet.pause_config.rx_pause;
|
|
|
|
pauseparam->tx_pause = bnad->bna.enet.pause_config.tx_pause;
|
2010-08-24 11:24:12 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_set_pauseparam(struct net_device *netdev,
|
|
|
|
struct ethtool_pauseparam *pauseparam)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
struct bna_pause_config pause_config;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (pauseparam->autoneg == AUTONEG_ENABLE)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&bnad->conf_mutex);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
if (pauseparam->rx_pause != bnad->bna.enet.pause_config.rx_pause ||
|
|
|
|
pauseparam->tx_pause != bnad->bna.enet.pause_config.tx_pause) {
|
2010-08-24 11:24:12 +08:00
|
|
|
pause_config.rx_pause = pauseparam->rx_pause;
|
|
|
|
pause_config.tx_pause = pauseparam->tx_pause;
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
|
2010-08-24 11:24:12 +08:00
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
}
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2012-04-04 13:44:14 +08:00
|
|
|
bnad_get_strings(struct net_device *netdev, u32 stringset, u8 *string)
|
2010-08-24 11:24:12 +08:00
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
int i, j, q_num;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
u32 bmap;
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
mutex_lock(&bnad->conf_mutex);
|
|
|
|
|
|
|
|
switch (stringset) {
|
|
|
|
case ETH_SS_STATS:
|
|
|
|
for (i = 0; i < BNAD_ETHTOOL_STATS_NUM; i++) {
|
|
|
|
BUG_ON(!(strlen(bnad_net_stats_strings[i]) <
|
|
|
|
ETH_GSTRING_LEN));
|
|
|
|
memcpy(string, bnad_net_stats_strings[i],
|
|
|
|
ETH_GSTRING_LEN);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
}
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bmap = bna_tx_rid_mask(&bnad->bna);
|
|
|
|
for (i = 0; bmap; i++) {
|
2010-08-24 11:24:12 +08:00
|
|
|
if (bmap & 1) {
|
|
|
|
sprintf(string, "txf%d_ucast_octets", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_ucast", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_ucast_vlan", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_mcast_octets", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_mcast", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_mcast_vlan", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_bcast_octets", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_bcast", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_bcast_vlan", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_errors", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_filter_vlan", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txf%d_filter_mac_sa", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
}
|
|
|
|
bmap >>= 1;
|
|
|
|
}
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bmap = bna_rx_rid_mask(&bnad->bna);
|
|
|
|
for (i = 0; bmap; i++) {
|
2010-08-24 11:24:12 +08:00
|
|
|
if (bmap & 1) {
|
|
|
|
sprintf(string, "rxf%d_ucast_octets", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_ucast", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_ucast_vlan", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_mcast_octets", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_mcast", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_mcast_vlan", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_bcast_octets", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_bcast", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_bcast_vlan", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxf%d_frame_drops", i);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
}
|
|
|
|
bmap >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
q_num = 0;
|
|
|
|
for (i = 0; i < bnad->num_rx; i++) {
|
|
|
|
if (!bnad->rx_info[i].rx)
|
|
|
|
continue;
|
|
|
|
for (j = 0; j < bnad->num_rxp_per_rx; j++) {
|
|
|
|
sprintf(string, "cq%d_producer_index", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "cq%d_consumer_index", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "cq%d_hw_producer_index",
|
|
|
|
q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
2011-08-30 23:27:43 +08:00
|
|
|
sprintf(string, "cq%d_intr", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "cq%d_poll", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "cq%d_schedule", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "cq%d_keep_poll", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "cq%d_complete", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
2010-08-24 11:24:12 +08:00
|
|
|
q_num++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
q_num = 0;
|
|
|
|
for (i = 0; i < bnad->num_rx; i++) {
|
|
|
|
if (!bnad->rx_info[i].rx)
|
|
|
|
continue;
|
|
|
|
for (j = 0; j < bnad->num_rxp_per_rx; j++) {
|
|
|
|
sprintf(string, "rxq%d_packets", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_bytes", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_packets_with_error",
|
|
|
|
q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_allocbuf_failed", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_producer_index", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_consumer_index", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
q_num++;
|
|
|
|
if (bnad->rx_info[i].rx_ctrl[j].ccb &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->
|
|
|
|
rcb[1] &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->
|
|
|
|
rcb[1]->rxq) {
|
|
|
|
sprintf(string, "rxq%d_packets", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_bytes", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string,
|
|
|
|
"rxq%d_packets_with_error", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_allocbuf_failed",
|
|
|
|
q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_producer_index",
|
|
|
|
q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "rxq%d_consumer_index",
|
|
|
|
q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
q_num++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
q_num = 0;
|
|
|
|
for (i = 0; i < bnad->num_tx; i++) {
|
|
|
|
if (!bnad->tx_info[i].tx)
|
|
|
|
continue;
|
|
|
|
for (j = 0; j < bnad->num_txq_per_tx; j++) {
|
|
|
|
sprintf(string, "txq%d_packets", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txq%d_bytes", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txq%d_producer_index", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txq%d_consumer_index", q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
sprintf(string, "txq%d_hw_consumer_index",
|
|
|
|
q_num);
|
|
|
|
string += ETH_GSTRING_LEN;
|
|
|
|
q_num++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_get_stats_count_locked(struct net_device *netdev)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
2011-08-30 23:27:43 +08:00
|
|
|
int i, j, count = 0, rxf_active_num = 0, txf_active_num = 0;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
u32 bmap;
|
2010-08-24 11:24:12 +08:00
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bmap = bna_tx_rid_mask(&bnad->bna);
|
|
|
|
for (i = 0; bmap; i++) {
|
2010-08-24 11:24:12 +08:00
|
|
|
if (bmap & 1)
|
|
|
|
txf_active_num++;
|
|
|
|
bmap >>= 1;
|
|
|
|
}
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bmap = bna_rx_rid_mask(&bnad->bna);
|
|
|
|
for (i = 0; bmap; i++) {
|
2010-08-24 11:24:12 +08:00
|
|
|
if (bmap & 1)
|
|
|
|
rxf_active_num++;
|
|
|
|
bmap >>= 1;
|
|
|
|
}
|
|
|
|
count = BNAD_ETHTOOL_STATS_NUM +
|
|
|
|
txf_active_num * BNAD_NUM_TXF_COUNTERS +
|
|
|
|
rxf_active_num * BNAD_NUM_RXF_COUNTERS;
|
|
|
|
|
|
|
|
for (i = 0; i < bnad->num_rx; i++) {
|
|
|
|
if (!bnad->rx_info[i].rx)
|
|
|
|
continue;
|
|
|
|
count += bnad->num_rxp_per_rx * BNAD_NUM_CQ_COUNTERS;
|
|
|
|
count += bnad->num_rxp_per_rx * BNAD_NUM_RXQ_COUNTERS;
|
|
|
|
for (j = 0; j < bnad->num_rxp_per_rx; j++)
|
|
|
|
if (bnad->rx_info[i].rx_ctrl[j].ccb &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1]->rxq)
|
|
|
|
count += BNAD_NUM_RXQ_COUNTERS;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < bnad->num_tx; i++) {
|
|
|
|
if (!bnad->tx_info[i].tx)
|
|
|
|
continue;
|
|
|
|
count += bnad->num_txq_per_tx * BNAD_NUM_TXQ_COUNTERS;
|
|
|
|
}
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_per_q_stats_fill(struct bnad *bnad, u64 *buf, int bi)
|
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
struct bna_rcb *rcb = NULL;
|
|
|
|
struct bna_tcb *tcb = NULL;
|
|
|
|
|
|
|
|
for (i = 0; i < bnad->num_rx; i++) {
|
|
|
|
if (!bnad->rx_info[i].rx)
|
|
|
|
continue;
|
|
|
|
for (j = 0; j < bnad->num_rxp_per_rx; j++)
|
|
|
|
if (bnad->rx_info[i].rx_ctrl[j].ccb &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->rcb[0] &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->rcb[0]->rxq) {
|
|
|
|
buf[bi++] = bnad->rx_info[i].rx_ctrl[j].
|
|
|
|
ccb->producer_index;
|
|
|
|
buf[bi++] = 0; /* ccb->consumer_index */
|
|
|
|
buf[bi++] = *(bnad->rx_info[i].rx_ctrl[j].
|
|
|
|
ccb->hw_producer_index);
|
2011-08-30 23:27:43 +08:00
|
|
|
|
|
|
|
buf[bi++] = bnad->rx_info[i].
|
|
|
|
rx_ctrl[j].rx_intr_ctr;
|
|
|
|
buf[bi++] = bnad->rx_info[i].
|
|
|
|
rx_ctrl[j].rx_poll_ctr;
|
|
|
|
buf[bi++] = bnad->rx_info[i].
|
|
|
|
rx_ctrl[j].rx_schedule;
|
|
|
|
buf[bi++] = bnad->rx_info[i].
|
|
|
|
rx_ctrl[j].rx_keep_poll;
|
|
|
|
buf[bi++] = bnad->rx_info[i].
|
|
|
|
rx_ctrl[j].rx_complete;
|
2010-08-24 11:24:12 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
for (i = 0; i < bnad->num_rx; i++) {
|
|
|
|
if (!bnad->rx_info[i].rx)
|
|
|
|
continue;
|
|
|
|
for (j = 0; j < bnad->num_rxp_per_rx; j++)
|
|
|
|
if (bnad->rx_info[i].rx_ctrl[j].ccb) {
|
|
|
|
if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[0] &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->
|
|
|
|
rcb[0]->rxq) {
|
|
|
|
rcb = bnad->rx_info[i].rx_ctrl[j].
|
|
|
|
ccb->rcb[0];
|
|
|
|
buf[bi++] = rcb->rxq->rx_packets;
|
|
|
|
buf[bi++] = rcb->rxq->rx_bytes;
|
|
|
|
buf[bi++] = rcb->rxq->
|
|
|
|
rx_packets_with_error;
|
|
|
|
buf[bi++] = rcb->rxq->
|
|
|
|
rxbuf_alloc_failed;
|
|
|
|
buf[bi++] = rcb->producer_index;
|
|
|
|
buf[bi++] = rcb->consumer_index;
|
|
|
|
}
|
|
|
|
if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
|
|
|
|
bnad->rx_info[i].rx_ctrl[j].ccb->
|
|
|
|
rcb[1]->rxq) {
|
|
|
|
rcb = bnad->rx_info[i].rx_ctrl[j].
|
|
|
|
ccb->rcb[1];
|
|
|
|
buf[bi++] = rcb->rxq->rx_packets;
|
|
|
|
buf[bi++] = rcb->rxq->rx_bytes;
|
|
|
|
buf[bi++] = rcb->rxq->
|
|
|
|
rx_packets_with_error;
|
|
|
|
buf[bi++] = rcb->rxq->
|
|
|
|
rxbuf_alloc_failed;
|
|
|
|
buf[bi++] = rcb->producer_index;
|
|
|
|
buf[bi++] = rcb->consumer_index;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < bnad->num_tx; i++) {
|
|
|
|
if (!bnad->tx_info[i].tx)
|
|
|
|
continue;
|
|
|
|
for (j = 0; j < bnad->num_txq_per_tx; j++)
|
|
|
|
if (bnad->tx_info[i].tcb[j] &&
|
|
|
|
bnad->tx_info[i].tcb[j]->txq) {
|
|
|
|
tcb = bnad->tx_info[i].tcb[j];
|
|
|
|
buf[bi++] = tcb->txq->tx_packets;
|
|
|
|
buf[bi++] = tcb->txq->tx_bytes;
|
|
|
|
buf[bi++] = tcb->producer_index;
|
|
|
|
buf[bi++] = tcb->consumer_index;
|
|
|
|
buf[bi++] = *(tcb->hw_consumer_index);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return bi;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bnad_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *stats,
|
|
|
|
u64 *buf)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
int i, j, bi;
|
2010-09-03 03:45:02 +08:00
|
|
|
unsigned long flags;
|
|
|
|
struct rtnl_link_stats64 *net_stats64;
|
2010-08-24 11:24:12 +08:00
|
|
|
u64 *stats64;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
u32 bmap;
|
2010-08-24 11:24:12 +08:00
|
|
|
|
|
|
|
mutex_lock(&bnad->conf_mutex);
|
|
|
|
if (bnad_get_stats_count_locked(netdev) != stats->n_stats) {
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Used bna_lock to sync reads from bna_stats, which is written
|
|
|
|
* under the same lock
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
|
|
|
bi = 0;
|
|
|
|
memset(buf, 0, stats->n_stats * sizeof(u64));
|
|
|
|
|
2010-09-03 03:45:02 +08:00
|
|
|
net_stats64 = (struct rtnl_link_stats64 *)buf;
|
|
|
|
bnad_netdev_qstats_fill(bnad, net_stats64);
|
|
|
|
bnad_netdev_hwstats_fill(bnad, net_stats64);
|
2010-08-24 11:24:12 +08:00
|
|
|
|
2010-09-03 03:45:02 +08:00
|
|
|
bi = sizeof(*net_stats64) / sizeof(u64);
|
2010-08-24 11:24:12 +08:00
|
|
|
|
2010-12-24 05:45:05 +08:00
|
|
|
/* Get netif_queue_stopped from stack */
|
|
|
|
bnad->stats.drv_stats.netif_queue_stopped = netif_queue_stopped(netdev);
|
|
|
|
|
2010-08-24 11:24:12 +08:00
|
|
|
/* Fill driver stats into ethtool buffers */
|
|
|
|
stats64 = (u64 *)&bnad->stats.drv_stats;
|
|
|
|
for (i = 0; i < sizeof(struct bnad_drv_stats) / sizeof(u64); i++)
|
|
|
|
buf[bi++] = stats64[i];
|
|
|
|
|
|
|
|
/* Fill hardware stats excluding the rxf/txf into ethtool bufs */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
stats64 = (u64 *) &bnad->stats.bna_stats->hw_stats;
|
2010-08-24 11:24:12 +08:00
|
|
|
for (i = 0;
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
i < offsetof(struct bfi_enet_stats, rxf_stats[0]) /
|
|
|
|
sizeof(u64);
|
2010-08-24 11:24:12 +08:00
|
|
|
i++)
|
|
|
|
buf[bi++] = stats64[i];
|
|
|
|
|
|
|
|
/* Fill txf stats into ethtool buffers */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bmap = bna_tx_rid_mask(&bnad->bna);
|
|
|
|
for (i = 0; bmap; i++) {
|
2010-08-24 11:24:12 +08:00
|
|
|
if (bmap & 1) {
|
|
|
|
stats64 = (u64 *)&bnad->stats.bna_stats->
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
hw_stats.txf_stats[i];
|
|
|
|
for (j = 0; j < sizeof(struct bfi_enet_stats_txf) /
|
2010-08-24 11:24:12 +08:00
|
|
|
sizeof(u64); j++)
|
|
|
|
buf[bi++] = stats64[j];
|
|
|
|
}
|
|
|
|
bmap >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fill rxf stats into ethtool buffers */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
bmap = bna_rx_rid_mask(&bnad->bna);
|
|
|
|
for (i = 0; bmap; i++) {
|
2010-08-24 11:24:12 +08:00
|
|
|
if (bmap & 1) {
|
|
|
|
stats64 = (u64 *)&bnad->stats.bna_stats->
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-09 00:21:39 +08:00
|
|
|
hw_stats.rxf_stats[i];
|
|
|
|
for (j = 0; j < sizeof(struct bfi_enet_stats_rxf) /
|
2010-08-24 11:24:12 +08:00
|
|
|
sizeof(u64); j++)
|
|
|
|
buf[bi++] = stats64[j];
|
|
|
|
}
|
|
|
|
bmap >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fill per Q stats into ethtool buffers */
|
|
|
|
bi = bnad_per_q_stats_fill(bnad, buf, bi);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
|
|
|
|
mutex_unlock(&bnad->conf_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_get_sset_count(struct net_device *netdev, int sset)
|
|
|
|
{
|
|
|
|
switch (sset) {
|
|
|
|
case ETH_SS_STATS:
|
|
|
|
return bnad_get_stats_count_locked(netdev);
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-12-22 21:29:45 +08:00
|
|
|
static u32
|
|
|
|
bnad_get_flash_partition_by_offset(struct bnad *bnad, u32 offset,
|
|
|
|
u32 *base_offset)
|
|
|
|
{
|
|
|
|
struct bfa_flash_attr *flash_attr;
|
|
|
|
struct bnad_iocmd_comp fcomp;
|
|
|
|
u32 i, flash_part = 0, ret;
|
|
|
|
unsigned long flags = 0;
|
|
|
|
|
|
|
|
flash_attr = kzalloc(sizeof(struct bfa_flash_attr), GFP_KERNEL);
|
|
|
|
if (!flash_attr)
|
2012-02-09 08:49:34 +08:00
|
|
|
return 0;
|
2011-12-22 21:29:45 +08:00
|
|
|
|
|
|
|
fcomp.bnad = bnad;
|
|
|
|
fcomp.comp_status = 0;
|
|
|
|
|
|
|
|
init_completion(&fcomp.comp);
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
|
|
|
ret = bfa_nw_flash_get_attr(&bnad->bna.flash, flash_attr,
|
|
|
|
bnad_cb_completion, &fcomp);
|
|
|
|
if (ret != BFA_STATUS_OK) {
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
kfree(flash_attr);
|
2012-02-09 08:49:34 +08:00
|
|
|
return 0;
|
2011-12-22 21:29:45 +08:00
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
wait_for_completion(&fcomp.comp);
|
|
|
|
ret = fcomp.comp_status;
|
|
|
|
|
|
|
|
/* Check for the flash type & base offset value */
|
|
|
|
if (ret == BFA_STATUS_OK) {
|
|
|
|
for (i = 0; i < flash_attr->npart; i++) {
|
|
|
|
if (offset >= flash_attr->part[i].part_off &&
|
|
|
|
offset < (flash_attr->part[i].part_off +
|
|
|
|
flash_attr->part[i].part_size)) {
|
|
|
|
flash_part = flash_attr->part[i].part_type;
|
|
|
|
*base_offset = flash_attr->part[i].part_off;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
kfree(flash_attr);
|
|
|
|
return flash_part;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_get_eeprom_len(struct net_device *netdev)
|
|
|
|
{
|
|
|
|
return BFA_TOTAL_FLASH_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
|
|
|
|
u8 *bytes)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
struct bnad_iocmd_comp fcomp;
|
|
|
|
u32 flash_part = 0, base_offset = 0;
|
|
|
|
unsigned long flags = 0;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/* Check if the flash read request is valid */
|
|
|
|
if (eeprom->magic != (bnad->pcidev->vendor |
|
|
|
|
(bnad->pcidev->device << 16)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
/* Query the flash partition based on the offset */
|
|
|
|
flash_part = bnad_get_flash_partition_by_offset(bnad,
|
|
|
|
eeprom->offset, &base_offset);
|
2012-02-09 08:49:34 +08:00
|
|
|
if (flash_part == 0)
|
2011-12-22 21:29:45 +08:00
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
fcomp.bnad = bnad;
|
|
|
|
fcomp.comp_status = 0;
|
|
|
|
|
|
|
|
init_completion(&fcomp.comp);
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
|
|
|
ret = bfa_nw_flash_read_part(&bnad->bna.flash, flash_part,
|
|
|
|
bnad->id, bytes, eeprom->len,
|
|
|
|
eeprom->offset - base_offset,
|
|
|
|
bnad_cb_completion, &fcomp);
|
|
|
|
if (ret != BFA_STATUS_OK) {
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
wait_for_completion(&fcomp.comp);
|
|
|
|
ret = fcomp.comp_status;
|
|
|
|
done:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bnad_set_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
|
|
|
|
u8 *bytes)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
struct bnad_iocmd_comp fcomp;
|
|
|
|
u32 flash_part = 0, base_offset = 0;
|
|
|
|
unsigned long flags = 0;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/* Check if the flash update request is valid */
|
|
|
|
if (eeprom->magic != (bnad->pcidev->vendor |
|
|
|
|
(bnad->pcidev->device << 16)))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Query the flash partition based on the offset */
|
|
|
|
flash_part = bnad_get_flash_partition_by_offset(bnad,
|
|
|
|
eeprom->offset, &base_offset);
|
2012-02-09 08:49:34 +08:00
|
|
|
if (flash_part == 0)
|
2011-12-22 21:29:45 +08:00
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
fcomp.bnad = bnad;
|
|
|
|
fcomp.comp_status = 0;
|
|
|
|
|
|
|
|
init_completion(&fcomp.comp);
|
|
|
|
spin_lock_irqsave(&bnad->bna_lock, flags);
|
|
|
|
ret = bfa_nw_flash_update_part(&bnad->bna.flash, flash_part,
|
|
|
|
bnad->id, bytes, eeprom->len,
|
|
|
|
eeprom->offset - base_offset,
|
|
|
|
bnad_cb_completion, &fcomp);
|
|
|
|
if (ret != BFA_STATUS_OK) {
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
|
|
|
wait_for_completion(&fcomp.comp);
|
|
|
|
ret = fcomp.comp_status;
|
|
|
|
done:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-02-01 23:02:41 +08:00
|
|
|
static int
|
|
|
|
bnad_flash_device(struct net_device *netdev, struct ethtool_flash *eflash)
|
|
|
|
{
|
|
|
|
struct bnad *bnad = netdev_priv(netdev);
|
|
|
|
struct bnad_iocmd_comp fcomp;
|
|
|
|
const struct firmware *fw;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = request_firmware(&fw, eflash->data, &bnad->pcidev->dev);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("BNA: Can't locate firmware %s\n", eflash->data);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
fcomp.bnad = bnad;
|
|
|
|
fcomp.comp_status = 0;
|
|
|
|
|
|
|
|
init_completion(&fcomp.comp);
|
|
|
|
spin_lock_irq(&bnad->bna_lock);
|
|
|
|
ret = bfa_nw_flash_update_part(&bnad->bna.flash, BFA_FLASH_PART_FWIMG,
|
|
|
|
bnad->id, (u8 *)fw->data, fw->size, 0,
|
|
|
|
bnad_cb_completion, &fcomp);
|
|
|
|
if (ret != BFA_STATUS_OK) {
|
|
|
|
pr_warn("BNA: Flash update failed with err: %d\n", ret);
|
|
|
|
ret = -EIO;
|
|
|
|
spin_unlock_irq(&bnad->bna_lock);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irq(&bnad->bna_lock);
|
|
|
|
wait_for_completion(&fcomp.comp);
|
|
|
|
if (fcomp.comp_status != BFA_STATUS_OK) {
|
|
|
|
ret = -EIO;
|
|
|
|
pr_warn("BNA: Firmware image update to flash failed with: %d\n",
|
|
|
|
fcomp.comp_status);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
release_firmware(fw);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-01-04 21:02:23 +08:00
|
|
|
static const struct ethtool_ops bnad_ethtool_ops = {
|
2010-08-24 11:24:12 +08:00
|
|
|
.get_settings = bnad_get_settings,
|
|
|
|
.set_settings = bnad_set_settings,
|
|
|
|
.get_drvinfo = bnad_get_drvinfo,
|
|
|
|
.get_wol = bnad_get_wol,
|
|
|
|
.get_link = ethtool_op_get_link,
|
|
|
|
.get_coalesce = bnad_get_coalesce,
|
|
|
|
.set_coalesce = bnad_set_coalesce,
|
|
|
|
.get_ringparam = bnad_get_ringparam,
|
|
|
|
.set_ringparam = bnad_set_ringparam,
|
|
|
|
.get_pauseparam = bnad_get_pauseparam,
|
|
|
|
.set_pauseparam = bnad_set_pauseparam,
|
|
|
|
.get_strings = bnad_get_strings,
|
|
|
|
.get_ethtool_stats = bnad_get_ethtool_stats,
|
2011-12-22 21:29:45 +08:00
|
|
|
.get_sset_count = bnad_get_sset_count,
|
|
|
|
.get_eeprom_len = bnad_get_eeprom_len,
|
|
|
|
.get_eeprom = bnad_get_eeprom,
|
|
|
|
.set_eeprom = bnad_set_eeprom,
|
2012-02-01 23:02:41 +08:00
|
|
|
.flash_device = bnad_flash_device,
|
2013-12-18 09:07:31 +08:00
|
|
|
.get_ts_info = ethtool_op_get_ts_info,
|
2010-08-24 11:24:12 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
void
|
|
|
|
bnad_set_ethtool_ops(struct net_device *netdev)
|
|
|
|
{
|
2014-05-11 08:12:32 +08:00
|
|
|
netdev->ethtool_ops = &bnad_ethtool_ops;
|
2010-08-24 11:24:12 +08:00
|
|
|
}
|