2015-03-09 17:00:19 +08:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
|
|
|
|
/ {
|
|
|
|
compatible = "snps,nsim_hs";
|
2015-10-28 21:36:10 +08:00
|
|
|
#address-cells = <2>;
|
|
|
|
#size-cells = <2>;
|
2015-03-09 17:00:19 +08:00
|
|
|
interrupt-parent = <&core_intc>;
|
|
|
|
|
2015-10-28 21:36:10 +08:00
|
|
|
memory {
|
|
|
|
device_type = "memory";
|
2015-12-15 16:27:16 +08:00
|
|
|
/* CONFIG_LINUX_LINK_BASE needs to match low mem start */
|
|
|
|
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
|
2015-10-28 21:36:10 +08:00
|
|
|
0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
|
|
|
|
};
|
|
|
|
|
2015-03-09 17:00:19 +08:00
|
|
|
chosen {
|
|
|
|
bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
|
|
|
|
};
|
|
|
|
|
|
|
|
aliases {
|
|
|
|
serial0 = &arcuart0;
|
|
|
|
};
|
|
|
|
|
|
|
|
fpga {
|
|
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
2015-10-28 21:36:10 +08:00
|
|
|
/* only perip space at end of low mem accessible */
|
|
|
|
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
|
2015-03-09 17:00:19 +08:00
|
|
|
|
|
|
|
core_intc: core-interrupt-controller {
|
|
|
|
compatible = "snps,archs-intc";
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
};
|
|
|
|
|
|
|
|
arcuart0: serial@c0fc1000 {
|
|
|
|
compatible = "snps,arc-uart";
|
|
|
|
reg = <0xc0fc1000 0x100>;
|
|
|
|
interrupts = <24>;
|
|
|
|
clock-frequency = <80000000>;
|
|
|
|
current-speed = <115200>;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
arcpct0: pct {
|
|
|
|
compatible = "snps,archs-pct";
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupts = <20>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|