2015-08-20 22:37:31 +08:00
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/*
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* 3-axis accelerometer driver for MXC4005XC Memsic sensor
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*
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* Copyright (c) 2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/iio/iio.h>
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#include <linux/acpi.h>
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#include <linux/regmap.h>
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#include <linux/iio/sysfs.h>
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2015-08-20 22:37:33 +08:00
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#include <linux/iio/trigger.h>
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2015-08-20 22:37:32 +08:00
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#include <linux/iio/buffer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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2015-08-20 22:37:31 +08:00
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#define MXC4005_DRV_NAME "mxc4005"
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2015-08-20 22:37:33 +08:00
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#define MXC4005_IRQ_NAME "mxc4005_event"
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2015-08-20 22:37:31 +08:00
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#define MXC4005_REGMAP_NAME "mxc4005_regmap"
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#define MXC4005_REG_XOUT_UPPER 0x03
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#define MXC4005_REG_XOUT_LOWER 0x04
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#define MXC4005_REG_YOUT_UPPER 0x05
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#define MXC4005_REG_YOUT_LOWER 0x06
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#define MXC4005_REG_ZOUT_UPPER 0x07
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#define MXC4005_REG_ZOUT_LOWER 0x08
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2015-08-20 22:37:33 +08:00
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#define MXC4005_REG_INT_MASK1 0x0B
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#define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01
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#define MXC4005_REG_INT_CLR1 0x01
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#define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01
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2015-08-20 22:37:31 +08:00
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#define MXC4005_REG_CONTROL 0x0D
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#define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5)
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#define MXC4005_CONTROL_FSR_SHIFT 5
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#define MXC4005_REG_DEVICE_ID 0x0E
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enum mxc4005_axis {
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AXIS_X,
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AXIS_Y,
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AXIS_Z,
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};
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enum mxc4005_range {
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MXC4005_RANGE_2G,
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MXC4005_RANGE_4G,
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MXC4005_RANGE_8G,
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};
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struct mxc4005_data {
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struct device *dev;
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struct mutex mutex;
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struct regmap *regmap;
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2015-08-20 22:37:33 +08:00
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struct iio_trigger *dready_trig;
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2015-08-20 22:37:32 +08:00
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__be16 buffer[8];
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2015-08-20 22:37:33 +08:00
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bool trigger_enabled;
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2015-08-20 22:37:31 +08:00
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};
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/*
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* MXC4005 can operate in the following ranges:
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* +/- 2G, 4G, 8G (the default +/-2G)
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*
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* (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
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* (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
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* (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
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*/
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static const struct {
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u8 range;
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int scale;
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} mxc4005_scale_table[] = {
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{MXC4005_RANGE_2G, 9582},
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{MXC4005_RANGE_4G, 19164},
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{MXC4005_RANGE_8G, 38329},
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};
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static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
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static struct attribute *mxc4005_attributes[] = {
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&iio_const_attr_in_accel_scale_available.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group mxc4005_attrs_group = {
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.attrs = mxc4005_attributes,
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};
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static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case MXC4005_REG_XOUT_UPPER:
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case MXC4005_REG_XOUT_LOWER:
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case MXC4005_REG_YOUT_UPPER:
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case MXC4005_REG_YOUT_LOWER:
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case MXC4005_REG_ZOUT_UPPER:
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case MXC4005_REG_ZOUT_LOWER:
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case MXC4005_REG_DEVICE_ID:
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case MXC4005_REG_CONTROL:
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return true;
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default:
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return false;
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}
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}
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static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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2015-08-20 22:37:33 +08:00
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case MXC4005_REG_INT_CLR1:
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case MXC4005_REG_INT_MASK1:
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2015-08-20 22:37:31 +08:00
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case MXC4005_REG_CONTROL:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config mxc4005_regmap_config = {
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.name = MXC4005_REGMAP_NAME,
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = MXC4005_REG_DEVICE_ID,
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.readable_reg = mxc4005_is_readable_reg,
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.writeable_reg = mxc4005_is_writeable_reg,
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};
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2015-08-20 22:37:32 +08:00
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static int mxc4005_read_xyz(struct mxc4005_data *data)
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{
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int ret;
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ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
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(u8 *) data->buffer, sizeof(data->buffer));
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if (ret < 0) {
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dev_err(data->dev, "failed to read axes\n");
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return ret;
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}
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return 0;
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}
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2015-08-20 22:37:31 +08:00
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static int mxc4005_read_axis(struct mxc4005_data *data,
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unsigned int addr)
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{
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__be16 reg;
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int ret;
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ret = regmap_bulk_read(data->regmap, addr, (u8 *) ®, sizeof(reg));
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if (ret < 0) {
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dev_err(data->dev, "failed to read reg %02x\n", addr);
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return ret;
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}
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return be16_to_cpu(reg);
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}
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static int mxc4005_read_scale(struct mxc4005_data *data)
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{
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unsigned int reg;
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int ret;
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int i;
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ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®);
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if (ret < 0) {
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dev_err(data->dev, "failed to read reg_control\n");
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return ret;
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}
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i = reg >> MXC4005_CONTROL_FSR_SHIFT;
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if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
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return -EINVAL;
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return mxc4005_scale_table[i].scale;
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}
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static int mxc4005_set_scale(struct mxc4005_data *data, int val)
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{
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unsigned int reg;
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int i;
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int ret;
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for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
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if (mxc4005_scale_table[i].scale == val) {
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reg = i << MXC4005_CONTROL_FSR_SHIFT;
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ret = regmap_update_bits(data->regmap,
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MXC4005_REG_CONTROL,
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MXC4005_REG_CONTROL_MASK_FSR,
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reg);
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if (ret < 0)
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dev_err(data->dev,
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"failed to write reg_control\n");
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return ret;
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}
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}
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return -EINVAL;
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}
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static int mxc4005_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct mxc4005_data *data = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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switch (chan->type) {
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case IIO_ACCEL:
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if (iio_buffer_enabled(indio_dev))
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return -EBUSY;
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ret = mxc4005_read_axis(data, chan->address);
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if (ret < 0)
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return ret;
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2015-08-20 22:37:32 +08:00
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*val = sign_extend32(ret >> chan->scan_type.shift,
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chan->scan_type.realbits - 1);
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2015-08-20 22:37:31 +08:00
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_SCALE:
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ret = mxc4005_read_scale(data);
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if (ret < 0)
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return ret;
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*val = 0;
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*val2 = ret;
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return IIO_VAL_INT_PLUS_MICRO;
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default:
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return -EINVAL;
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}
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}
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static int mxc4005_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct mxc4005_data *data = iio_priv(indio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_SCALE:
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if (val != 0)
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return -EINVAL;
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return mxc4005_set_scale(data, val2);
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default:
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return -EINVAL;
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}
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}
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static const struct iio_info mxc4005_info = {
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.read_raw = mxc4005_read_raw,
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.write_raw = mxc4005_write_raw,
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.attrs = &mxc4005_attrs_group,
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};
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2015-08-20 22:37:32 +08:00
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static const unsigned long mxc4005_scan_masks[] = {
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BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
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0
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};
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2015-08-20 22:37:31 +08:00
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#define MXC4005_CHANNEL(_axis, _addr) { \
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.type = IIO_ACCEL, \
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.modified = 1, \
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.channel2 = IIO_MOD_##_axis, \
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.address = _addr, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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2015-08-20 22:37:32 +08:00
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.scan_index = AXIS_##_axis, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 12, \
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.storagebits = 16, \
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.shift = 4, \
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.endianness = IIO_BE, \
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}, \
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2015-08-20 22:37:31 +08:00
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}
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static const struct iio_chan_spec mxc4005_channels[] = {
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MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
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MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
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MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
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2015-08-20 22:37:32 +08:00
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IIO_CHAN_SOFT_TIMESTAMP(3),
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2015-08-20 22:37:31 +08:00
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};
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2015-08-20 22:37:32 +08:00
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static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
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{
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struct iio_poll_func *pf = private;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct mxc4005_data *data = iio_priv(indio_dev);
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int ret;
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ret = mxc4005_read_xyz(data);
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if (ret < 0)
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goto err;
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iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
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pf->timestamp);
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err:
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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2015-08-20 22:37:33 +08:00
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static int mxc4005_clr_intr(struct mxc4005_data *data)
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{
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int ret;
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/* clear interrupt */
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ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
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MXC4005_REG_INT_CLR1_BIT_DRDYC);
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if (ret < 0) {
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dev_err(data->dev, "failed to write to reg_int_clr1\n");
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return ret;
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}
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return 0;
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}
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static int mxc4005_set_trigger_state(struct iio_trigger *trig,
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bool state)
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{
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struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
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struct mxc4005_data *data = iio_priv(indio_dev);
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int ret;
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mutex_lock(&data->mutex);
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if (state) {
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ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
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MXC4005_REG_INT_MASK1_BIT_DRDYE);
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} else {
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ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
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~MXC4005_REG_INT_MASK1_BIT_DRDYE);
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}
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if (ret < 0) {
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mutex_unlock(&data->mutex);
|
|
|
|
dev_err(data->dev, "failed to update reg_int_mask1");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
data->trigger_enabled = state;
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
|
|
|
|
{
|
|
|
|
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
|
|
|
|
struct mxc4005_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
if (!data->dready_trig)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return mxc4005_clr_intr(data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct iio_trigger_ops mxc4005_trigger_ops = {
|
|
|
|
.set_trigger_state = mxc4005_set_trigger_state,
|
|
|
|
.try_reenable = mxc4005_trigger_try_reen,
|
|
|
|
};
|
|
|
|
|
2015-08-20 22:37:31 +08:00
|
|
|
static int mxc4005_chip_init(struct mxc4005_data *data)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
unsigned int reg;
|
|
|
|
|
|
|
|
ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(data->dev, "failed to read chip id\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mxc4005_probe(struct i2c_client *client,
|
|
|
|
const struct i2c_device_id *id)
|
|
|
|
{
|
|
|
|
struct mxc4005_data *data;
|
|
|
|
struct iio_dev *indio_dev;
|
|
|
|
struct regmap *regmap;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
|
|
|
|
if (!indio_dev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
|
|
|
|
if (IS_ERR(regmap)) {
|
|
|
|
dev_err(&client->dev, "failed to initialize regmap\n");
|
|
|
|
return PTR_ERR(regmap);
|
|
|
|
}
|
|
|
|
|
|
|
|
data = iio_priv(indio_dev);
|
|
|
|
i2c_set_clientdata(client, indio_dev);
|
|
|
|
data->dev = &client->dev;
|
|
|
|
data->regmap = regmap;
|
|
|
|
|
|
|
|
ret = mxc4005_chip_init(data);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&client->dev, "failed to initialize chip\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_init(&data->mutex);
|
|
|
|
|
|
|
|
indio_dev->dev.parent = &client->dev;
|
|
|
|
indio_dev->channels = mxc4005_channels;
|
|
|
|
indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
|
2015-08-20 22:37:32 +08:00
|
|
|
indio_dev->available_scan_masks = mxc4005_scan_masks;
|
2015-08-20 22:37:31 +08:00
|
|
|
indio_dev->name = MXC4005_DRV_NAME;
|
|
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
|
|
indio_dev->info = &mxc4005_info;
|
|
|
|
|
2015-08-20 22:37:32 +08:00
|
|
|
ret = iio_triggered_buffer_setup(indio_dev,
|
2015-08-20 22:37:33 +08:00
|
|
|
iio_pollfunc_store_time,
|
2015-08-20 22:37:32 +08:00
|
|
|
mxc4005_trigger_handler,
|
|
|
|
NULL);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&client->dev,
|
|
|
|
"failed to setup iio triggered buffer\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-20 22:37:33 +08:00
|
|
|
if (client->irq > 0) {
|
|
|
|
data->dready_trig = devm_iio_trigger_alloc(&client->dev,
|
|
|
|
"%s-dev%d",
|
|
|
|
indio_dev->name,
|
|
|
|
indio_dev->id);
|
|
|
|
if (!data->dready_trig)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ret = devm_request_threaded_irq(&client->dev, client->irq,
|
|
|
|
iio_trigger_generic_data_rdy_poll,
|
|
|
|
NULL,
|
|
|
|
IRQF_TRIGGER_FALLING |
|
|
|
|
IRQF_ONESHOT,
|
|
|
|
MXC4005_IRQ_NAME,
|
|
|
|
data->dready_trig);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&client->dev,
|
|
|
|
"failed to init threaded irq\n");
|
|
|
|
goto err_buffer_cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
data->dready_trig->dev.parent = &client->dev;
|
|
|
|
data->dready_trig->ops = &mxc4005_trigger_ops;
|
|
|
|
iio_trigger_set_drvdata(data->dready_trig, indio_dev);
|
|
|
|
indio_dev->trig = data->dready_trig;
|
|
|
|
iio_trigger_get(indio_dev->trig);
|
|
|
|
ret = iio_trigger_register(data->dready_trig);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&client->dev,
|
|
|
|
"failed to register trigger\n");
|
|
|
|
goto err_trigger_unregister;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-20 22:37:31 +08:00
|
|
|
ret = iio_device_register(indio_dev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&client->dev,
|
|
|
|
"unable to register iio device %d\n", ret);
|
2015-08-20 22:37:32 +08:00
|
|
|
goto err_buffer_cleanup;
|
2015-08-20 22:37:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2015-08-20 22:37:32 +08:00
|
|
|
|
2015-08-20 22:37:33 +08:00
|
|
|
err_trigger_unregister:
|
|
|
|
iio_trigger_unregister(data->dready_trig);
|
2015-08-20 22:37:32 +08:00
|
|
|
err_buffer_cleanup:
|
|
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
|
|
|
|
|
|
|
return ret;
|
2015-08-20 22:37:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mxc4005_remove(struct i2c_client *client)
|
|
|
|
{
|
2015-08-20 22:37:32 +08:00
|
|
|
struct iio_dev *indio_dev = i2c_get_clientdata(client);
|
2015-08-20 22:37:33 +08:00
|
|
|
struct mxc4005_data *data = iio_priv(indio_dev);
|
2015-08-20 22:37:32 +08:00
|
|
|
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
|
|
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
2015-08-20 22:37:33 +08:00
|
|
|
if (data->dready_trig)
|
|
|
|
iio_trigger_unregister(data->dready_trig);
|
2015-08-20 22:37:31 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct acpi_device_id mxc4005_acpi_match[] = {
|
|
|
|
{"MXC4005", 0},
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
|
|
|
|
|
|
|
|
static const struct i2c_device_id mxc4005_id[] = {
|
|
|
|
{"mxc4005", 0},
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, mxc4005_id);
|
|
|
|
|
|
|
|
static struct i2c_driver mxc4005_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = MXC4005_DRV_NAME,
|
|
|
|
.acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
|
|
|
|
},
|
|
|
|
.probe = mxc4005_probe,
|
|
|
|
.remove = mxc4005_remove,
|
|
|
|
.id_table = mxc4005_id,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_i2c_driver(mxc4005_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");
|