2019-05-19 20:08:20 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2010-11-24 17:17:14 +08:00
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/*
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2021-05-17 22:03:49 +08:00
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* PCI glue driver for SPI PXA2xx compatible controllers.
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* CE4100's SPI device is more or less the same one as found on PXA.
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2010-11-24 17:17:14 +08:00
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*
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2021-05-17 22:03:49 +08:00
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* Copyright (C) 2016, 2021 Intel Corporation
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2010-11-24 17:17:14 +08:00
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*/
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2016-07-04 17:44:27 +08:00
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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2010-11-24 17:17:14 +08:00
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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2021-04-24 02:24:31 +08:00
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2010-11-24 17:17:14 +08:00
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#include <linux/spi/pxa2xx_spi.h>
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2014-08-20 01:29:19 +08:00
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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2014-04-18 00:26:06 +08:00
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enum {
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2016-07-04 17:44:27 +08:00
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PORT_QUARK_X1000,
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2014-04-18 00:26:06 +08:00
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PORT_BYT,
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2016-07-04 17:44:25 +08:00
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PORT_MRFLD,
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2014-08-20 01:29:21 +08:00
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PORT_BSW0,
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PORT_BSW1,
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PORT_BSW2,
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2016-07-04 17:44:27 +08:00
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PORT_CE4100,
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2021-02-09 00:38:15 +08:00
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PORT_LPT0,
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PORT_LPT1,
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2014-04-18 00:26:06 +08:00
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};
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struct pxa_spi_info {
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enum pxa_ssp_type type;
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int port_id;
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2022-02-26 01:23:40 +08:00
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unsigned int num_chipselect;
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2014-07-25 01:10:54 +08:00
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unsigned long max_clk_rate;
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2014-08-20 01:29:19 +08:00
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/* DMA channel request parameters */
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2016-07-04 17:44:24 +08:00
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bool (*dma_filter)(struct dma_chan *chan, void *param);
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2014-08-20 01:29:19 +08:00
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void *tx_param;
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void *rx_param;
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2016-07-04 17:44:24 +08:00
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2019-03-19 23:48:42 +08:00
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int dma_burst_size;
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2016-07-04 17:44:24 +08:00
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int (*setup)(struct pci_dev *pdev, struct pxa_spi_info *c);
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2014-04-18 00:26:06 +08:00
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};
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2014-08-20 01:29:19 +08:00
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static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
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static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
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2017-01-02 19:47:31 +08:00
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static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
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static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
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static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
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static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
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static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
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static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };
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2014-08-20 01:29:21 +08:00
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static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
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static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
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static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
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static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 };
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static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
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static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };
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2021-02-09 00:38:15 +08:00
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static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
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static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
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static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
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static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };
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2016-02-21 03:20:22 +08:00
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2014-08-20 01:29:19 +08:00
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static bool lpss_dma_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma_slave *dws = param;
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if (dws->dma_dev != chan->device->dev)
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return false;
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chan->private = dws;
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return true;
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}
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2022-02-24 03:16:37 +08:00
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static void lpss_dma_put_device(void *dma_dev)
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{
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pci_dev_put(dma_dev);
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}
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2016-07-04 17:44:24 +08:00
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static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
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{
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struct pci_dev *dma_dev;
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2022-02-24 03:16:37 +08:00
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int ret;
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2016-07-04 17:44:24 +08:00
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c->num_chipselect = 1;
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c->max_clk_rate = 50000000;
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dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
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2022-02-24 03:16:37 +08:00
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ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev);
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if (ret)
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return ret;
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2016-07-04 17:44:24 +08:00
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if (c->tx_param) {
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struct dw_dma_slave *slave = c->tx_param;
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slave->dma_dev = &dma_dev->dev;
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slave->m_master = 0;
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slave->p_master = 1;
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}
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if (c->rx_param) {
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struct dw_dma_slave *slave = c->rx_param;
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slave->dma_dev = &dma_dev->dev;
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slave->m_master = 0;
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slave->p_master = 1;
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}
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c->dma_filter = lpss_dma_filter;
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return 0;
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}
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2022-02-26 01:23:40 +08:00
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static int ce4100_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
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{
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c->num_chipselect = dev->devfn;
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c->max_clk_rate = 3686400;
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return 0;
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}
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2016-07-04 17:44:25 +08:00
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static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
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{
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2017-01-02 19:47:31 +08:00
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struct dw_dma_slave *tx, *rx;
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2022-02-24 03:16:37 +08:00
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struct pci_dev *dma_dev;
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int ret;
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2017-01-02 19:47:31 +08:00
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2016-07-04 17:44:25 +08:00
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switch (PCI_FUNC(dev->devfn)) {
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case 0:
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c->port_id = 3;
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c->num_chipselect = 1;
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2017-01-02 19:47:31 +08:00
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c->tx_param = &mrfld3_tx_param;
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c->rx_param = &mrfld3_rx_param;
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2016-07-04 17:44:25 +08:00
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break;
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case 1:
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c->port_id = 5;
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c->num_chipselect = 4;
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2017-01-02 19:47:31 +08:00
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c->tx_param = &mrfld5_tx_param;
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c->rx_param = &mrfld5_rx_param;
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2016-07-04 17:44:25 +08:00
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break;
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case 2:
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c->port_id = 6;
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c->num_chipselect = 1;
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2017-01-02 19:47:31 +08:00
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c->tx_param = &mrfld6_tx_param;
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c->rx_param = &mrfld6_rx_param;
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2016-07-04 17:44:25 +08:00
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break;
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default:
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return -ENODEV;
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}
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2017-01-02 19:47:31 +08:00
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2022-02-24 03:16:37 +08:00
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dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
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ret = devm_add_action_or_reset(&dev->dev, lpss_dma_put_device, dma_dev);
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if (ret)
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return ret;
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2017-01-02 19:47:31 +08:00
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tx = c->tx_param;
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tx->dma_dev = &dma_dev->dev;
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rx = c->rx_param;
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rx->dma_dev = &dma_dev->dev;
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c->dma_filter = lpss_dma_filter;
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2019-03-19 23:48:42 +08:00
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c->dma_burst_size = 8;
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2016-07-04 17:44:25 +08:00
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return 0;
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}
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2022-02-26 01:23:41 +08:00
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static int qrk_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
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{
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c->num_chipselect = 1;
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c->max_clk_rate = 50000000;
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return 0;
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}
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2014-04-18 00:26:06 +08:00
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static struct pxa_spi_info spi_info_configs[] = {
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[PORT_CE4100] = {
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.type = PXA25x_SSP,
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.port_id = -1,
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2022-02-26 01:23:40 +08:00
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.setup = ce4100_spi_setup,
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2014-04-18 00:26:06 +08:00
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},
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[PORT_BYT] = {
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2015-06-04 21:55:10 +08:00
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.type = LPSS_BYT_SSP,
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2014-04-18 00:26:06 +08:00
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.port_id = 0,
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2016-07-04 17:44:24 +08:00
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.setup = lpss_spi_setup,
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2014-08-20 01:29:19 +08:00
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.tx_param = &byt_tx_param,
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.rx_param = &byt_rx_param,
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2014-04-18 00:26:06 +08:00
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},
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2014-08-20 01:29:21 +08:00
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[PORT_BSW0] = {
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2016-07-06 04:12:05 +08:00
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.type = LPSS_BSW_SSP,
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2014-08-20 01:29:21 +08:00
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.port_id = 0,
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2016-07-04 17:44:24 +08:00
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.setup = lpss_spi_setup,
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2014-08-20 01:29:21 +08:00
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.tx_param = &bsw0_tx_param,
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.rx_param = &bsw0_rx_param,
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},
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[PORT_BSW1] = {
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2016-07-06 04:12:05 +08:00
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.type = LPSS_BSW_SSP,
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2014-08-20 01:29:21 +08:00
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.port_id = 1,
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2016-07-04 17:44:24 +08:00
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.setup = lpss_spi_setup,
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2014-08-20 01:29:21 +08:00
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.tx_param = &bsw1_tx_param,
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.rx_param = &bsw1_rx_param,
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},
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[PORT_BSW2] = {
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2016-07-06 04:12:05 +08:00
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.type = LPSS_BSW_SSP,
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2014-08-20 01:29:21 +08:00
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.port_id = 2,
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2016-07-04 17:44:24 +08:00
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.setup = lpss_spi_setup,
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2014-08-20 01:29:21 +08:00
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.tx_param = &bsw2_tx_param,
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.rx_param = &bsw2_rx_param,
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2014-04-18 00:26:06 +08:00
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},
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2016-07-04 17:44:25 +08:00
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[PORT_MRFLD] = {
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2021-05-10 20:41:34 +08:00
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.type = MRFLD_SSP,
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2016-07-04 17:44:25 +08:00
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.max_clk_rate = 25000000,
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.setup = mrfld_spi_setup,
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},
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2014-11-26 18:35:10 +08:00
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[PORT_QUARK_X1000] = {
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.type = QUARK_X1000_SSP,
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.port_id = -1,
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2022-02-26 01:23:41 +08:00
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.setup = qrk_spi_setup,
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2014-11-26 18:35:10 +08:00
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},
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2021-02-09 00:38:15 +08:00
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[PORT_LPT0] = {
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2016-02-21 03:20:22 +08:00
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.type = LPSS_LPT_SSP,
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.port_id = 0,
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2016-07-04 17:44:24 +08:00
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.setup = lpss_spi_setup,
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2021-02-09 00:38:15 +08:00
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.tx_param = &lpt0_tx_param,
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.rx_param = &lpt0_rx_param,
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},
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[PORT_LPT1] = {
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.type = LPSS_LPT_SSP,
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.port_id = 1,
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.setup = lpss_spi_setup,
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.tx_param = &lpt1_tx_param,
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.rx_param = &lpt1_rx_param,
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2016-02-21 03:20:22 +08:00
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},
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2014-04-18 00:26:06 +08:00
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};
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static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
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2010-11-24 17:17:14 +08:00
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const struct pci_device_id *ent)
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{
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2013-01-07 18:44:32 +08:00
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struct platform_device_info pi;
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2010-11-24 17:17:14 +08:00
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int ret;
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struct platform_device *pdev;
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2019-01-16 23:13:31 +08:00
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struct pxa2xx_spi_controller spi_pdata;
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2010-11-24 17:17:14 +08:00
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struct ssp_device *ssp;
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2014-04-18 00:26:06 +08:00
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struct pxa_spi_info *c;
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2014-07-25 01:10:54 +08:00
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char buf[40];
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2010-11-24 17:17:14 +08:00
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2013-01-07 18:44:32 +08:00
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ret = pcim_enable_device(dev);
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2010-11-24 17:17:14 +08:00
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if (ret)
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return ret;
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2013-01-07 18:44:32 +08:00
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ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI");
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2013-03-05 18:05:16 +08:00
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if (ret)
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2010-11-24 17:17:14 +08:00
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return ret;
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2014-04-18 00:26:06 +08:00
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c = &spi_info_configs[ent->driver_data];
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2022-02-26 01:23:42 +08:00
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ret = c->setup(dev, c);
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if (ret)
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return ret;
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2014-08-20 01:29:19 +08:00
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2016-07-04 17:44:24 +08:00
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memset(&spi_pdata, 0, sizeof(spi_pdata));
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2022-02-26 01:23:40 +08:00
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spi_pdata.num_chipselect = c->num_chipselect;
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2016-07-04 17:44:24 +08:00
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spi_pdata.dma_filter = c->dma_filter;
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2014-08-20 01:29:19 +08:00
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spi_pdata.tx_param = c->tx_param;
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spi_pdata.rx_param = c->rx_param;
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spi_pdata.enable_dma = c->rx_param && c->tx_param;
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2019-03-19 23:48:42 +08:00
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spi_pdata.dma_burst_size = c->dma_burst_size ? c->dma_burst_size : 1;
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2010-11-24 17:17:14 +08:00
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2013-01-07 18:44:33 +08:00
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ssp = &spi_pdata.ssp;
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2021-04-24 02:24:30 +08:00
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ssp->dev = &dev->dev;
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2010-11-24 17:17:14 +08:00
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ssp->phys_base = pci_resource_start(dev, 0);
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2013-01-07 18:44:32 +08:00
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ssp->mmio_base = pcim_iomap_table(dev)[0];
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2014-04-18 00:26:06 +08:00
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ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
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ssp->type = c->type;
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2010-11-24 17:17:14 +08:00
|
|
|
|
2017-01-21 17:06:39 +08:00
|
|
|
pci_set_master(dev);
|
|
|
|
|
|
|
|
ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
ssp->irq = pci_irq_vector(dev, 0);
|
|
|
|
|
2014-07-25 01:10:54 +08:00
|
|
|
snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
|
2021-03-24 14:16:34 +08:00
|
|
|
ssp->clk = clk_register_fixed_rate(&dev->dev, buf, NULL, 0,
|
2016-04-20 09:10:07 +08:00
|
|
|
c->max_clk_rate);
|
2021-05-21 17:47:45 +08:00
|
|
|
if (IS_ERR(ssp->clk))
|
2014-07-25 01:10:54 +08:00
|
|
|
return PTR_ERR(ssp->clk);
|
|
|
|
|
2013-01-07 18:44:32 +08:00
|
|
|
memset(&pi, 0, sizeof(pi));
|
2022-02-24 03:19:48 +08:00
|
|
|
pi.fwnode = dev_fwnode(&dev->dev);
|
2013-01-07 18:44:32 +08:00
|
|
|
pi.parent = &dev->dev;
|
|
|
|
pi.name = "pxa2xx-spi";
|
|
|
|
pi.id = ssp->port_id;
|
|
|
|
pi.data = &spi_pdata;
|
|
|
|
pi.size_data = sizeof(spi_pdata);
|
2010-11-24 17:17:14 +08:00
|
|
|
|
2013-01-07 18:44:32 +08:00
|
|
|
pdev = platform_device_register_full(&pi);
|
2014-07-25 01:10:54 +08:00
|
|
|
if (IS_ERR(pdev)) {
|
|
|
|
clk_unregister(ssp->clk);
|
2013-02-22 10:52:35 +08:00
|
|
|
return PTR_ERR(pdev);
|
2014-07-25 01:10:54 +08:00
|
|
|
}
|
2010-11-24 17:17:14 +08:00
|
|
|
|
2013-01-07 18:44:33 +08:00
|
|
|
pci_set_drvdata(dev, pdev);
|
2010-11-24 17:17:14 +08:00
|
|
|
|
2013-01-07 18:44:32 +08:00
|
|
|
return 0;
|
2010-11-24 17:17:14 +08:00
|
|
|
}
|
|
|
|
|
2014-04-18 00:26:06 +08:00
|
|
|
static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
|
2010-11-24 17:17:14 +08:00
|
|
|
{
|
2013-01-07 18:44:33 +08:00
|
|
|
struct platform_device *pdev = pci_get_drvdata(dev);
|
2019-01-16 23:13:31 +08:00
|
|
|
struct pxa2xx_spi_controller *spi_pdata;
|
2014-07-25 01:10:54 +08:00
|
|
|
|
|
|
|
spi_pdata = dev_get_platdata(&pdev->dev);
|
2010-11-24 17:17:14 +08:00
|
|
|
|
2013-01-07 18:44:33 +08:00
|
|
|
platform_device_unregister(pdev);
|
2014-07-25 01:10:54 +08:00
|
|
|
clk_unregister(spi_pdata->ssp.clk);
|
2010-11-24 17:17:14 +08:00
|
|
|
}
|
|
|
|
|
2014-04-18 00:26:06 +08:00
|
|
|
static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
|
2014-11-26 18:35:10 +08:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 },
|
2014-04-18 00:26:06 +08:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT },
|
2016-07-04 17:44:25 +08:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD },
|
2014-08-20 01:29:21 +08:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },
|
2016-07-04 17:44:27 +08:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
|
2021-02-09 00:38:16 +08:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c65), PORT_LPT0 },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c66), PORT_LPT1 },
|
2021-02-09 00:38:15 +08:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 },
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 },
|
|
|
|
{ }
|
2010-11-24 17:17:14 +08:00
|
|
|
};
|
2014-04-18 00:26:06 +08:00
|
|
|
MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);
|
2010-11-24 17:17:14 +08:00
|
|
|
|
2014-04-18 00:26:06 +08:00
|
|
|
static struct pci_driver pxa2xx_spi_pci_driver = {
|
|
|
|
.name = "pxa2xx_spi_pci",
|
|
|
|
.id_table = pxa2xx_spi_pci_devices,
|
|
|
|
.probe = pxa2xx_spi_pci_probe,
|
|
|
|
.remove = pxa2xx_spi_pci_remove,
|
2010-11-24 17:17:14 +08:00
|
|
|
};
|
|
|
|
|
2014-04-18 00:26:06 +08:00
|
|
|
module_pci_driver(pxa2xx_spi_pci_driver);
|
2010-11-24 17:17:14 +08:00
|
|
|
|
2014-04-18 00:26:06 +08:00
|
|
|
MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver");
|
2010-11-24 17:17:14 +08:00
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");
|