2017-12-04 22:07:49 +08:00
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#ifndef _ASM_INTEL_DS_H
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#define _ASM_INTEL_DS_H
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#include <linux/percpu-defs.h>
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#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
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#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
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/* The maximal number of PEBS events: */
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#define MAX_PEBS_EVENTS 8
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2018-03-09 10:15:41 +08:00
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#define MAX_FIXED_PEBS_EVENTS 3
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2017-12-04 22:07:49 +08:00
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/*
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* A debug store configuration.
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*
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* We only support architectures that use 64bit fields.
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*/
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struct debug_store {
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u64 bts_buffer_base;
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u64 bts_index;
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u64 bts_absolute_maximum;
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u64 bts_interrupt_threshold;
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u64 pebs_buffer_base;
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u64 pebs_index;
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u64 pebs_absolute_maximum;
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u64 pebs_interrupt_threshold;
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2018-03-09 10:15:41 +08:00
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u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS];
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2017-12-04 22:07:49 +08:00
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} __aligned(PAGE_SIZE);
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DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
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struct debug_store_buffers {
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char bts_buffer[BTS_BUFFER_SIZE];
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char pebs_buffer[PEBS_BUFFER_SIZE];
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};
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#endif
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