2019-05-19 20:07:45 +08:00
|
|
|
# SPDX-License-Identifier: GPL-2.0-only
|
2005-07-31 07:31:23 +08:00
|
|
|
#
|
|
|
|
# PHY Layer Configuration
|
|
|
|
#
|
|
|
|
|
2017-03-24 01:01:19 +08:00
|
|
|
menuconfig MDIO_DEVICE
|
|
|
|
tristate "MDIO bus device drivers"
|
2005-07-31 07:31:23 +08:00
|
|
|
help
|
2017-08-14 21:43:00 +08:00
|
|
|
MDIO devices and driver infrastructure code.
|
2016-10-17 23:49:55 +08:00
|
|
|
|
2019-03-22 07:34:44 +08:00
|
|
|
if MDIO_DEVICE
|
|
|
|
|
2017-07-26 23:13:59 +08:00
|
|
|
config MDIO_BUS
|
|
|
|
tristate
|
2018-04-28 03:41:49 +08:00
|
|
|
default m if PHYLIB=m
|
2017-07-26 23:13:59 +08:00
|
|
|
default MDIO_DEVICE
|
|
|
|
help
|
|
|
|
This internal symbol is used for link time dependencies and it
|
|
|
|
reflects whether the mdio_bus/mdio_device code is built as a
|
|
|
|
loadable module or built-in.
|
|
|
|
|
|
|
|
if MDIO_BUS
|
2005-07-31 07:31:23 +08:00
|
|
|
|
2020-07-05 17:55:47 +08:00
|
|
|
config MDIO_DEVRES
|
|
|
|
tristate
|
|
|
|
|
2019-07-31 13:39:57 +08:00
|
|
|
config MDIO_ASPEED
|
|
|
|
tristate "ASPEED MDIO bus controller"
|
|
|
|
depends on ARCH_ASPEED || COMPILE_TEST
|
|
|
|
depends on OF_MDIO && HAS_IOMEM
|
|
|
|
help
|
|
|
|
This module provides a driver for the independent MDIO bus
|
|
|
|
controllers found in the ASPEED AST2600 SoC. This is a driver for the
|
|
|
|
third revision of the ASPEED MDIO register interface - the first two
|
|
|
|
revisions are the "old" and "new" interfaces found in the AST2400 and
|
|
|
|
AST2500, embedded in the MAC. For legacy reasons, FTGMAC100 driver
|
|
|
|
continues to drive the embedded MDIO controller for the AST2400 and
|
|
|
|
AST2500 SoCs, so say N if AST2600 support is not required.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_BCM_IPROC
|
|
|
|
tristate "Broadcom iProc MDIO bus controller"
|
|
|
|
depends on ARCH_BCM_IPROC || COMPILE_TEST
|
|
|
|
depends on HAS_IOMEM && OF_MDIO
|
2020-01-28 08:38:28 +08:00
|
|
|
default ARCH_BCM_IPROC
|
2016-08-19 05:56:05 +08:00
|
|
|
help
|
|
|
|
This module provides a driver for the MDIO busses found in the
|
|
|
|
Broadcom iProc SoC's.
|
2012-10-15 03:07:16 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_BCM_UNIMAC
|
|
|
|
tristate "Broadcom UniMAC MDIO bus controller"
|
2018-07-17 23:42:04 +08:00
|
|
|
depends on HAS_IOMEM
|
2016-08-19 05:56:05 +08:00
|
|
|
help
|
|
|
|
This module provides a driver for the Broadcom UniMAC MDIO busses.
|
|
|
|
This hardware can be found in the Broadcom GENET Ethernet MAC
|
|
|
|
controllers as well as some Broadcom Ethernet switches such as the
|
|
|
|
Starfighter 2 switches.
|
2012-03-18 19:03:05 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_BITBANG
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Bitbanged MDIO buses"
|
2016-08-19 05:56:05 +08:00
|
|
|
help
|
|
|
|
This module implements the MDIO bus protocol in software,
|
|
|
|
for use by low level drivers that export the ability to
|
|
|
|
drive the relevant pins.
|
2005-07-31 07:31:23 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
If in doubt, say N.
|
2005-07-31 07:31:23 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_BUS_MUX
|
|
|
|
tristate
|
|
|
|
depends on OF_MDIO
|
|
|
|
help
|
|
|
|
This module provides a driver framework for MDIO bus
|
|
|
|
multiplexers which connect one of several child MDIO busses
|
|
|
|
to a parent bus. Switching between child busses is done by
|
|
|
|
device specific drivers.
|
2005-07-31 07:31:23 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_BUS_MUX_BCM_IPROC
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Broadcom iProc based MDIO bus multiplexers"
|
2016-08-19 05:56:05 +08:00
|
|
|
depends on OF && OF_MDIO && (ARCH_BCM_IPROC || COMPILE_TEST)
|
|
|
|
select MDIO_BUS_MUX
|
|
|
|
default ARCH_BCM_IPROC
|
|
|
|
help
|
|
|
|
This module provides a driver for MDIO bus multiplexers found in
|
|
|
|
iProc based Broadcom SoCs. This multiplexer connects one of several
|
|
|
|
child MDIO bus to a parent bus. Buses could be internal as well as
|
|
|
|
external and selection logic lies inside the same multiplexer.
|
2007-05-11 13:52:55 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_BUS_MUX_GPIO
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "GPIO controlled MDIO bus multiplexers"
|
2016-08-19 05:56:05 +08:00
|
|
|
depends on OF_GPIO && OF_MDIO
|
|
|
|
select MDIO_BUS_MUX
|
|
|
|
help
|
|
|
|
This module provides a driver for MDIO bus multiplexers that
|
|
|
|
are controlled via GPIO lines. The multiplexer connects one of
|
|
|
|
several child MDIO busses to a parent bus. Child bus
|
|
|
|
selection is under the control of GPIO lines.
|
2005-07-31 07:31:23 +08:00
|
|
|
|
2019-04-04 21:11:45 +08:00
|
|
|
config MDIO_BUS_MUX_MESON_G12A
|
|
|
|
tristate "Amlogic G12a based MDIO bus multiplexer"
|
|
|
|
depends on ARCH_MESON || COMPILE_TEST
|
|
|
|
depends on OF_MDIO && HAS_IOMEM && COMMON_CLK
|
|
|
|
select MDIO_BUS_MUX
|
|
|
|
default m if ARCH_MESON
|
|
|
|
help
|
|
|
|
This module provides a driver for the MDIO multiplexer/glue of
|
|
|
|
the amlogic g12a SoC. The multiplexers connects either the external
|
|
|
|
or the internal MDIO bus to the parent bus.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_BUS_MUX_MMIOREG
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "MMIO device-controlled MDIO bus multiplexers"
|
2016-08-19 05:56:05 +08:00
|
|
|
depends on OF_MDIO && HAS_IOMEM
|
|
|
|
select MDIO_BUS_MUX
|
|
|
|
help
|
|
|
|
This module provides a driver for MDIO bus multiplexers that
|
|
|
|
are controlled via a simple memory-mapped device, like an FPGA.
|
|
|
|
The multiplexer connects one of several child MDIO busses to a
|
|
|
|
parent bus. Child bus selection is under the control of one of
|
|
|
|
the FPGA's registers.
|
2015-07-17 11:19:46 +08:00
|
|
|
|
2017-09-01 19:56:03 +08:00
|
|
|
Currently, only 8/16/32 bits registers are supported.
|
2006-05-08 05:22:53 +08:00
|
|
|
|
2019-02-25 14:16:55 +08:00
|
|
|
config MDIO_BUS_MUX_MULTIPLEXER
|
|
|
|
tristate "MDIO bus multiplexer using kernel multiplexer subsystem"
|
2019-03-05 04:35:10 +08:00
|
|
|
depends on OF_MDIO
|
2019-02-25 14:16:55 +08:00
|
|
|
select MULTIPLEXER
|
|
|
|
select MDIO_BUS_MUX
|
|
|
|
help
|
|
|
|
This module provides a driver for MDIO bus multiplexer
|
|
|
|
that is controlled via the kernel multiplexer subsystem. The
|
|
|
|
bus multiplexer connects one of several child MDIO busses to
|
|
|
|
a parent bus. Child bus selection is under the control of
|
|
|
|
the kernel multiplexer subsystem.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_CAVIUM
|
2015-10-07 03:25:48 +08:00
|
|
|
tristate
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_GPIO
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "GPIO lib-based bitbanged MDIO buses"
|
2018-06-22 02:58:00 +08:00
|
|
|
depends on MDIO_BITBANG
|
|
|
|
depends on GPIOLIB || COMPILE_TEST
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Supports GPIO lib-based MDIO busses.
|
2006-10-03 23:18:13 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
To compile this driver as a module, choose M here: the module
|
|
|
|
will be called mdio-gpio.
|
|
|
|
|
|
|
|
config MDIO_HISI_FEMAC
|
|
|
|
tristate "Hisilicon FEMAC MDIO bus controller"
|
|
|
|
depends on HAS_IOMEM && OF_MDIO
|
|
|
|
help
|
|
|
|
This module provides a driver for the MDIO busses found in the
|
|
|
|
Hisilicon SoC that have an Fast Ethernet MAC.
|
|
|
|
|
2017-07-25 22:03:08 +08:00
|
|
|
config MDIO_I2C
|
|
|
|
tristate
|
|
|
|
depends on I2C
|
|
|
|
help
|
|
|
|
Support I2C based PHYs. This provides a MDIO bus bridged
|
|
|
|
to I2C to allow PHYs connected in I2C mode to be accessed
|
|
|
|
using the existing infrastructure.
|
|
|
|
|
|
|
|
This is library mode.
|
|
|
|
|
2020-04-30 17:07:05 +08:00
|
|
|
config MDIO_IPQ4019
|
|
|
|
tristate "Qualcomm IPQ4019 MDIO interface support"
|
|
|
|
depends on HAS_IOMEM && OF_MDIO
|
|
|
|
help
|
|
|
|
This driver supports the MDIO interface found in Qualcomm
|
|
|
|
IPQ40xx series Soc-s.
|
|
|
|
|
2020-03-05 05:38:32 +08:00
|
|
|
config MDIO_IPQ8064
|
|
|
|
tristate "Qualcomm IPQ8064 MDIO interface support"
|
|
|
|
depends on HAS_IOMEM && OF_MDIO
|
|
|
|
depends on MFD_SYSCON
|
|
|
|
help
|
|
|
|
This driver supports the MDIO interface found in the network
|
|
|
|
interface units of the IPQ8064 SoC
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_MOXART
|
2017-08-14 21:43:00 +08:00
|
|
|
tristate "MOXA ART MDIO interface support"
|
2018-05-18 04:07:45 +08:00
|
|
|
depends on ARCH_MOXART || COMPILE_TEST
|
2017-08-14 21:43:00 +08:00
|
|
|
help
|
|
|
|
This driver supports the MDIO interface found in the network
|
|
|
|
interface units of the MOXA ART SoC
|
2016-08-19 05:56:05 +08:00
|
|
|
|
2018-05-15 04:04:55 +08:00
|
|
|
config MDIO_MSCC_MIIM
|
|
|
|
tristate "Microsemi MIIM interface support"
|
|
|
|
depends on HAS_IOMEM
|
2020-07-13 23:12:07 +08:00
|
|
|
select MDIO_DEVRES
|
2018-05-15 04:04:55 +08:00
|
|
|
help
|
|
|
|
This driver supports the MIIM (MDIO) interface found in the network
|
2020-05-27 00:22:56 +08:00
|
|
|
switches of the Microsemi SoCs; it is recommended to switch on
|
|
|
|
CONFIG_HIGH_RES_TIMERS
|
2018-05-15 04:04:55 +08:00
|
|
|
|
2020-03-23 18:14:14 +08:00
|
|
|
config MDIO_MVUSB
|
|
|
|
tristate "Marvell USB to MDIO Adapter"
|
|
|
|
depends on USB
|
2020-08-02 15:49:53 +08:00
|
|
|
select MDIO_DEVRES
|
2020-03-23 18:14:14 +08:00
|
|
|
help
|
|
|
|
A USB to MDIO converter present on development boards for
|
|
|
|
Marvell's Link Street family of Ethernet switches.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MDIO_OCTEON
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Octeon and some ThunderX SOCs MDIO buses"
|
2019-08-03 14:01:56 +08:00
|
|
|
depends on (64BIT && OF_MDIO) || COMPILE_TEST
|
|
|
|
depends on HAS_IOMEM
|
2016-08-19 05:56:05 +08:00
|
|
|
select MDIO_CAVIUM
|
|
|
|
help
|
|
|
|
This module provides a driver for the Octeon and ThunderX MDIO
|
|
|
|
buses. It is required by the Octeon and ThunderX ethernet device
|
|
|
|
drivers on some systems.
|
|
|
|
|
|
|
|
config MDIO_SUN4I
|
|
|
|
tristate "Allwinner sun4i MDIO interface support"
|
2018-05-18 04:07:45 +08:00
|
|
|
depends on ARCH_SUNXI || COMPILE_TEST
|
2016-08-19 05:56:05 +08:00
|
|
|
help
|
|
|
|
This driver supports the MDIO interface found in the network
|
|
|
|
interface units of the Allwinner SoC that have an EMAC (A10,
|
|
|
|
A12, A10s, etc.)
|
|
|
|
|
|
|
|
config MDIO_THUNDER
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "ThunderX SOCs MDIO buses"
|
2016-08-19 05:56:05 +08:00
|
|
|
depends on 64BIT
|
|
|
|
depends on PCI
|
|
|
|
select MDIO_CAVIUM
|
|
|
|
help
|
|
|
|
This driver supports the MDIO interfaces found on Cavium
|
|
|
|
ThunderX SoCs when the MDIO bus device appears as a PCI
|
|
|
|
device.
|
|
|
|
|
|
|
|
config MDIO_XGENE
|
|
|
|
tristate "APM X-Gene SoC MDIO bus controller"
|
2016-10-07 02:22:51 +08:00
|
|
|
depends on ARCH_XGENE || COMPILE_TEST
|
2016-08-19 05:56:05 +08:00
|
|
|
help
|
|
|
|
This module provides a driver for the MDIO busses found in the
|
|
|
|
APM X-Gene SoC's.
|
|
|
|
|
2020-03-09 16:36:26 +08:00
|
|
|
config MDIO_XPCS
|
|
|
|
tristate "Synopsys DesignWare XPCS controller"
|
|
|
|
help
|
|
|
|
This module provides helper functions for Synopsys DesignWare XPCS
|
|
|
|
controllers.
|
|
|
|
|
2017-03-24 01:01:19 +08:00
|
|
|
endif
|
2019-03-22 07:34:44 +08:00
|
|
|
endif
|
2017-03-24 01:01:19 +08:00
|
|
|
|
phylink: add phylink infrastructure
The link between the ethernet MAC and its PHY has become more complex
as the interface evolves. This is especially true with serdes links,
where the part of the PHY is effectively integrated into the MAC.
Serdes links can be connected to a variety of devices, including SFF
modules soldered down onto the board with the MAC, a SFP cage with
a hotpluggable SFP module which may contain a PHY or directly modulate
the serdes signals onto optical media with or without a PHY, or even
a classical PHY connection.
Moreover, the negotiation information on serdes links comes in two
varieties - SGMII mode, where the PHY provides its speed/duplex/flow
control information to the MAC, and 1000base-X mode where both ends
exchange their abilities and each resolve the link capabilities.
This means we need a more flexible means to support these arrangements,
particularly with the hotpluggable nature of SFP, where the PHY can
be attached or detached after the network device has been brought up.
Ethtool information can come from multiple sources:
- we may have a PHY operating in either SGMII or 1000base-X mode, in
which case we take ethtool/mii data directly from the PHY.
- we may have a optical SFP module without a PHY, with the MAC
operating in 1000base-X mode - the ethtool/mii data needs to come
from the MAC.
- we may have a copper SFP module with a PHY whic can't be accessed,
which means we need to take ethtool/mii data from the MAC.
Phylink aims to solve this by providing an intermediary between the
MAC and PHY, providing a safe way for PHYs to be hotplugged, and
allowing a SFP driver to reconfigure the serdes connection.
Phylink also takes over support of fixed link connections, where the
speed/duplex/flow control are fixed, but link status may be controlled
by a GPIO signal. By avoiding the fixed-phy implementation, phylink
can provide a faster response to link events: fixed-phy has to wait for
phylib to operate its state machine, which can take several seconds.
In comparison, phylink takes milliseconds.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- remove sync status
- rework supported and advertisment handling
- add 1000base-x speed for fixed links
- use functionality exported from phy-core, reworking
__phylink_ethtool_ksettings_set for it
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-25 22:03:13 +08:00
|
|
|
config PHYLINK
|
|
|
|
tristate
|
|
|
|
depends on NETDEVICES
|
|
|
|
select PHYLIB
|
|
|
|
select SWPHY
|
|
|
|
help
|
|
|
|
PHYlink models the link between the PHY and MAC, allowing fixed
|
|
|
|
configuration links, PHYs, and Serdes links with MAC level
|
|
|
|
autonegotiation modes.
|
|
|
|
|
2017-09-18 20:59:20 +08:00
|
|
|
menuconfig PHYLIB
|
2018-04-28 03:41:49 +08:00
|
|
|
tristate "PHY Device support and infrastructure"
|
2017-09-18 20:59:20 +08:00
|
|
|
depends on NETDEVICES
|
|
|
|
select MDIO_DEVICE
|
2020-07-05 17:55:47 +08:00
|
|
|
select MDIO_DEVRES
|
2017-09-18 20:59:20 +08:00
|
|
|
help
|
|
|
|
Ethernet controllers are usually attached to PHY
|
|
|
|
devices. This option provides infrastructure for
|
|
|
|
managing PHY devices.
|
|
|
|
|
2017-03-24 01:01:19 +08:00
|
|
|
if PHYLIB
|
|
|
|
|
|
|
|
config SWPHY
|
|
|
|
bool
|
|
|
|
|
|
|
|
config LED_TRIGGER_PHY
|
|
|
|
bool "Support LED triggers for tracking link state"
|
|
|
|
depends on LEDS_TRIGGERS
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-03-24 01:01:19 +08:00
|
|
|
Adds support for a set of LED trigger events per-PHY. Link
|
|
|
|
state change will trigger the events, for consumption by an
|
|
|
|
LED class driver. There are triggers for each link speed currently
|
2017-11-02 07:49:18 +08:00
|
|
|
supported by the PHY and also a one common "link" trigger as a
|
|
|
|
logical-or of all the link speed ones.
|
|
|
|
All these triggers are named according to the following pattern:
|
2017-08-14 21:43:00 +08:00
|
|
|
<mii bus id>:<phy>:<speed>
|
2017-03-24 01:01:19 +08:00
|
|
|
|
|
|
|
Where speed is in the form:
|
2017-11-02 07:49:18 +08:00
|
|
|
<Speed in megabits>Mbps OR <Speed in gigabits>Gbps OR link
|
|
|
|
for any speed known to the PHY.
|
2017-03-24 01:01:19 +08:00
|
|
|
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
comment "MII PHY device drivers"
|
|
|
|
|
2017-07-25 22:03:39 +08:00
|
|
|
config SFP
|
|
|
|
tristate "SFP cage support"
|
|
|
|
depends on I2C && PHYLINK
|
2018-07-20 00:41:39 +08:00
|
|
|
depends on HWMON || HWMON=n
|
2017-07-25 22:03:39 +08:00
|
|
|
select MDIO_I2C
|
|
|
|
|
2019-08-16 21:09:59 +08:00
|
|
|
config ADIN_PHY
|
|
|
|
tristate "Analog Devices Industrial Ethernet PHYs"
|
|
|
|
help
|
|
|
|
Adds support for the Analog Devices Industrial Ethernet PHYs.
|
|
|
|
Currently supports the:
|
|
|
|
- ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
|
|
|
|
- ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
|
|
|
|
Ethernet PHY
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config AMD_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "AMD PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the am79c874
|
2015-10-07 03:25:49 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config AQUANTIA_PHY
|
2017-08-14 21:43:00 +08:00
|
|
|
tristate "Aquantia PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-08-14 21:43:00 +08:00
|
|
|
Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
|
2016-08-19 05:56:05 +08:00
|
|
|
|
2019-06-07 13:37:34 +08:00
|
|
|
config AX88796B_PHY
|
2018-04-19 10:05:18 +08:00
|
|
|
tristate "Asix PHYs"
|
|
|
|
help
|
|
|
|
Currently supports the Asix Electronics PHY found in the X-Surf 100
|
|
|
|
AX88796B package.
|
|
|
|
|
2009-07-01 09:29:36 +08:00
|
|
|
config BCM63XX_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Broadcom 63xx SOCs internal PHY"
|
2018-09-12 07:53:10 +08:00
|
|
|
depends on BCM63XX || COMPILE_TEST
|
2015-10-07 03:25:48 +08:00
|
|
|
select BCM_NET_PHYLIB
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2009-07-01 09:29:36 +08:00
|
|
|
Currently supports the 6348 and 6358 PHYs.
|
|
|
|
|
2014-02-14 08:08:45 +08:00
|
|
|
config BCM7XXX_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Broadcom 7xxx SOCs internal PHYs"
|
2015-10-07 03:25:48 +08:00
|
|
|
select BCM_NET_PHYLIB
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2014-02-14 08:08:45 +08:00
|
|
|
Currently supports the BCM7366, BCM7439, BCM7445, and
|
|
|
|
40nm and 65nm generation of BCM7xxx Set Top Box SoCs.
|
|
|
|
|
2012-06-27 15:33:38 +08:00
|
|
|
config BCM87XX_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Broadcom BCM8706 and BCM8727 PHYs"
|
2012-06-27 15:33:38 +08:00
|
|
|
help
|
|
|
|
Currently supports the BCM8706 and BCM8727 10G Ethernet PHYs.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config BCM_CYGNUS_PHY
|
2019-03-22 07:23:30 +08:00
|
|
|
tristate "Broadcom Cygnus/Omega SoC internal PHY"
|
2019-03-21 03:53:13 +08:00
|
|
|
depends on ARCH_BCM_IPROC || COMPILE_TEST
|
2016-08-19 05:56:05 +08:00
|
|
|
depends on MDIO_BCM_IPROC
|
|
|
|
select BCM_NET_PHYLIB
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
This PHY driver is for the 1G internal PHYs of the Broadcom
|
2019-03-21 03:53:13 +08:00
|
|
|
Cygnus and Omega Family SoC.
|
2007-05-12 07:24:51 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports internal PHY's used in the BCM11300,
|
|
|
|
BCM11320, BCM11350, BCM11360, BCM58300, BCM58302,
|
|
|
|
BCM58303 & BCM58305 Broadcom Cygnus SoCs.
|
2008-02-03 19:50:54 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config BCM_NET_PHYLIB
|
|
|
|
tristate
|
2008-11-29 08:14:12 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config BROADCOM_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Broadcom PHYs"
|
2016-08-19 05:56:05 +08:00
|
|
|
select BCM_NET_PHYLIB
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
|
2016-11-04 13:10:58 +08:00
|
|
|
BCM5481, BCM54810 and BCM5482 PHYs.
|
2008-11-29 08:42:41 +08:00
|
|
|
|
2020-04-21 02:21:12 +08:00
|
|
|
config BCM54140_PHY
|
|
|
|
tristate "Broadcom BCM54140 PHY"
|
|
|
|
depends on PHYLIB
|
2020-04-21 02:21:13 +08:00
|
|
|
depends on HWMON || HWMON=n
|
2020-04-21 02:21:12 +08:00
|
|
|
select BCM_NET_PHYLIB
|
|
|
|
help
|
|
|
|
Support the Broadcom BCM54140 Quad SGMII/QSGMII PHY.
|
|
|
|
|
|
|
|
This driver also supports the hardware monitoring of this PHY and
|
|
|
|
exposes voltage and temperature sensors.
|
|
|
|
|
2019-12-11 18:56:56 +08:00
|
|
|
config BCM84881_PHY
|
2020-02-18 00:03:11 +08:00
|
|
|
tristate "Broadcom BCM84881 PHY"
|
|
|
|
depends on PHYLIB
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2019-12-11 18:56:56 +08:00
|
|
|
Support the Broadcom BCM84881 PHY.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config CICADA_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Cicada PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the cis8204
|
2008-12-10 14:21:25 +08:00
|
|
|
|
2017-05-29 17:11:30 +08:00
|
|
|
config CORTINA_PHY
|
|
|
|
tristate "Cortina EDC CDR 10G Ethernet PHY"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-05-29 17:11:30 +08:00
|
|
|
Currently supports the CS4340 phy.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config DAVICOM_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Davicom PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports dm9161e and dm9131
|
2010-04-29 14:12:41 +08:00
|
|
|
|
2017-10-11 01:42:55 +08:00
|
|
|
config DP83822_PHY
|
2020-01-22 23:34:54 +08:00
|
|
|
tristate "Texas Instruments DP83822/825/826 PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2020-01-22 23:34:55 +08:00
|
|
|
Supports the DP83822, DP83825I, DP83825CM, DP83825CS, DP83825S,
|
|
|
|
DP83826C and DP83826NC PHYs.
|
2017-10-11 01:42:55 +08:00
|
|
|
|
2018-05-12 02:08:19 +08:00
|
|
|
config DP83TC811_PHY
|
2020-01-11 04:03:56 +08:00
|
|
|
tristate "Texas Instruments DP83TC811 PHY"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2020-01-11 04:03:56 +08:00
|
|
|
Supports the DP83TC811 PHY.
|
2018-05-12 02:08:19 +08:00
|
|
|
|
2015-10-21 05:28:57 +08:00
|
|
|
config DP83848_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Texas Instruments DP83848 PHY"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2015-10-21 05:28:57 +08:00
|
|
|
Supports the DP83848 PHY.
|
|
|
|
|
2015-06-02 22:34:37 +08:00
|
|
|
config DP83867_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Texas Instruments DP83867 Gigabit PHY"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2015-06-02 22:34:37 +08:00
|
|
|
Currently supports the DP83867 PHY.
|
|
|
|
|
2019-11-14 00:42:26 +08:00
|
|
|
config DP83869_PHY
|
|
|
|
tristate "Texas Instruments DP83869 Gigabit PHY"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2019-11-14 00:42:26 +08:00
|
|
|
Currently supports the DP83869 PHY. This PHY supports copper and
|
|
|
|
fiber connections.
|
|
|
|
|
2006-08-15 14:00:29 +08:00
|
|
|
config FIXED_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
|
2014-12-17 03:30:09 +08:00
|
|
|
depends on PHYLIB
|
2016-06-23 21:50:05 +08:00
|
|
|
select SWPHY
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2007-12-07 06:51:22 +08:00
|
|
|
Adds the platform "fixed" MDIO Bus to cover the boards that use
|
|
|
|
PHYs that are not connected to the real MDIO bus.
|
|
|
|
|
|
|
|
Currently tested with mpc866ads and mpc8349e-mitx.
|
2007-08-11 05:05:16 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config ICPLUS_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "ICPlus PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the IP175C and IP1001 PHYs.
|
2015-10-07 03:25:47 +08:00
|
|
|
|
2016-06-06 05:41:11 +08:00
|
|
|
config INTEL_XWAY_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Intel XWAY PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-06-06 05:41:11 +08:00
|
|
|
Supports the Intel XWAY (former Lantiq) 11G and 22E PHYs.
|
|
|
|
These PHYs are marked as standalone chips under the names
|
|
|
|
PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel
|
|
|
|
SoCs xRX200, xRX300, xRX330, xRX350 and xRX550.
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config LSI_ET1011C_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "LSI ET1011C PHY"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Supports the LSI ET1011C PHY.
|
2016-07-15 16:26:33 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config LXT_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Intel LXT PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the lxt970, lxt971
|
|
|
|
|
|
|
|
config MARVELL_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Marvell PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently has a driver for the 88E1011S
|
|
|
|
|
2017-06-05 19:23:16 +08:00
|
|
|
config MARVELL_10G_PHY
|
|
|
|
tristate "Marvell Alaska 10Gbit PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-06-05 19:23:16 +08:00
|
|
|
Support for the Marvell Alaska MV88X3310 and compatible PHYs.
|
|
|
|
|
2016-11-04 23:51:23 +08:00
|
|
|
config MESON_GXL_PHY
|
|
|
|
tristate "Amlogic Meson GXL Internal PHY"
|
2017-01-09 22:17:27 +08:00
|
|
|
depends on ARCH_MESON || COMPILE_TEST
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-11-04 23:51:23 +08:00
|
|
|
Currently has a driver for the Amlogic Meson GXL Internal PHY
|
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config MICREL_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Micrel PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Supports the KSZ9021, VSC8201, KS8001 PHYs.
|
|
|
|
|
|
|
|
config MICROCHIP_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Microchip PHYs"
|
2016-07-26 08:12:40 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Supports the LAN88XX PHYs.
|
2016-07-26 08:12:40 +08:00
|
|
|
|
2018-05-02 23:39:17 +08:00
|
|
|
config MICROCHIP_T1_PHY
|
|
|
|
tristate "Microchip T1 PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2018-05-02 23:39:17 +08:00
|
|
|
Supports the LAN87XX PHYs.
|
|
|
|
|
2016-08-05 20:24:21 +08:00
|
|
|
config MICROSEMI_PHY
|
2016-09-08 16:39:31 +08:00
|
|
|
tristate "Microsemi PHYs"
|
2020-01-14 06:31:46 +08:00
|
|
|
depends on MACSEC || MACSEC=n
|
2020-06-25 15:18:16 +08:00
|
|
|
select CRYPTO_LIB_AES if MACSEC
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
net: phy: mscc: add support for VSC8514 PHY.
The VSC8514 PHY is a 4-ports PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X, can communicate with the MAC via QSGMII.
The MAC interface protocol for each port within QSGMII can
be either 1000BASE-X or SGMII, if the QSGMII MAC that the VSC8514 is
connecting to supports this functionality.
VSC8514 also supports SGMII MAC-side autonegotiation on each individual
port, downshifting, can set the blinking pattern of each of its 4 LEDs,
SyncE, 1000BASE-T Ring Resiliency as well as HP Auto-MDIX detection.
This adds support for 10BASE-T, 100BASE-TX, and 1000BASE-T,
QSGMII link with the MAC, downshifting, HP Auto-MDIX detection
and blinking pattern for its 4 LEDs.
The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
If the PHYs haven't been reset before booting the Linux kernel and were
configured to use interrupts for e.g. link status updates, it is
required to clear the interrupts mask register of all PHYs before being
able to use interrupts with any PHY. The first PHY of the package that
will be init will take care of clearing all PHYs interrupts mask
registers. Thus, we need to keep track of the init sequence in the
package, if it's already been done or if it's to be done.
Most of the init sequence of a PHY of the package is common to all PHYs
in the package, thus we use the SMI broadcast feature which enables us
to propagate a write in one register of one PHY to all PHYs in the same
package.
Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Co-developed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-22 19:51:35 +08:00
|
|
|
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
|
2016-08-05 20:24:21 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config NATIONAL_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "National Semiconductor PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the DP83865 PHY.
|
|
|
|
|
2019-05-24 22:22:28 +08:00
|
|
|
config NXP_TJA11XX_PHY
|
|
|
|
tristate "NXP TJA11xx PHYs support"
|
|
|
|
depends on HWMON
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2019-05-24 22:22:28 +08:00
|
|
|
Currently supports the NXP TJA1100 and TJA1101 PHY.
|
|
|
|
|
2019-11-07 06:36:12 +08:00
|
|
|
config AT803X_PHY
|
|
|
|
tristate "Qualcomm Atheros AR803X PHYs"
|
2019-11-07 21:03:44 +08:00
|
|
|
depends on REGULATOR
|
2019-11-07 06:36:12 +08:00
|
|
|
help
|
2019-11-07 06:36:15 +08:00
|
|
|
Currently supports the AR8030, AR8031, AR8033 and AR8035 model
|
2019-11-07 06:36:12 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config QSEMI_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Quality Semiconductor PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the qs6612
|
|
|
|
|
|
|
|
config REALTEK_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "Realtek PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Supports the Realtek 821x PHY.
|
|
|
|
|
2017-10-08 21:40:08 +08:00
|
|
|
config RENESAS_PHY
|
|
|
|
tristate "Driver for Renesas PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-10-08 21:40:08 +08:00
|
|
|
Supports the Renesas PHYs uPD60620 and uPD60620A.
|
|
|
|
|
2017-08-10 21:56:40 +08:00
|
|
|
config ROCKCHIP_PHY
|
2019-09-23 23:52:43 +08:00
|
|
|
tristate "Driver for Rockchip Ethernet PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2019-09-23 23:52:43 +08:00
|
|
|
Currently supports the integrated Ethernet PHY.
|
2017-08-10 21:56:40 +08:00
|
|
|
|
2016-08-19 05:56:05 +08:00
|
|
|
config SMSC_PHY
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "SMSC PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
Currently supports the LAN83C185, LAN8187 and LAN8700 PHYs
|
|
|
|
|
|
|
|
config STE10XP
|
2016-08-19 05:56:06 +08:00
|
|
|
tristate "STMicroelectronics STe10Xp PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-08-19 05:56:05 +08:00
|
|
|
This is the driver for the STe100p and STe101p PHYs.
|
|
|
|
|
|
|
|
config TERANETICS_PHY
|
2017-08-14 21:43:00 +08:00
|
|
|
tristate "Teranetics PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-08-14 21:43:00 +08:00
|
|
|
Currently supports the Teranetics TN2020
|
2016-08-19 05:56:05 +08:00
|
|
|
|
|
|
|
config VITESSE_PHY
|
2017-08-14 21:43:00 +08:00
|
|
|
tristate "Vitesse PHYs"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-08-14 21:43:00 +08:00
|
|
|
Currently supports the vsc8244
|
2016-08-19 05:56:05 +08:00
|
|
|
|
2016-08-10 13:50:08 +08:00
|
|
|
config XILINX_GMII2RGMII
|
2017-08-14 21:43:00 +08:00
|
|
|
tristate "Xilinx GMII2RGMII converter driver"
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2017-08-14 21:43:00 +08:00
|
|
|
This driver support xilinx GMII to RGMII IP core it provides
|
|
|
|
the Reduced Gigabit Media Independent Interface(RGMII) between
|
|
|
|
Ethernet physical media devices and the Gigabit Ethernet controller.
|
2016-08-10 13:50:08 +08:00
|
|
|
|
2007-05-11 13:52:55 +08:00
|
|
|
endif # PHYLIB
|
2011-12-18 15:33:41 +08:00
|
|
|
|
|
|
|
config MICREL_KS8995MA
|
|
|
|
tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch"
|
|
|
|
depends on SPI
|