2014-11-15 01:18:23 +08:00
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/*
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* CPU-agnostic ARM page table allocator.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright (C) 2014 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
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iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
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#include <linux/atomic.h>
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2018-03-26 20:35:13 +08:00
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#include <linux/bitops.h>
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2014-11-15 01:18:23 +08:00
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#include <linux/iommu.h>
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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2016-01-27 19:10:32 +08:00
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#include <linux/dma-mapping.h>
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2014-11-15 01:18:23 +08:00
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2015-07-30 02:46:09 +08:00
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#include <asm/barrier.h>
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2014-11-15 01:18:23 +08:00
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#include "io-pgtable.h"
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2018-03-26 20:35:13 +08:00
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#define ARM_LPAE_MAX_ADDR_BITS 52
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2014-11-15 01:18:23 +08:00
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#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
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#define ARM_LPAE_MAX_LEVELS 4
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/* Struct accessors */
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#define io_pgtable_to_data(x) \
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container_of((x), struct arm_lpae_io_pgtable, iop)
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#define io_pgtable_ops_to_data(x) \
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io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
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/*
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* For consistency with the architecture, we always consider
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* ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
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*/
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#define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels)
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/*
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* Calculate the right shift amount to get to the portion describing level l
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* in a virtual address mapped by the pagetable in d.
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*/
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#define ARM_LPAE_LVL_SHIFT(l,d) \
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((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \
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* (d)->bits_per_level) + (d)->pg_shift)
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2015-12-08 02:18:53 +08:00
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#define ARM_LPAE_GRANULE(d) (1UL << (d)->pg_shift)
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2015-02-17 02:38:20 +08:00
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#define ARM_LPAE_PAGES_PER_PGD(d) \
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2015-12-08 02:18:53 +08:00
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DIV_ROUND_UP((d)->pgd_size, ARM_LPAE_GRANULE(d))
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2014-11-15 01:18:23 +08:00
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/*
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* Calculate the index at level l used to map virtual address a using the
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* pagetable in d.
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*/
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#define ARM_LPAE_PGD_IDX(l,d) \
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((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
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#define ARM_LPAE_LVL_IDX(a,l,d) \
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2015-02-17 02:38:20 +08:00
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(((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
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2014-11-15 01:18:23 +08:00
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((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
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/* Calculate the block/page mapping size at level l for pagetable in d. */
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#define ARM_LPAE_BLOCK_SIZE(l,d) \
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2017-04-03 20:12:10 +08:00
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(1ULL << (ilog2(sizeof(arm_lpae_iopte)) + \
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2014-11-15 01:18:23 +08:00
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((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
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/* Page table bits */
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#define ARM_LPAE_PTE_TYPE_SHIFT 0
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#define ARM_LPAE_PTE_TYPE_MASK 0x3
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#define ARM_LPAE_PTE_TYPE_BLOCK 1
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#define ARM_LPAE_PTE_TYPE_TABLE 3
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#define ARM_LPAE_PTE_TYPE_PAGE 3
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2018-03-26 20:35:13 +08:00
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#define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12)
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2014-12-15 05:34:50 +08:00
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#define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
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2014-11-15 01:18:23 +08:00
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#define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
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#define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
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#define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
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#define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
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#define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
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2014-12-15 05:34:50 +08:00
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#define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
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2014-11-15 01:18:23 +08:00
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#define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
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#define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
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/* Ignore the contiguous bit for block splitting */
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#define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
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#define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
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ARM_LPAE_PTE_ATTR_HI_MASK)
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
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/* Software bit for solving coherency races */
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#define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55)
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2014-11-15 01:18:23 +08:00
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/* Stage-1 PTE */
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#define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
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#define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
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#define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
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#define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
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/* Stage-2 PTE */
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#define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
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#define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
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#define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
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#define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
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#define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
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#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
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/* Register bits */
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#define ARM_32_LPAE_TCR_EAE (1 << 31)
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#define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
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2015-03-18 18:22:18 +08:00
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#define ARM_LPAE_TCR_EPD1 (1 << 23)
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2014-11-15 01:18:23 +08:00
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#define ARM_LPAE_TCR_TG0_4K (0 << 14)
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#define ARM_LPAE_TCR_TG0_64K (1 << 14)
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#define ARM_LPAE_TCR_TG0_16K (2 << 14)
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#define ARM_LPAE_TCR_SH0_SHIFT 12
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#define ARM_LPAE_TCR_SH0_MASK 0x3
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#define ARM_LPAE_TCR_SH_NS 0
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#define ARM_LPAE_TCR_SH_OS 2
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#define ARM_LPAE_TCR_SH_IS 3
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#define ARM_LPAE_TCR_ORGN0_SHIFT 10
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#define ARM_LPAE_TCR_IRGN0_SHIFT 8
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#define ARM_LPAE_TCR_RGN_MASK 0x3
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#define ARM_LPAE_TCR_RGN_NC 0
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#define ARM_LPAE_TCR_RGN_WBWA 1
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#define ARM_LPAE_TCR_RGN_WT 2
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#define ARM_LPAE_TCR_RGN_WB 3
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#define ARM_LPAE_TCR_SL0_SHIFT 6
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#define ARM_LPAE_TCR_SL0_MASK 0x3
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#define ARM_LPAE_TCR_T0SZ_SHIFT 0
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#define ARM_LPAE_TCR_SZ_MASK 0xf
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#define ARM_LPAE_TCR_PS_SHIFT 16
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#define ARM_LPAE_TCR_PS_MASK 0x7
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#define ARM_LPAE_TCR_IPS_SHIFT 32
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#define ARM_LPAE_TCR_IPS_MASK 0x7
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#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
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#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
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#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
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#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
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#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
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#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
|
2018-03-26 20:35:13 +08:00
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#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
|
2014-11-15 01:18:23 +08:00
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#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
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#define ARM_LPAE_MAIR_ATTR_MASK 0xff
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#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
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#define ARM_LPAE_MAIR_ATTR_NC 0x44
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#define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
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#define ARM_LPAE_MAIR_ATTR_IDX_NC 0
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#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
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#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
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/* IOPTE accessors */
|
2018-03-26 20:35:13 +08:00
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#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
|
2014-11-15 01:18:23 +08:00
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#define iopte_type(pte,l) \
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(((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
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#define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
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#define iopte_leaf(pte,l) \
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(l == (ARM_LPAE_MAX_LEVELS - 1) ? \
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(iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
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(iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
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struct arm_lpae_io_pgtable {
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struct io_pgtable iop;
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int levels;
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size_t pgd_size;
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unsigned long pg_shift;
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unsigned long bits_per_level;
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void *pgd;
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};
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typedef u64 arm_lpae_iopte;
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|
|
2018-03-26 20:35:13 +08:00
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static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr,
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|
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struct arm_lpae_io_pgtable *data)
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|
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{
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arm_lpae_iopte pte = paddr;
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/* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */
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return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK;
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}
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static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte,
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|
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struct arm_lpae_io_pgtable *data)
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|
|
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{
|
2018-03-29 19:24:52 +08:00
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|
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u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK;
|
2018-03-26 20:35:13 +08:00
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if (data->pg_shift < 16)
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return paddr;
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|
|
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/* Rotate the packed high-order bits back to the top */
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|
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return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4);
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|
|
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}
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|
|
|
|
2014-11-18 07:31:12 +08:00
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|
|
static bool selftest_running = false;
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|
|
|
|
2015-09-18 00:42:16 +08:00
|
|
|
static dma_addr_t __arm_lpae_dma_addr(void *pages)
|
2015-07-30 02:46:04 +08:00
|
|
|
{
|
2015-09-18 00:42:16 +08:00
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|
|
return (dma_addr_t)virt_to_phys(pages);
|
2015-07-30 02:46:04 +08:00
|
|
|
}
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|
|
static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
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|
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struct io_pgtable_cfg *cfg)
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{
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|
struct device *dev = cfg->iommu_dev;
|
2018-05-22 19:50:09 +08:00
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int order = get_order(size);
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struct page *p;
|
2015-07-30 02:46:04 +08:00
|
|
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dma_addr_t dma;
|
2018-05-22 19:50:09 +08:00
|
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|
void *pages;
|
2015-07-30 02:46:04 +08:00
|
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|
2018-05-22 19:50:09 +08:00
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|
VM_BUG_ON((gfp & __GFP_HIGHMEM));
|
2018-06-18 19:27:54 +08:00
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|
p = alloc_pages_node(dev ? dev_to_node(dev) : NUMA_NO_NODE,
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|
|
gfp | __GFP_ZERO, order);
|
2018-05-22 19:50:09 +08:00
|
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|
if (!p)
|
2015-07-30 02:46:04 +08:00
|
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|
return NULL;
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|
|
|
2018-05-22 19:50:09 +08:00
|
|
|
pages = page_address(p);
|
2017-06-22 23:53:53 +08:00
|
|
|
if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA)) {
|
2015-07-30 02:46:04 +08:00
|
|
|
dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
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|
|
if (dma_mapping_error(dev, dma))
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goto out_free;
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/*
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|
|
|
* We depend on the IOMMU being able to work with any physical
|
2015-09-18 00:42:16 +08:00
|
|
|
* address directly, so if the DMA layer suggests otherwise by
|
|
|
|
* translating or truncating them, that bodes very badly...
|
2015-07-30 02:46:04 +08:00
|
|
|
*/
|
2015-09-18 00:42:16 +08:00
|
|
|
if (dma != virt_to_phys(pages))
|
2015-07-30 02:46:04 +08:00
|
|
|
goto out_unmap;
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|
|
|
}
|
|
|
|
|
|
|
|
return pages;
|
|
|
|
|
|
|
|
out_unmap:
|
|
|
|
dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
|
|
|
|
dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
|
|
|
|
out_free:
|
2018-05-22 19:50:09 +08:00
|
|
|
__free_pages(p, order);
|
2015-07-30 02:46:04 +08:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __arm_lpae_free_pages(void *pages, size_t size,
|
|
|
|
struct io_pgtable_cfg *cfg)
|
|
|
|
{
|
2017-06-22 23:53:53 +08:00
|
|
|
if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
|
2015-09-18 00:42:16 +08:00
|
|
|
dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
|
2015-07-30 02:46:04 +08:00
|
|
|
size, DMA_TO_DEVICE);
|
2018-05-22 19:50:09 +08:00
|
|
|
free_pages((unsigned long)pages, get_order(size));
|
2015-07-30 02:46:04 +08:00
|
|
|
}
|
|
|
|
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep,
|
|
|
|
struct io_pgtable_cfg *cfg)
|
|
|
|
{
|
|
|
|
dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep),
|
|
|
|
sizeof(*ptep), DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
|
2015-07-30 02:46:04 +08:00
|
|
|
static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
|
2015-07-30 02:46:09 +08:00
|
|
|
struct io_pgtable_cfg *cfg)
|
2015-07-30 02:46:04 +08:00
|
|
|
{
|
|
|
|
*ptep = pte;
|
|
|
|
|
2017-06-22 23:53:53 +08:00
|
|
|
if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA))
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
__arm_lpae_sync_pte(ptep, cfg);
|
2015-07-30 02:46:04 +08:00
|
|
|
}
|
|
|
|
|
2018-02-06 01:59:19 +08:00
|
|
|
static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
|
|
|
|
unsigned long iova, size_t size, int lvl,
|
|
|
|
arm_lpae_iopte *ptep);
|
iommu/io-pgtable-arm: Unmap and free table when overwriting with block
When installing a block mapping, we unconditionally overwrite a non-leaf
PTE if we find one. However, this can cause a problem if the following
sequence of events occur:
(1) iommu_map called for a 4k (i.e. PAGE_SIZE) mapping at some address
- We initialise the page table all the way down to a leaf entry
- No TLB maintenance is required, because we're going from invalid
to valid.
(2) iommu_unmap is called on the mapping installed in (1)
- We walk the page table to the final (leaf) entry and zero it
- We only changed a valid leaf entry, so we invalidate leaf-only
(3) iommu_map is called on the same address as (1), but this time for
a 2MB (i.e. BLOCK_SIZE) mapping)
- We walk the page table down to the penultimate level, where we
find a table entry
- We overwrite the table entry with a block mapping and return
without any TLB maintenance and without freeing the memory used
by the now-orphaned table.
This last step can lead to a walk-cache caching the overwritten table
entry, causing unexpected faults when the new mapping is accessed by a
device. One way to fix this would be to collapse the page table when
freeing the last page at a given level, but this would require expensive
iteration on every map call. Instead, this patch detects the case when
we are overwriting a table entry and explicitly unmaps the table first,
which takes care of both freeing and TLB invalidation.
Cc: <stable@vger.kernel.org>
Reported-by: Brian Starkey <brian.starkey@arm.com>
Tested-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2015-08-11 23:48:32 +08:00
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
|
|
|
|
phys_addr_t paddr, arm_lpae_iopte prot,
|
|
|
|
int lvl, arm_lpae_iopte *ptep)
|
|
|
|
{
|
|
|
|
arm_lpae_iopte pte = prot;
|
|
|
|
|
|
|
|
if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS)
|
|
|
|
pte |= ARM_LPAE_PTE_NS;
|
|
|
|
|
|
|
|
if (lvl == ARM_LPAE_MAX_LEVELS - 1)
|
|
|
|
pte |= ARM_LPAE_PTE_TYPE_PAGE;
|
|
|
|
else
|
|
|
|
pte |= ARM_LPAE_PTE_TYPE_BLOCK;
|
|
|
|
|
|
|
|
pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
|
2018-03-26 20:35:13 +08:00
|
|
|
pte |= paddr_to_iopte(paddr, data);
|
2017-06-22 23:53:51 +08:00
|
|
|
|
|
|
|
__arm_lpae_set_pte(ptep, pte, &data->iop.cfg);
|
|
|
|
}
|
|
|
|
|
2014-11-15 01:18:23 +08:00
|
|
|
static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
|
|
|
|
unsigned long iova, phys_addr_t paddr,
|
|
|
|
arm_lpae_iopte prot, int lvl,
|
|
|
|
arm_lpae_iopte *ptep)
|
|
|
|
{
|
2017-06-22 23:53:51 +08:00
|
|
|
arm_lpae_iopte pte = *ptep;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
if (iopte_leaf(pte, lvl)) {
|
iommu/io-pgtable-arm: Unmap and free table when overwriting with block
When installing a block mapping, we unconditionally overwrite a non-leaf
PTE if we find one. However, this can cause a problem if the following
sequence of events occur:
(1) iommu_map called for a 4k (i.e. PAGE_SIZE) mapping at some address
- We initialise the page table all the way down to a leaf entry
- No TLB maintenance is required, because we're going from invalid
to valid.
(2) iommu_unmap is called on the mapping installed in (1)
- We walk the page table to the final (leaf) entry and zero it
- We only changed a valid leaf entry, so we invalidate leaf-only
(3) iommu_map is called on the same address as (1), but this time for
a 2MB (i.e. BLOCK_SIZE) mapping)
- We walk the page table down to the penultimate level, where we
find a table entry
- We overwrite the table entry with a block mapping and return
without any TLB maintenance and without freeing the memory used
by the now-orphaned table.
This last step can lead to a walk-cache caching the overwritten table
entry, causing unexpected faults when the new mapping is accessed by a
device. One way to fix this would be to collapse the page table when
freeing the last page at a given level, but this would require expensive
iteration on every map call. Instead, this patch detects the case when
we are overwriting a table entry and explicitly unmaps the table first,
which takes care of both freeing and TLB invalidation.
Cc: <stable@vger.kernel.org>
Reported-by: Brian Starkey <brian.starkey@arm.com>
Tested-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2015-08-11 23:48:32 +08:00
|
|
|
/* We require an unmap first */
|
2014-11-18 07:31:12 +08:00
|
|
|
WARN_ON(!selftest_running);
|
2014-11-15 01:18:23 +08:00
|
|
|
return -EEXIST;
|
2017-06-22 23:53:51 +08:00
|
|
|
} else if (iopte_type(pte, lvl) == ARM_LPAE_PTE_TYPE_TABLE) {
|
iommu/io-pgtable-arm: Unmap and free table when overwriting with block
When installing a block mapping, we unconditionally overwrite a non-leaf
PTE if we find one. However, this can cause a problem if the following
sequence of events occur:
(1) iommu_map called for a 4k (i.e. PAGE_SIZE) mapping at some address
- We initialise the page table all the way down to a leaf entry
- No TLB maintenance is required, because we're going from invalid
to valid.
(2) iommu_unmap is called on the mapping installed in (1)
- We walk the page table to the final (leaf) entry and zero it
- We only changed a valid leaf entry, so we invalidate leaf-only
(3) iommu_map is called on the same address as (1), but this time for
a 2MB (i.e. BLOCK_SIZE) mapping)
- We walk the page table down to the penultimate level, where we
find a table entry
- We overwrite the table entry with a block mapping and return
without any TLB maintenance and without freeing the memory used
by the now-orphaned table.
This last step can lead to a walk-cache caching the overwritten table
entry, causing unexpected faults when the new mapping is accessed by a
device. One way to fix this would be to collapse the page table when
freeing the last page at a given level, but this would require expensive
iteration on every map call. Instead, this patch detects the case when
we are overwriting a table entry and explicitly unmaps the table first,
which takes care of both freeing and TLB invalidation.
Cc: <stable@vger.kernel.org>
Reported-by: Brian Starkey <brian.starkey@arm.com>
Tested-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2015-08-11 23:48:32 +08:00
|
|
|
/*
|
|
|
|
* We need to unmap and free the old table before
|
|
|
|
* overwriting it with a block entry.
|
|
|
|
*/
|
|
|
|
arm_lpae_iopte *tblp;
|
|
|
|
size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
|
|
|
|
|
|
|
tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
|
|
|
|
if (WARN_ON(__arm_lpae_unmap(data, iova, sz, lvl, tblp) != sz))
|
|
|
|
return -EINVAL;
|
2014-11-18 07:31:12 +08:00
|
|
|
}
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
__arm_lpae_init_pte(data, paddr, prot, lvl, ptep);
|
|
|
|
return 0;
|
|
|
|
}
|
2014-12-15 05:34:50 +08:00
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table,
|
|
|
|
arm_lpae_iopte *ptep,
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
arm_lpae_iopte curr,
|
2017-06-22 23:53:51 +08:00
|
|
|
struct io_pgtable_cfg *cfg)
|
|
|
|
{
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
arm_lpae_iopte old, new;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
new = __pa(table) | ARM_LPAE_PTE_TYPE_TABLE;
|
|
|
|
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
|
|
|
|
new |= ARM_LPAE_PTE_NSTABLE;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2017-06-23 19:02:38 +08:00
|
|
|
/*
|
|
|
|
* Ensure the table itself is visible before its PTE can be.
|
|
|
|
* Whilst we could get away with cmpxchg64_release below, this
|
|
|
|
* doesn't have any ordering semantics when !CONFIG_SMP.
|
|
|
|
*/
|
|
|
|
dma_wmb();
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
|
|
|
|
old = cmpxchg64_relaxed(ptep, curr, new);
|
|
|
|
|
|
|
|
if ((cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) ||
|
|
|
|
(old & ARM_LPAE_PTE_SW_SYNC))
|
|
|
|
return old;
|
|
|
|
|
|
|
|
/* Even if it's not ours, there's no point waiting; just kick it */
|
|
|
|
__arm_lpae_sync_pte(ptep, cfg);
|
|
|
|
if (old == curr)
|
|
|
|
WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC);
|
|
|
|
|
|
|
|
return old;
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
|
|
|
|
phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
|
|
|
|
int lvl, arm_lpae_iopte *ptep)
|
|
|
|
{
|
|
|
|
arm_lpae_iopte *cptep, pte;
|
|
|
|
size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
size_t tblsz = ARM_LPAE_GRANULE(data);
|
2015-07-30 02:46:04 +08:00
|
|
|
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
/* Find our entry at the current level */
|
|
|
|
ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
|
|
|
|
|
|
|
|
/* If we can install a leaf entry at this level, then do so */
|
2015-07-30 02:46:04 +08:00
|
|
|
if (size == block_size && (size & cfg->pgsize_bitmap))
|
2014-11-15 01:18:23 +08:00
|
|
|
return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
|
|
|
|
|
|
|
|
/* We can't allocate tables at the final level */
|
|
|
|
if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Grab a pointer to the next level */
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
pte = READ_ONCE(*ptep);
|
2014-11-15 01:18:23 +08:00
|
|
|
if (!pte) {
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
cptep = __arm_lpae_alloc_pages(tblsz, GFP_ATOMIC, cfg);
|
2014-11-15 01:18:23 +08:00
|
|
|
if (!cptep)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
pte = arm_lpae_install_table(cptep, ptep, 0, cfg);
|
|
|
|
if (pte)
|
|
|
|
__arm_lpae_free_pages(cptep, tblsz, cfg);
|
|
|
|
} else if (!(cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) &&
|
|
|
|
!(pte & ARM_LPAE_PTE_SW_SYNC)) {
|
|
|
|
__arm_lpae_sync_pte(ptep, cfg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pte && !iopte_leaf(pte, lvl)) {
|
2014-11-15 01:18:23 +08:00
|
|
|
cptep = iopte_deref(pte, data);
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
} else if (pte) {
|
2017-02-27 20:30:25 +08:00
|
|
|
/* We require an unmap first */
|
|
|
|
WARN_ON(!selftest_running);
|
|
|
|
return -EEXIST;
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Rinse, repeat */
|
|
|
|
return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep);
|
|
|
|
}
|
|
|
|
|
|
|
|
static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
|
|
|
|
int prot)
|
|
|
|
{
|
|
|
|
arm_lpae_iopte pte;
|
|
|
|
|
|
|
|
if (data->iop.fmt == ARM_64_LPAE_S1 ||
|
|
|
|
data->iop.fmt == ARM_32_LPAE_S1) {
|
2017-01-06 21:28:09 +08:00
|
|
|
pte = ARM_LPAE_PTE_nG;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
|
|
|
|
pte |= ARM_LPAE_PTE_AP_RDONLY;
|
|
|
|
|
2017-01-06 21:28:09 +08:00
|
|
|
if (!(prot & IOMMU_PRIV))
|
|
|
|
pte |= ARM_LPAE_PTE_AP_UNPRIV;
|
|
|
|
|
2016-04-05 19:39:31 +08:00
|
|
|
if (prot & IOMMU_MMIO)
|
|
|
|
pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
|
|
|
|
<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
|
|
|
|
else if (prot & IOMMU_CACHE)
|
2014-11-15 01:18:23 +08:00
|
|
|
pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
|
|
|
|
<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
|
|
|
|
} else {
|
|
|
|
pte = ARM_LPAE_PTE_HAP_FAULT;
|
|
|
|
if (prot & IOMMU_READ)
|
|
|
|
pte |= ARM_LPAE_PTE_HAP_READ;
|
|
|
|
if (prot & IOMMU_WRITE)
|
|
|
|
pte |= ARM_LPAE_PTE_HAP_WRITE;
|
2016-04-05 19:39:31 +08:00
|
|
|
if (prot & IOMMU_MMIO)
|
|
|
|
pte |= ARM_LPAE_PTE_MEMATTR_DEV;
|
|
|
|
else if (prot & IOMMU_CACHE)
|
2014-11-15 01:18:23 +08:00
|
|
|
pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
|
|
|
|
else
|
|
|
|
pte |= ARM_LPAE_PTE_MEMATTR_NC;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (prot & IOMMU_NOEXEC)
|
|
|
|
pte |= ARM_LPAE_PTE_XN;
|
|
|
|
|
|
|
|
return pte;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
|
|
|
|
phys_addr_t paddr, size_t size, int iommu_prot)
|
|
|
|
{
|
|
|
|
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
|
|
|
arm_lpae_iopte *ptep = data->pgd;
|
2015-07-30 02:46:09 +08:00
|
|
|
int ret, lvl = ARM_LPAE_START_LVL(data);
|
2014-11-15 01:18:23 +08:00
|
|
|
arm_lpae_iopte prot;
|
|
|
|
|
|
|
|
/* If no access, then nothing to do */
|
|
|
|
if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
|
|
|
|
return 0;
|
|
|
|
|
2017-07-03 21:52:24 +08:00
|
|
|
if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
|
|
|
|
paddr >= (1ULL << data->iop.cfg.oas)))
|
|
|
|
return -ERANGE;
|
|
|
|
|
2014-11-15 01:18:23 +08:00
|
|
|
prot = arm_lpae_prot_to_pte(data, iommu_prot);
|
2015-07-30 02:46:09 +08:00
|
|
|
ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
|
|
|
|
/*
|
|
|
|
* Synchronise all PTE updates for the new mapping before there's
|
|
|
|
* a chance for anything to kick off a table walk for the new iova.
|
|
|
|
*/
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
return ret;
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
|
|
|
|
arm_lpae_iopte *ptep)
|
|
|
|
{
|
|
|
|
arm_lpae_iopte *start, *end;
|
|
|
|
unsigned long table_size;
|
|
|
|
|
|
|
|
if (lvl == ARM_LPAE_START_LVL(data))
|
|
|
|
table_size = data->pgd_size;
|
|
|
|
else
|
2015-12-08 02:18:53 +08:00
|
|
|
table_size = ARM_LPAE_GRANULE(data);
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
start = ptep;
|
2015-12-16 00:08:12 +08:00
|
|
|
|
|
|
|
/* Only leaf entries at the last level */
|
|
|
|
if (lvl == ARM_LPAE_MAX_LEVELS - 1)
|
|
|
|
end = ptep;
|
|
|
|
else
|
|
|
|
end = (void *)ptep + table_size;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
while (ptep != end) {
|
|
|
|
arm_lpae_iopte pte = *ptep++;
|
|
|
|
|
|
|
|
if (!pte || iopte_leaf(pte, lvl))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
|
|
|
|
}
|
|
|
|
|
2015-07-30 02:46:04 +08:00
|
|
|
__arm_lpae_free_pages(start, table_size, &data->iop.cfg);
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void arm_lpae_free_pgtable(struct io_pgtable *iop)
|
|
|
|
{
|
|
|
|
struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
|
|
|
|
|
|
|
|
__arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd);
|
|
|
|
kfree(data);
|
|
|
|
}
|
|
|
|
|
2018-02-06 01:59:19 +08:00
|
|
|
static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
|
|
|
|
unsigned long iova, size_t size,
|
|
|
|
arm_lpae_iopte blk_pte, int lvl,
|
|
|
|
arm_lpae_iopte *ptep)
|
2014-11-15 01:18:23 +08:00
|
|
|
{
|
2017-06-22 23:53:51 +08:00
|
|
|
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
|
|
|
arm_lpae_iopte pte, *tablep;
|
2014-11-15 01:18:23 +08:00
|
|
|
phys_addr_t blk_paddr;
|
2017-06-22 23:53:51 +08:00
|
|
|
size_t tablesz = ARM_LPAE_GRANULE(data);
|
|
|
|
size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
|
|
|
|
int i, unmap_idx = -1;
|
|
|
|
|
|
|
|
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
|
|
|
|
return 0;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg);
|
|
|
|
if (!tablep)
|
|
|
|
return 0; /* Bytes unmapped */
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
if (size == split_sz)
|
|
|
|
unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data);
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2018-03-26 20:35:13 +08:00
|
|
|
blk_paddr = iopte_to_paddr(blk_pte, data);
|
2017-06-22 23:53:51 +08:00
|
|
|
pte = iopte_prot(blk_pte);
|
|
|
|
|
|
|
|
for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) {
|
2014-11-15 01:18:23 +08:00
|
|
|
/* Unmap! */
|
2017-06-22 23:53:51 +08:00
|
|
|
if (i == unmap_idx)
|
2014-11-15 01:18:23 +08:00
|
|
|
continue;
|
|
|
|
|
2017-06-22 23:53:51 +08:00
|
|
|
__arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]);
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
pte = arm_lpae_install_table(tablep, ptep, blk_pte, cfg);
|
|
|
|
if (pte != blk_pte) {
|
|
|
|
__arm_lpae_free_pages(tablep, tablesz, cfg);
|
|
|
|
/*
|
|
|
|
* We may race against someone unmapping another part of this
|
|
|
|
* block, but anything else is invalid. We can't misinterpret
|
|
|
|
* a page entry here since we're never at the last level.
|
|
|
|
*/
|
|
|
|
if (iopte_type(pte, lvl - 1) != ARM_LPAE_PTE_TYPE_TABLE)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
tablep = iopte_deref(pte, data);
|
2018-09-07 00:59:50 +08:00
|
|
|
} else if (unmap_idx >= 0) {
|
|
|
|
io_pgtable_tlb_add_flush(&data->iop, iova, size, size, true);
|
2018-09-21 00:10:24 +08:00
|
|
|
io_pgtable_tlb_sync(&data->iop);
|
2018-09-07 00:59:50 +08:00
|
|
|
return size;
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
}
|
2017-06-22 23:53:51 +08:00
|
|
|
|
2018-09-07 00:59:50 +08:00
|
|
|
return __arm_lpae_unmap(data, iova, size, lvl, tablep);
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
2018-02-06 01:59:19 +08:00
|
|
|
static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
|
|
|
|
unsigned long iova, size_t size, int lvl,
|
|
|
|
arm_lpae_iopte *ptep)
|
2014-11-15 01:18:23 +08:00
|
|
|
{
|
|
|
|
arm_lpae_iopte pte;
|
2016-01-27 01:13:14 +08:00
|
|
|
struct io_pgtable *iop = &data->iop;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2015-12-05 01:52:58 +08:00
|
|
|
/* Something went horribly wrong and we ran out of page table */
|
|
|
|
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
|
|
|
|
return 0;
|
|
|
|
|
2014-11-15 01:18:23 +08:00
|
|
|
ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
pte = READ_ONCE(*ptep);
|
2015-12-05 01:52:58 +08:00
|
|
|
if (WARN_ON(!pte))
|
2014-11-15 01:18:23 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* If the size matches this level, we're in the right place */
|
2017-06-22 23:53:51 +08:00
|
|
|
if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
|
2016-01-27 01:13:14 +08:00
|
|
|
__arm_lpae_set_pte(ptep, 0, &iop->cfg);
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
if (!iopte_leaf(pte, lvl)) {
|
|
|
|
/* Also flush any partial walks */
|
2016-01-27 01:13:14 +08:00
|
|
|
io_pgtable_tlb_add_flush(iop, iova, size,
|
|
|
|
ARM_LPAE_GRANULE(data), false);
|
|
|
|
io_pgtable_tlb_sync(iop);
|
2014-11-15 01:18:23 +08:00
|
|
|
ptep = iopte_deref(pte, data);
|
|
|
|
__arm_lpae_free_pgtable(data, lvl + 1, ptep);
|
2018-09-21 00:10:24 +08:00
|
|
|
} else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) {
|
|
|
|
/*
|
|
|
|
* Order the PTE update against queueing the IOVA, to
|
|
|
|
* guarantee that a flush callback from a different CPU
|
|
|
|
* has observed it before the TLBIALL can be issued.
|
|
|
|
*/
|
|
|
|
smp_wmb();
|
2014-11-15 01:18:23 +08:00
|
|
|
} else {
|
2016-01-27 01:13:14 +08:00
|
|
|
io_pgtable_tlb_add_flush(iop, iova, size, size, true);
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return size;
|
|
|
|
} else if (iopte_leaf(pte, lvl)) {
|
|
|
|
/*
|
|
|
|
* Insert a table at the next level to map the old region,
|
|
|
|
* minus the part we want to unmap
|
|
|
|
*/
|
2017-06-22 23:53:51 +08:00
|
|
|
return arm_lpae_split_blk_unmap(data, iova, size, pte,
|
|
|
|
lvl + 1, ptep);
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Keep on walkin' */
|
|
|
|
ptep = iopte_deref(pte, data);
|
|
|
|
return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
|
|
|
|
}
|
|
|
|
|
2018-02-06 01:59:19 +08:00
|
|
|
static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
|
|
|
|
size_t size)
|
2014-11-15 01:18:23 +08:00
|
|
|
{
|
|
|
|
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
|
|
|
arm_lpae_iopte *ptep = data->pgd;
|
|
|
|
int lvl = ARM_LPAE_START_LVL(data);
|
|
|
|
|
2017-07-03 21:52:24 +08:00
|
|
|
if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
|
|
|
|
return 0;
|
|
|
|
|
2017-09-28 22:55:01 +08:00
|
|
|
return __arm_lpae_unmap(data, iova, size, lvl, ptep);
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
|
|
|
|
unsigned long iova)
|
|
|
|
{
|
|
|
|
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
|
|
|
arm_lpae_iopte pte, *ptep = data->pgd;
|
|
|
|
int lvl = ARM_LPAE_START_LVL(data);
|
|
|
|
|
|
|
|
do {
|
|
|
|
/* Valid IOPTE pointer? */
|
|
|
|
if (!ptep)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Grab the IOPTE we're interested in */
|
iommu/io-pgtable-arm: Support lockless operation
For parallel I/O with multiple concurrent threads servicing the same
device (or devices, if several share a domain), serialising page table
updates becomes a massive bottleneck. On reflection, though, we don't
strictly need to do that - for valid IOMMU API usage, there are in fact
only two races that we need to guard against: multiple map requests for
different blocks within the same region, when the intermediate-level
table for that region does not yet exist; and multiple unmaps of
different parts of the same block entry. Both of those are fairly easily
solved by using a cmpxchg to install the new table, such that if we then
find that someone else's table got there first, we can simply free ours
and continue.
Make the requisite changes such that we can withstand being called
without the caller maintaining a lock. In theory, this opens up a few
corners in which wildly misbehaving callers making nonsensical
overlapping requests might lead to crashes instead of just unpredictable
results, but correct code really does not deserve to pay a significant
performance cost for the sake of masking bugs in theoretical broken code.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-06-22 23:53:54 +08:00
|
|
|
ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
|
|
|
|
pte = READ_ONCE(*ptep);
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
/* Valid entry? */
|
|
|
|
if (!pte)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Leaf entry? */
|
|
|
|
if (iopte_leaf(pte,lvl))
|
|
|
|
goto found_translation;
|
|
|
|
|
|
|
|
/* Take it to the next level */
|
|
|
|
ptep = iopte_deref(pte, data);
|
|
|
|
} while (++lvl < ARM_LPAE_MAX_LEVELS);
|
|
|
|
|
|
|
|
/* Ran out of page tables to walk */
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
found_translation:
|
2016-06-17 01:21:19 +08:00
|
|
|
iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
|
2018-03-26 20:35:13 +08:00
|
|
|
return iopte_to_paddr(pte, data) | iova;
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
|
|
|
|
{
|
2018-03-26 20:35:13 +08:00
|
|
|
unsigned long granule, page_sizes;
|
|
|
|
unsigned int max_addr_bits = 48;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to restrict the supported page sizes to match the
|
|
|
|
* translation regime for a particular granule. Aim to match
|
|
|
|
* the CPU page size if possible, otherwise prefer smaller sizes.
|
|
|
|
* While we're at it, restrict the block sizes to match the
|
|
|
|
* chosen granule.
|
|
|
|
*/
|
|
|
|
if (cfg->pgsize_bitmap & PAGE_SIZE)
|
|
|
|
granule = PAGE_SIZE;
|
|
|
|
else if (cfg->pgsize_bitmap & ~PAGE_MASK)
|
|
|
|
granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
|
|
|
|
else if (cfg->pgsize_bitmap & PAGE_MASK)
|
|
|
|
granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
|
|
|
|
else
|
|
|
|
granule = 0;
|
|
|
|
|
|
|
|
switch (granule) {
|
|
|
|
case SZ_4K:
|
2018-03-26 20:35:13 +08:00
|
|
|
page_sizes = (SZ_4K | SZ_2M | SZ_1G);
|
2014-11-15 01:18:23 +08:00
|
|
|
break;
|
|
|
|
case SZ_16K:
|
2018-03-26 20:35:13 +08:00
|
|
|
page_sizes = (SZ_16K | SZ_32M);
|
2014-11-15 01:18:23 +08:00
|
|
|
break;
|
|
|
|
case SZ_64K:
|
2018-03-26 20:35:13 +08:00
|
|
|
max_addr_bits = 52;
|
|
|
|
page_sizes = (SZ_64K | SZ_512M);
|
|
|
|
if (cfg->oas > 48)
|
|
|
|
page_sizes |= 1ULL << 42; /* 4TB */
|
2014-11-15 01:18:23 +08:00
|
|
|
break;
|
|
|
|
default:
|
2018-03-26 20:35:13 +08:00
|
|
|
page_sizes = 0;
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
2018-03-26 20:35:13 +08:00
|
|
|
|
|
|
|
cfg->pgsize_bitmap &= page_sizes;
|
|
|
|
cfg->ias = min(cfg->ias, max_addr_bits);
|
|
|
|
cfg->oas = min(cfg->oas, max_addr_bits);
|
2014-11-15 01:18:23 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct arm_lpae_io_pgtable *
|
|
|
|
arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
|
|
|
|
{
|
|
|
|
unsigned long va_bits, pgd_bits;
|
|
|
|
struct arm_lpae_io_pgtable *data;
|
|
|
|
|
|
|
|
arm_lpae_restrict_pgsizes(cfg);
|
|
|
|
|
|
|
|
if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
|
|
|
|
return NULL;
|
|
|
|
|
2015-09-18 00:42:16 +08:00
|
|
|
if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) {
|
|
|
|
dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-11-15 01:18:23 +08:00
|
|
|
data = kmalloc(sizeof(*data), GFP_KERNEL);
|
|
|
|
if (!data)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
data->pg_shift = __ffs(cfg->pgsize_bitmap);
|
|
|
|
data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte));
|
|
|
|
|
|
|
|
va_bits = cfg->ias - data->pg_shift;
|
|
|
|
data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
|
|
|
|
|
|
|
|
/* Calculate the actual size of our pgd (without concatenation) */
|
|
|
|
pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
|
|
|
|
data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
|
|
|
|
|
|
|
|
data->iop.ops = (struct io_pgtable_ops) {
|
|
|
|
.map = arm_lpae_map,
|
|
|
|
.unmap = arm_lpae_unmap,
|
|
|
|
.iova_to_phys = arm_lpae_iova_to_phys,
|
|
|
|
};
|
|
|
|
|
|
|
|
return data;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct io_pgtable *
|
|
|
|
arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
|
|
|
|
{
|
|
|
|
u64 reg;
|
2016-02-13 01:09:46 +08:00
|
|
|
struct arm_lpae_io_pgtable *data;
|
|
|
|
|
2018-09-21 00:10:24 +08:00
|
|
|
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | IO_PGTABLE_QUIRK_NO_DMA |
|
|
|
|
IO_PGTABLE_QUIRK_NON_STRICT))
|
2016-02-13 01:09:46 +08:00
|
|
|
return NULL;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2016-02-13 01:09:46 +08:00
|
|
|
data = arm_lpae_alloc_pgtable(cfg);
|
2014-11-15 01:18:23 +08:00
|
|
|
if (!data)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
/* TCR */
|
|
|
|
reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
|
|
|
|
(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
|
|
|
|
(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
|
|
|
|
|
2015-12-08 02:18:53 +08:00
|
|
|
switch (ARM_LPAE_GRANULE(data)) {
|
2014-11-15 01:18:23 +08:00
|
|
|
case SZ_4K:
|
|
|
|
reg |= ARM_LPAE_TCR_TG0_4K;
|
|
|
|
break;
|
|
|
|
case SZ_16K:
|
|
|
|
reg |= ARM_LPAE_TCR_TG0_16K;
|
|
|
|
break;
|
|
|
|
case SZ_64K:
|
|
|
|
reg |= ARM_LPAE_TCR_TG0_64K;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (cfg->oas) {
|
|
|
|
case 32:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 36:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 40:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 42:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 44:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 48:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
|
|
|
|
break;
|
2018-03-26 20:35:13 +08:00
|
|
|
case 52:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_IPS_SHIFT);
|
|
|
|
break;
|
2014-11-15 01:18:23 +08:00
|
|
|
default:
|
|
|
|
goto out_free_data;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
|
2015-03-18 18:22:18 +08:00
|
|
|
|
|
|
|
/* Disable speculative walks through TTBR1 */
|
|
|
|
reg |= ARM_LPAE_TCR_EPD1;
|
2014-11-15 01:18:23 +08:00
|
|
|
cfg->arm_lpae_s1_cfg.tcr = reg;
|
|
|
|
|
|
|
|
/* MAIRs */
|
|
|
|
reg = (ARM_LPAE_MAIR_ATTR_NC
|
|
|
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
|
|
|
|
(ARM_LPAE_MAIR_ATTR_WBRWA
|
|
|
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
|
|
|
|
(ARM_LPAE_MAIR_ATTR_DEVICE
|
|
|
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
|
|
|
|
|
|
|
|
cfg->arm_lpae_s1_cfg.mair[0] = reg;
|
|
|
|
cfg->arm_lpae_s1_cfg.mair[1] = 0;
|
|
|
|
|
|
|
|
/* Looking good; allocate a pgd */
|
2015-07-30 02:46:04 +08:00
|
|
|
data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
|
2014-11-15 01:18:23 +08:00
|
|
|
if (!data->pgd)
|
|
|
|
goto out_free_data;
|
|
|
|
|
2015-07-30 02:46:09 +08:00
|
|
|
/* Ensure the empty pgd is visible before any actual TTBR write */
|
|
|
|
wmb();
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
/* TTBRs */
|
|
|
|
cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);
|
|
|
|
cfg->arm_lpae_s1_cfg.ttbr[1] = 0;
|
|
|
|
return &data->iop;
|
|
|
|
|
|
|
|
out_free_data:
|
|
|
|
kfree(data);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct io_pgtable *
|
|
|
|
arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
|
|
|
|
{
|
|
|
|
u64 reg, sl;
|
2016-02-13 01:09:46 +08:00
|
|
|
struct arm_lpae_io_pgtable *data;
|
|
|
|
|
|
|
|
/* The NS quirk doesn't apply at stage 2 */
|
2018-09-21 00:10:24 +08:00
|
|
|
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NO_DMA |
|
|
|
|
IO_PGTABLE_QUIRK_NON_STRICT))
|
2016-02-13 01:09:46 +08:00
|
|
|
return NULL;
|
2014-11-15 01:18:23 +08:00
|
|
|
|
2016-02-13 01:09:46 +08:00
|
|
|
data = arm_lpae_alloc_pgtable(cfg);
|
2014-11-15 01:18:23 +08:00
|
|
|
if (!data)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Concatenate PGDs at level 1 if possible in order to reduce
|
|
|
|
* the depth of the stage-2 walk.
|
|
|
|
*/
|
|
|
|
if (data->levels == ARM_LPAE_MAX_LEVELS) {
|
|
|
|
unsigned long pgd_pages;
|
|
|
|
|
|
|
|
pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte));
|
|
|
|
if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
|
|
|
|
data->pgd_size = pgd_pages << data->pg_shift;
|
|
|
|
data->levels--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* VTCR */
|
|
|
|
reg = ARM_64_LPAE_S2_TCR_RES1 |
|
|
|
|
(ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
|
|
|
|
(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
|
|
|
|
(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
|
|
|
|
|
|
|
|
sl = ARM_LPAE_START_LVL(data);
|
|
|
|
|
2015-12-08 02:18:53 +08:00
|
|
|
switch (ARM_LPAE_GRANULE(data)) {
|
2014-11-15 01:18:23 +08:00
|
|
|
case SZ_4K:
|
|
|
|
reg |= ARM_LPAE_TCR_TG0_4K;
|
|
|
|
sl++; /* SL0 format is different for 4K granule size */
|
|
|
|
break;
|
|
|
|
case SZ_16K:
|
|
|
|
reg |= ARM_LPAE_TCR_TG0_16K;
|
|
|
|
break;
|
|
|
|
case SZ_64K:
|
|
|
|
reg |= ARM_LPAE_TCR_TG0_64K;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (cfg->oas) {
|
|
|
|
case 32:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 36:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 40:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 42:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 44:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT);
|
|
|
|
break;
|
|
|
|
case 48:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
|
|
|
|
break;
|
2018-03-26 20:35:13 +08:00
|
|
|
case 52:
|
|
|
|
reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_PS_SHIFT);
|
|
|
|
break;
|
2014-11-15 01:18:23 +08:00
|
|
|
default:
|
|
|
|
goto out_free_data;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
|
|
|
|
reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT;
|
|
|
|
cfg->arm_lpae_s2_cfg.vtcr = reg;
|
|
|
|
|
|
|
|
/* Allocate pgd pages */
|
2015-07-30 02:46:04 +08:00
|
|
|
data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
|
2014-11-15 01:18:23 +08:00
|
|
|
if (!data->pgd)
|
|
|
|
goto out_free_data;
|
|
|
|
|
2015-07-30 02:46:09 +08:00
|
|
|
/* Ensure the empty pgd is visible before any actual TTBR write */
|
|
|
|
wmb();
|
2014-11-15 01:18:23 +08:00
|
|
|
|
|
|
|
/* VTTBR */
|
|
|
|
cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
|
|
|
|
return &data->iop;
|
|
|
|
|
|
|
|
out_free_data:
|
|
|
|
kfree(data);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct io_pgtable *
|
|
|
|
arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
|
|
|
|
{
|
|
|
|
struct io_pgtable *iop;
|
|
|
|
|
|
|
|
if (cfg->ias > 32 || cfg->oas > 40)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
|
|
|
|
iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
|
|
|
|
if (iop) {
|
|
|
|
cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE;
|
|
|
|
cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff;
|
|
|
|
}
|
|
|
|
|
|
|
|
return iop;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct io_pgtable *
|
|
|
|
arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
|
|
|
|
{
|
|
|
|
struct io_pgtable *iop;
|
|
|
|
|
|
|
|
if (cfg->ias > 40 || cfg->oas > 40)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
|
|
|
|
iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
|
|
|
|
if (iop)
|
|
|
|
cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff;
|
|
|
|
|
|
|
|
return iop;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
|
|
|
|
.alloc = arm_64_lpae_alloc_pgtable_s1,
|
|
|
|
.free = arm_lpae_free_pgtable,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
|
|
|
|
.alloc = arm_64_lpae_alloc_pgtable_s2,
|
|
|
|
.free = arm_lpae_free_pgtable,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
|
|
|
|
.alloc = arm_32_lpae_alloc_pgtable_s1,
|
|
|
|
.free = arm_lpae_free_pgtable,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
|
|
|
|
.alloc = arm_32_lpae_alloc_pgtable_s2,
|
|
|
|
.free = arm_lpae_free_pgtable,
|
|
|
|
};
|
2014-11-18 07:31:12 +08:00
|
|
|
|
|
|
|
#ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
|
|
|
|
|
|
|
|
static struct io_pgtable_cfg *cfg_cookie;
|
|
|
|
|
|
|
|
static void dummy_tlb_flush_all(void *cookie)
|
|
|
|
{
|
|
|
|
WARN_ON(cookie != cfg_cookie);
|
|
|
|
}
|
|
|
|
|
2015-12-08 02:18:53 +08:00
|
|
|
static void dummy_tlb_add_flush(unsigned long iova, size_t size,
|
|
|
|
size_t granule, bool leaf, void *cookie)
|
2014-11-18 07:31:12 +08:00
|
|
|
{
|
|
|
|
WARN_ON(cookie != cfg_cookie);
|
|
|
|
WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dummy_tlb_sync(void *cookie)
|
|
|
|
{
|
|
|
|
WARN_ON(cookie != cfg_cookie);
|
|
|
|
}
|
|
|
|
|
2016-10-26 02:06:12 +08:00
|
|
|
static const struct iommu_gather_ops dummy_tlb_ops __initconst = {
|
2014-11-18 07:31:12 +08:00
|
|
|
.tlb_flush_all = dummy_tlb_flush_all,
|
|
|
|
.tlb_add_flush = dummy_tlb_add_flush,
|
|
|
|
.tlb_sync = dummy_tlb_sync,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
|
|
|
|
{
|
|
|
|
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
|
|
|
|
struct io_pgtable_cfg *cfg = &data->iop.cfg;
|
|
|
|
|
|
|
|
pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
|
|
|
|
cfg->pgsize_bitmap, cfg->ias);
|
|
|
|
pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n",
|
|
|
|
data->levels, data->pgd_size, data->pg_shift,
|
|
|
|
data->bits_per_level, data->pgd);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define __FAIL(ops, i) ({ \
|
|
|
|
WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
|
|
|
|
arm_lpae_dump_ops(ops); \
|
|
|
|
selftest_running = false; \
|
|
|
|
-EFAULT; \
|
|
|
|
})
|
|
|
|
|
|
|
|
static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
|
|
|
|
{
|
|
|
|
static const enum io_pgtable_fmt fmts[] = {
|
|
|
|
ARM_64_LPAE_S1,
|
|
|
|
ARM_64_LPAE_S2,
|
|
|
|
};
|
|
|
|
|
|
|
|
int i, j;
|
|
|
|
unsigned long iova;
|
|
|
|
size_t size;
|
|
|
|
struct io_pgtable_ops *ops;
|
|
|
|
|
|
|
|
selftest_running = true;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
|
|
|
|
cfg_cookie = cfg;
|
|
|
|
ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
|
|
|
|
if (!ops) {
|
|
|
|
pr_err("selftest: failed to allocate io pgtable ops\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initial sanity checks.
|
|
|
|
* Empty page tables shouldn't provide any translations.
|
|
|
|
*/
|
|
|
|
if (ops->iova_to_phys(ops, 42))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
if (ops->iova_to_phys(ops, SZ_1G + 42))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
if (ops->iova_to_phys(ops, SZ_2G + 42))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Distinct mappings of different granule sizes.
|
|
|
|
*/
|
|
|
|
iova = 0;
|
2016-09-21 13:41:31 +08:00
|
|
|
for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
|
2014-11-18 07:31:12 +08:00
|
|
|
size = 1UL << j;
|
|
|
|
|
|
|
|
if (ops->map(ops, iova, iova, size, IOMMU_READ |
|
|
|
|
IOMMU_WRITE |
|
|
|
|
IOMMU_NOEXEC |
|
|
|
|
IOMMU_CACHE))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
/* Overlapping mappings */
|
|
|
|
if (!ops->map(ops, iova, iova + size, size,
|
|
|
|
IOMMU_READ | IOMMU_NOEXEC))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
iova += SZ_1G;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Partial unmap */
|
|
|
|
size = 1UL << __ffs(cfg->pgsize_bitmap);
|
|
|
|
if (ops->unmap(ops, SZ_1G + size, size) != size)
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
/* Remap of partial unmap */
|
|
|
|
if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
/* Full unmap */
|
|
|
|
iova = 0;
|
2018-04-26 12:49:29 +08:00
|
|
|
for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
|
2014-11-18 07:31:12 +08:00
|
|
|
size = 1UL << j;
|
|
|
|
|
|
|
|
if (ops->unmap(ops, iova, size) != size)
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
if (ops->iova_to_phys(ops, iova + 42))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
/* Remap full block */
|
|
|
|
if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
|
|
|
|
return __FAIL(ops, i);
|
|
|
|
|
|
|
|
iova += SZ_1G;
|
|
|
|
}
|
|
|
|
|
|
|
|
free_io_pgtable_ops(ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
selftest_running = false;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init arm_lpae_do_selftests(void)
|
|
|
|
{
|
|
|
|
static const unsigned long pgsize[] = {
|
|
|
|
SZ_4K | SZ_2M | SZ_1G,
|
|
|
|
SZ_16K | SZ_32M,
|
|
|
|
SZ_64K | SZ_512M,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const unsigned int ias[] = {
|
|
|
|
32, 36, 40, 42, 44, 48,
|
|
|
|
};
|
|
|
|
|
|
|
|
int i, j, pass = 0, fail = 0;
|
|
|
|
struct io_pgtable_cfg cfg = {
|
|
|
|
.tlb = &dummy_tlb_ops,
|
|
|
|
.oas = 48,
|
2017-06-22 23:53:53 +08:00
|
|
|
.quirks = IO_PGTABLE_QUIRK_NO_DMA,
|
2014-11-18 07:31:12 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
|
|
|
|
for (j = 0; j < ARRAY_SIZE(ias); ++j) {
|
|
|
|
cfg.pgsize_bitmap = pgsize[i];
|
|
|
|
cfg.ias = ias[j];
|
|
|
|
pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
|
|
|
|
pgsize[i], ias[j]);
|
|
|
|
if (arm_lpae_run_tests(&cfg))
|
|
|
|
fail++;
|
|
|
|
else
|
|
|
|
pass++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
|
|
|
|
return fail ? -EFAULT : 0;
|
|
|
|
}
|
|
|
|
subsys_initcall(arm_lpae_do_selftests);
|
|
|
|
#endif
|