2005-04-17 06:20:36 +08:00
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/*
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* Intel Multiprocessor Specification 1.1 and 1.4
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* compliant MP-table parsing routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
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*
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* Fixes
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* Erich Boleyn : MP v1.4 and additional changes.
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* Alan Cox : Added EBDA scanning
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* Ingo Molnar : various cleanups and rewrites
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* Maciej W. Rozycki: Bits for default MP configurations
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* Paul Diefenbaugh: Added full ACPI support
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*/
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/config.h>
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#include <linux/bootmem.h>
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#include <linux/smp_lock.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/acpi.h>
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2005-06-23 15:08:18 +08:00
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#include <linux/module.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/smp.h>
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#include <asm/mtrr.h>
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#include <asm/mpspec.h>
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#include <asm/pgalloc.h>
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#include <asm/io_apic.h>
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#include <asm/proto.h>
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2005-06-01 05:39:26 +08:00
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#include <asm/acpi.h>
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2005-04-17 06:20:36 +08:00
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/* Have we found an MP table */
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int smp_found_config;
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unsigned int __initdata maxcpus = NR_CPUS;
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int acpi_found_madt;
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/*
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* Various Linux-internal data structures created from the
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* MP-table.
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*/
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int apic_version [MAX_APICS];
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unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
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int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
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2005-06-23 15:08:18 +08:00
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unsigned char pci_bus_to_node [256];
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EXPORT_SYMBOL(pci_bus_to_node);
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2005-04-17 06:20:36 +08:00
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static int mp_current_pci_id = 0;
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/* I/O APIC entries */
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struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
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/* # of MP IRQ source entries */
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struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* MP IRQ source entries */
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int mp_irq_entries;
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int nr_ioapics;
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int pic_mode;
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unsigned long mp_lapic_addr = 0;
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/* Processor that is doing the boot up */
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unsigned int boot_cpu_id = -1U;
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/* Internal processor count */
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static unsigned int num_processors = 0;
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/* Bitmask of physically existing CPUs */
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physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
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/* ACPI MADT entry parsing functions */
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#ifdef CONFIG_ACPI_BOOT
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extern struct acpi_boot_flags acpi_boot;
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#ifdef CONFIG_X86_LOCAL_APIC
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extern int acpi_parse_lapic (acpi_table_entry_header *header);
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extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
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extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
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#endif /*CONFIG_X86_LOCAL_APIC*/
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#ifdef CONFIG_X86_IO_APIC
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extern int acpi_parse_ioapic (acpi_table_entry_header *header);
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#endif /*CONFIG_X86_IO_APIC*/
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#endif /*CONFIG_ACPI_BOOT*/
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u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
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/*
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* Intel MP BIOS table parsing routines:
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*/
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/*
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* Checksum an MP configuration block.
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*/
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static int __init mpf_checksum(unsigned char *mp, int len)
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{
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int sum = 0;
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while (len--)
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sum += *mp++;
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return sum & 0xFF;
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}
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static void __init MP_processor_info (struct mpc_config_processor *m)
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{
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2005-07-29 12:15:27 +08:00
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int ver, cpu;
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2005-05-17 12:53:35 +08:00
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static int found_bsp=0;
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2005-04-17 06:20:36 +08:00
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if (!(m->mpc_cpuflag & CPU_ENABLED))
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return;
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printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
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m->mpc_apicid,
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(m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
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(m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
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m->mpc_apicver);
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if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
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Dprintk(" Bootup CPU\n");
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boot_cpu_id = m->mpc_apicid;
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}
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if (num_processors >= NR_CPUS) {
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printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
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" Processor ignored.\n", NR_CPUS);
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return;
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}
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2005-07-29 12:15:27 +08:00
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cpu = num_processors++;
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2005-04-17 06:20:36 +08:00
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if (m->mpc_apicid > MAX_APICS) {
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printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
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m->mpc_apicid, MAX_APICS);
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return;
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}
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ver = m->mpc_apicver;
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physid_set(m->mpc_apicid, phys_cpu_present_map);
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/*
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* Validate version
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*/
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if (ver == 0x0) {
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printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
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ver = 0x10;
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}
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apic_version[m->mpc_apicid] = ver;
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2005-05-17 12:53:35 +08:00
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if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
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/*
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* bios_cpu_apicid is required to have processors listed
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* in same order as logical cpu numbers. Hence the first
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* entry is BSP, and so on.
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*/
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2005-07-29 12:15:27 +08:00
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cpu = 0;
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2005-05-17 12:53:35 +08:00
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bios_cpu_apicid[0] = m->mpc_apicid;
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x86_cpu_to_apicid[0] = m->mpc_apicid;
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found_bsp = 1;
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2005-07-29 12:15:27 +08:00
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} else
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cpu = num_processors - found_bsp;
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bios_cpu_apicid[cpu] = m->mpc_apicid;
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x86_cpu_to_apicid[cpu] = m->mpc_apicid;
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cpu_set(cpu, cpu_possible_map);
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cpu_set(cpu, cpu_present_map);
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2005-04-17 06:20:36 +08:00
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}
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static void __init MP_bus_info (struct mpc_config_bus *m)
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{
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char str[7];
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memcpy(str, m->mpc_bustype, 6);
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str[6] = 0;
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Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
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if (strncmp(str, "ISA", 3) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
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} else if (strncmp(str, "EISA", 4) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
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} else if (strncmp(str, "PCI", 3) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
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mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
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mp_current_pci_id++;
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} else if (strncmp(str, "MCA", 3) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
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} else {
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printk(KERN_ERR "Unknown bustype %s\n", str);
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}
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}
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static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
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{
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if (!(m->mpc_flags & MPC_APIC_USABLE))
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return;
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printk("I/O APIC #%d Version %d at 0x%X.\n",
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m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
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if (nr_ioapics >= MAX_IO_APICS) {
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printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
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MAX_IO_APICS, nr_ioapics);
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panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
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}
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if (!m->mpc_apicaddr) {
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printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
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" found in MP table, skipping!\n");
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return;
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}
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mp_ioapics[nr_ioapics] = *m;
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nr_ioapics++;
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}
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static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
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{
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mp_irqs [mp_irq_entries] = *m;
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Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC INT %02x\n",
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
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m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
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if (++mp_irq_entries == MAX_IRQ_SOURCES)
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panic("Max # of irq sources exceeded!!\n");
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}
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static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
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{
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Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC LINT %02x\n",
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
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m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
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/*
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* Well it seems all SMP boards in existence
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* use ExtINT/LVT1 == LINT0 and
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* NMI/LVT2 == LINT1 - the following check
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* will show us if this assumptions is false.
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* Until then we do not have to add baggage.
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*/
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if ((m->mpc_irqtype == mp_ExtINT) &&
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(m->mpc_destapiclint != 0))
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BUG();
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if ((m->mpc_irqtype == mp_NMI) &&
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(m->mpc_destapiclint != 1))
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BUG();
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}
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/*
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* Read/parse the MPC
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*/
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static int __init smp_read_mpc(struct mp_config_table *mpc)
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{
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char str[16];
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int count=sizeof(*mpc);
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unsigned char *mpt=((unsigned char *)mpc)+count;
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if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
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printk("SMP mptable: bad signature [%c%c%c%c]!\n",
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mpc->mpc_signature[0],
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mpc->mpc_signature[1],
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mpc->mpc_signature[2],
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mpc->mpc_signature[3]);
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return 0;
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}
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if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
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printk("SMP mptable: checksum error!\n");
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return 0;
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}
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if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
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printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
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mpc->mpc_spec);
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return 0;
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}
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if (!mpc->mpc_lapic) {
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printk(KERN_ERR "SMP mptable: null local APIC address!\n");
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return 0;
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}
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memcpy(str,mpc->mpc_oem,8);
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str[8]=0;
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printk(KERN_INFO "OEM ID: %s ",str);
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memcpy(str,mpc->mpc_productid,12);
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str[12]=0;
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printk(KERN_INFO "Product ID: %s ",str);
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printk(KERN_INFO "APIC at: 0x%X\n",mpc->mpc_lapic);
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/* save the local APIC address, it might be non-default */
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if (!acpi_lapic)
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mp_lapic_addr = mpc->mpc_lapic;
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/*
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* Now process the configuration blocks.
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*/
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while (count < mpc->mpc_length) {
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switch(*mpt) {
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case MP_PROCESSOR:
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{
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struct mpc_config_processor *m=
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(struct mpc_config_processor *)mpt;
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if (!acpi_lapic)
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MP_processor_info(m);
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mpt += sizeof(*m);
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count += sizeof(*m);
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break;
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}
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case MP_BUS:
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{
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struct mpc_config_bus *m=
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(struct mpc_config_bus *)mpt;
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MP_bus_info(m);
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mpt += sizeof(*m);
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count += sizeof(*m);
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break;
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}
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case MP_IOAPIC:
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{
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struct mpc_config_ioapic *m=
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(struct mpc_config_ioapic *)mpt;
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MP_ioapic_info(m);
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mpt+=sizeof(*m);
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count+=sizeof(*m);
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break;
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}
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case MP_INTSRC:
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{
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struct mpc_config_intsrc *m=
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(struct mpc_config_intsrc *)mpt;
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MP_intsrc_info(m);
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mpt+=sizeof(*m);
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count+=sizeof(*m);
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break;
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}
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case MP_LINTSRC:
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{
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struct mpc_config_lintsrc *m=
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(struct mpc_config_lintsrc *)mpt;
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|
|
|
MP_lintsrc_info(m);
|
|
|
|
mpt+=sizeof(*m);
|
|
|
|
count+=sizeof(*m);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
clustered_apic_check();
|
|
|
|
if (!num_processors)
|
|
|
|
printk(KERN_ERR "SMP mptable: no processors registered!\n");
|
|
|
|
return num_processors;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init ELCR_trigger(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned int port;
|
|
|
|
|
|
|
|
port = 0x4d0 + (irq >> 3);
|
|
|
|
return (inb(port) >> (irq & 7)) & 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init construct_default_ioirq_mptable(int mpc_default_type)
|
|
|
|
{
|
|
|
|
struct mpc_config_intsrc intsrc;
|
|
|
|
int i;
|
|
|
|
int ELCR_fallback = 0;
|
|
|
|
|
|
|
|
intsrc.mpc_type = MP_INTSRC;
|
|
|
|
intsrc.mpc_irqflag = 0; /* conforming */
|
|
|
|
intsrc.mpc_srcbus = 0;
|
|
|
|
intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
|
|
|
|
|
|
|
|
intsrc.mpc_irqtype = mp_INT;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If true, we have an ISA/PCI system with no IRQ entries
|
|
|
|
* in the MP table. To prevent the PCI interrupts from being set up
|
|
|
|
* incorrectly, we try to use the ELCR. The sanity check to see if
|
|
|
|
* there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
|
|
|
|
* never be level sensitive, so we simply see if the ELCR agrees.
|
|
|
|
* If it does, we assume it's valid.
|
|
|
|
*/
|
|
|
|
if (mpc_default_type == 5) {
|
|
|
|
printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
|
|
|
|
|
|
|
|
if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
|
|
|
|
printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
|
|
|
|
else {
|
|
|
|
printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
|
|
|
|
ELCR_fallback = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
switch (mpc_default_type) {
|
|
|
|
case 2:
|
|
|
|
if (i == 0 || i == 13)
|
|
|
|
continue; /* IRQ0 & IRQ13 not connected */
|
|
|
|
/* fall through */
|
|
|
|
default:
|
|
|
|
if (i == 2)
|
|
|
|
continue; /* IRQ2 is never connected */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ELCR_fallback) {
|
|
|
|
/*
|
|
|
|
* If the ELCR indicates a level-sensitive interrupt, we
|
|
|
|
* copy that information over to the MP table in the
|
|
|
|
* irqflag field (level sensitive, active high polarity).
|
|
|
|
*/
|
|
|
|
if (ELCR_trigger(i))
|
|
|
|
intsrc.mpc_irqflag = 13;
|
|
|
|
else
|
|
|
|
intsrc.mpc_irqflag = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
intsrc.mpc_srcbusirq = i;
|
|
|
|
intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
|
|
|
|
MP_intsrc_info(&intsrc);
|
|
|
|
}
|
|
|
|
|
|
|
|
intsrc.mpc_irqtype = mp_ExtINT;
|
|
|
|
intsrc.mpc_srcbusirq = 0;
|
|
|
|
intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
|
|
|
|
MP_intsrc_info(&intsrc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void __init construct_default_ISA_mptable(int mpc_default_type)
|
|
|
|
{
|
|
|
|
struct mpc_config_processor processor;
|
|
|
|
struct mpc_config_bus bus;
|
|
|
|
struct mpc_config_ioapic ioapic;
|
|
|
|
struct mpc_config_lintsrc lintsrc;
|
|
|
|
int linttypes[2] = { mp_ExtINT, mp_NMI };
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* local APIC has default address
|
|
|
|
*/
|
|
|
|
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 2 CPUs, numbered 0 & 1.
|
|
|
|
*/
|
|
|
|
processor.mpc_type = MP_PROCESSOR;
|
|
|
|
/* Either an integrated APIC or a discrete 82489DX. */
|
|
|
|
processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
|
|
|
processor.mpc_cpuflag = CPU_ENABLED;
|
|
|
|
processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
|
|
|
|
(boot_cpu_data.x86_model << 4) |
|
|
|
|
boot_cpu_data.x86_mask;
|
|
|
|
processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
|
|
|
|
processor.mpc_reserved[0] = 0;
|
|
|
|
processor.mpc_reserved[1] = 0;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
processor.mpc_apicid = i;
|
|
|
|
MP_processor_info(&processor);
|
|
|
|
}
|
|
|
|
|
|
|
|
bus.mpc_type = MP_BUS;
|
|
|
|
bus.mpc_busid = 0;
|
|
|
|
switch (mpc_default_type) {
|
|
|
|
default:
|
|
|
|
printk(KERN_ERR "???\nUnknown standard configuration %d\n",
|
|
|
|
mpc_default_type);
|
|
|
|
/* fall through */
|
|
|
|
case 1:
|
|
|
|
case 5:
|
|
|
|
memcpy(bus.mpc_bustype, "ISA ", 6);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
case 6:
|
|
|
|
case 3:
|
|
|
|
memcpy(bus.mpc_bustype, "EISA ", 6);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
case 7:
|
|
|
|
memcpy(bus.mpc_bustype, "MCA ", 6);
|
|
|
|
}
|
|
|
|
MP_bus_info(&bus);
|
|
|
|
if (mpc_default_type > 4) {
|
|
|
|
bus.mpc_busid = 1;
|
|
|
|
memcpy(bus.mpc_bustype, "PCI ", 6);
|
|
|
|
MP_bus_info(&bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
ioapic.mpc_type = MP_IOAPIC;
|
|
|
|
ioapic.mpc_apicid = 2;
|
|
|
|
ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
|
|
|
ioapic.mpc_flags = MPC_APIC_USABLE;
|
|
|
|
ioapic.mpc_apicaddr = 0xFEC00000;
|
|
|
|
MP_ioapic_info(&ioapic);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We set up most of the low 16 IO-APIC pins according to MPS rules.
|
|
|
|
*/
|
|
|
|
construct_default_ioirq_mptable(mpc_default_type);
|
|
|
|
|
|
|
|
lintsrc.mpc_type = MP_LINTSRC;
|
|
|
|
lintsrc.mpc_irqflag = 0; /* conforming */
|
|
|
|
lintsrc.mpc_srcbusid = 0;
|
|
|
|
lintsrc.mpc_srcbusirq = 0;
|
|
|
|
lintsrc.mpc_destapic = MP_APIC_ALL;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
lintsrc.mpc_irqtype = linttypes[i];
|
|
|
|
lintsrc.mpc_destapiclint = i;
|
|
|
|
MP_lintsrc_info(&lintsrc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct intel_mp_floating *mpf_found;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Scan the memory blocks for an SMP configuration block.
|
|
|
|
*/
|
|
|
|
void __init get_smp_config (void)
|
|
|
|
{
|
|
|
|
struct intel_mp_floating *mpf = mpf_found;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ACPI may be used to obtain the entire SMP configuration or just to
|
|
|
|
* enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
|
|
|
|
* ACPI supports both logical (e.g. Hyper-Threading) and physical
|
|
|
|
* processors, where MPS only supports physical.
|
|
|
|
*/
|
|
|
|
if (acpi_lapic && acpi_ioapic) {
|
|
|
|
printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
else if (acpi_lapic)
|
|
|
|
printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
|
|
|
|
|
|
|
|
printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
|
|
|
|
if (mpf->mpf_feature2 & (1<<7)) {
|
|
|
|
printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
|
|
|
|
pic_mode = 1;
|
|
|
|
} else {
|
|
|
|
printk(KERN_INFO " Virtual Wire compatibility mode.\n");
|
|
|
|
pic_mode = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now see if we need to read further.
|
|
|
|
*/
|
|
|
|
if (mpf->mpf_feature1 != 0) {
|
|
|
|
|
|
|
|
printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
|
|
|
|
construct_default_ISA_mptable(mpf->mpf_feature1);
|
|
|
|
|
|
|
|
} else if (mpf->mpf_physptr) {
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read the physical hardware table. Anything here will
|
|
|
|
* override the defaults.
|
|
|
|
*/
|
|
|
|
if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
|
|
|
|
smp_found_config = 0;
|
|
|
|
printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
|
|
|
|
printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* If there are no explicit MP IRQ entries, then we are
|
|
|
|
* broken. We set up most of the low 16 IO-APIC pins to
|
|
|
|
* ISA defaults and hope it will work.
|
|
|
|
*/
|
|
|
|
if (!mp_irq_entries) {
|
|
|
|
struct mpc_config_bus bus;
|
|
|
|
|
|
|
|
printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
|
|
|
|
|
|
|
|
bus.mpc_type = MP_BUS;
|
|
|
|
bus.mpc_busid = 0;
|
|
|
|
memcpy(bus.mpc_bustype, "ISA ", 6);
|
|
|
|
MP_bus_info(&bus);
|
|
|
|
|
|
|
|
construct_default_ioirq_mptable(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
} else
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
printk(KERN_INFO "Processors: %d\n", num_processors);
|
|
|
|
/*
|
|
|
|
* Only use the first configuration found.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init smp_scan_config (unsigned long base, unsigned long length)
|
|
|
|
{
|
|
|
|
extern void __bad_mpf_size(void);
|
|
|
|
unsigned int *bp = phys_to_virt(base);
|
|
|
|
struct intel_mp_floating *mpf;
|
|
|
|
|
|
|
|
Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
|
|
|
|
if (sizeof(*mpf) != 16)
|
|
|
|
__bad_mpf_size();
|
|
|
|
|
|
|
|
while (length > 0) {
|
|
|
|
mpf = (struct intel_mp_floating *)bp;
|
|
|
|
if ((*bp == SMP_MAGIC_IDENT) &&
|
|
|
|
(mpf->mpf_length == 1) &&
|
|
|
|
!mpf_checksum((unsigned char *)bp, 16) &&
|
|
|
|
((mpf->mpf_specification == 1)
|
|
|
|
|| (mpf->mpf_specification == 4)) ) {
|
|
|
|
|
|
|
|
smp_found_config = 1;
|
|
|
|
reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
|
|
|
|
if (mpf->mpf_physptr)
|
|
|
|
reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
|
|
|
|
mpf_found = mpf;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
bp += 4;
|
|
|
|
length -= 16;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init find_intel_smp (void)
|
|
|
|
{
|
|
|
|
unsigned int address;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: Linux assumes you have 640K of base ram..
|
|
|
|
* this continues the error...
|
|
|
|
*
|
|
|
|
* 1) Scan the bottom 1K for a signature
|
|
|
|
* 2) Scan the top 1K of base RAM
|
|
|
|
* 3) Scan the 64K of bios
|
|
|
|
*/
|
|
|
|
if (smp_scan_config(0x0,0x400) ||
|
|
|
|
smp_scan_config(639*0x400,0x400) ||
|
|
|
|
smp_scan_config(0xF0000,0x10000))
|
|
|
|
return;
|
|
|
|
/*
|
|
|
|
* If it is an SMP machine we should know now, unless the
|
|
|
|
* configuration is in an EISA/MCA bus machine with an
|
|
|
|
* extended bios data area.
|
|
|
|
*
|
|
|
|
* there is a real-mode segmented pointer pointing to the
|
|
|
|
* 4K EBDA area at 0x40E, calculate and scan it here.
|
|
|
|
*
|
|
|
|
* NOTE! There are Linux loaders that will corrupt the EBDA
|
|
|
|
* area, and as such this kind of SMP config may be less
|
|
|
|
* trustworthy, simply because the SMP table may have been
|
|
|
|
* stomped on during early boot. These loaders are buggy and
|
|
|
|
* should be fixed.
|
|
|
|
*/
|
|
|
|
|
|
|
|
address = *(unsigned short *)phys_to_virt(0x40E);
|
|
|
|
address <<= 4;
|
|
|
|
if (smp_scan_config(address, 0x1000))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* If we have come this far, we did not find an MP table */
|
|
|
|
printk(KERN_INFO "No mptable found.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* - Intel MP Configuration Table
|
|
|
|
*/
|
|
|
|
void __init find_smp_config (void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
|
|
|
find_intel_smp();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* --------------------------------------------------------------------------
|
|
|
|
ACPI-based MP Configuration
|
|
|
|
-------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
#ifdef CONFIG_ACPI_BOOT
|
|
|
|
|
|
|
|
void __init mp_register_lapic_address (
|
|
|
|
u64 address)
|
|
|
|
{
|
|
|
|
mp_lapic_addr = (unsigned long) address;
|
|
|
|
|
|
|
|
set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
|
|
|
|
|
|
|
|
if (boot_cpu_id == -1U)
|
|
|
|
boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
|
|
|
|
|
|
|
|
Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void __init mp_register_lapic (
|
|
|
|
u8 id,
|
|
|
|
u8 enabled)
|
|
|
|
{
|
|
|
|
struct mpc_config_processor processor;
|
|
|
|
int boot_cpu = 0;
|
|
|
|
|
|
|
|
if (id >= MAX_APICS) {
|
|
|
|
printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
|
|
|
|
id, MAX_APICS);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (id == boot_cpu_physical_apicid)
|
|
|
|
boot_cpu = 1;
|
|
|
|
|
|
|
|
processor.mpc_type = MP_PROCESSOR;
|
|
|
|
processor.mpc_apicid = id;
|
|
|
|
processor.mpc_apicver = 0x10; /* TBD: lapic version */
|
|
|
|
processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
|
|
|
|
processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
|
|
|
|
processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
|
|
|
|
(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
|
|
|
|
processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
|
|
|
|
processor.mpc_reserved[0] = 0;
|
|
|
|
processor.mpc_reserved[1] = 0;
|
|
|
|
|
|
|
|
MP_processor_info(&processor);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
|
|
|
|
|
|
#define MP_ISA_BUS 0
|
|
|
|
#define MP_MAX_IOAPIC_PIN 127
|
|
|
|
|
|
|
|
static struct mp_ioapic_routing {
|
|
|
|
int apic_id;
|
|
|
|
int gsi_start;
|
|
|
|
int gsi_end;
|
|
|
|
u32 pin_programmed[4];
|
|
|
|
} mp_ioapic_routing[MAX_IO_APICS];
|
|
|
|
|
|
|
|
|
|
|
|
static int mp_find_ioapic (
|
|
|
|
int gsi)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
/* Find the IOAPIC that manages this GSI. */
|
|
|
|
for (i = 0; i < nr_ioapics; i++) {
|
|
|
|
if ((gsi >= mp_ioapic_routing[i].gsi_start)
|
|
|
|
&& (gsi <= mp_ioapic_routing[i].gsi_end))
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void __init mp_register_ioapic (
|
|
|
|
u8 id,
|
|
|
|
u32 address,
|
|
|
|
u32 gsi_base)
|
|
|
|
{
|
|
|
|
int idx = 0;
|
|
|
|
|
|
|
|
if (nr_ioapics >= MAX_IO_APICS) {
|
|
|
|
printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
|
|
|
|
"(found %d)\n", MAX_IO_APICS, nr_ioapics);
|
|
|
|
panic("Recompile kernel with bigger MAX_IO_APICS!\n");
|
|
|
|
}
|
|
|
|
if (!address) {
|
|
|
|
printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
|
|
|
|
" found in MADT table, skipping!\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
idx = nr_ioapics++;
|
|
|
|
|
|
|
|
mp_ioapics[idx].mpc_type = MP_IOAPIC;
|
|
|
|
mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
|
|
|
|
mp_ioapics[idx].mpc_apicaddr = address;
|
|
|
|
|
|
|
|
set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
|
2005-05-17 12:53:27 +08:00
|
|
|
mp_ioapics[idx].mpc_apicid = id;
|
2005-04-17 06:20:36 +08:00
|
|
|
mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Build basic IRQ lookup table to facilitate gsi->io_apic lookups
|
|
|
|
* and to prevent reprogramming of IOAPIC pins (PCI IRQs).
|
|
|
|
*/
|
|
|
|
mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
|
|
|
|
mp_ioapic_routing[idx].gsi_start = gsi_base;
|
|
|
|
mp_ioapic_routing[idx].gsi_end = gsi_base +
|
|
|
|
io_apic_get_redir_entries(idx);
|
|
|
|
|
|
|
|
printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
|
|
|
|
"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
|
|
|
|
mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
|
|
|
|
mp_ioapic_routing[idx].gsi_start,
|
|
|
|
mp_ioapic_routing[idx].gsi_end);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void __init mp_override_legacy_irq (
|
|
|
|
u8 bus_irq,
|
|
|
|
u8 polarity,
|
|
|
|
u8 trigger,
|
|
|
|
u32 gsi)
|
|
|
|
{
|
|
|
|
struct mpc_config_intsrc intsrc;
|
|
|
|
int ioapic = -1;
|
|
|
|
int pin = -1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Convert 'gsi' to 'ioapic.pin'.
|
|
|
|
*/
|
|
|
|
ioapic = mp_find_ioapic(gsi);
|
|
|
|
if (ioapic < 0)
|
|
|
|
return;
|
|
|
|
pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TBD: This check is for faulty timer entries, where the override
|
|
|
|
* erroneously sets the trigger to level, resulting in a HUGE
|
|
|
|
* increase of timer interrupts!
|
|
|
|
*/
|
|
|
|
if ((bus_irq == 0) && (trigger == 3))
|
|
|
|
trigger = 1;
|
|
|
|
|
|
|
|
intsrc.mpc_type = MP_INTSRC;
|
|
|
|
intsrc.mpc_irqtype = mp_INT;
|
|
|
|
intsrc.mpc_irqflag = (trigger << 2) | polarity;
|
|
|
|
intsrc.mpc_srcbus = MP_ISA_BUS;
|
|
|
|
intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
|
|
|
|
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
|
|
|
|
intsrc.mpc_dstirq = pin; /* INTIN# */
|
|
|
|
|
|
|
|
Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
|
|
|
|
intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
|
|
|
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
|
|
|
intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
|
|
|
|
|
|
|
|
mp_irqs[mp_irq_entries] = intsrc;
|
|
|
|
if (++mp_irq_entries == MAX_IRQ_SOURCES)
|
|
|
|
panic("Max # of irq sources exceeded!\n");
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void __init mp_config_acpi_legacy_irqs (void)
|
|
|
|
{
|
|
|
|
struct mpc_config_intsrc intsrc;
|
|
|
|
int i = 0;
|
|
|
|
int ioapic = -1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fabricate the legacy ISA bus (bus #31).
|
|
|
|
*/
|
|
|
|
mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
|
|
|
|
Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Locate the IOAPIC that manages the ISA IRQs (0-15).
|
|
|
|
*/
|
|
|
|
ioapic = mp_find_ioapic(0);
|
|
|
|
if (ioapic < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intsrc.mpc_type = MP_INTSRC;
|
|
|
|
intsrc.mpc_irqflag = 0; /* Conforming */
|
|
|
|
intsrc.mpc_srcbus = MP_ISA_BUS;
|
|
|
|
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Use the default configuration for the IRQs 0-15. Unless
|
|
|
|
* overridden by (MADT) interrupt source override entries.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
for (idx = 0; idx < mp_irq_entries; idx++) {
|
|
|
|
struct mpc_config_intsrc *irq = mp_irqs + idx;
|
|
|
|
|
|
|
|
/* Do we already have a mapping for this ISA IRQ? */
|
|
|
|
if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Do we already have a mapping for this IOAPIC pin */
|
|
|
|
if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
|
|
|
|
(irq->mpc_dstirq == i))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (idx != mp_irq_entries) {
|
|
|
|
printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
|
|
|
|
continue; /* IRQ already used */
|
|
|
|
}
|
|
|
|
|
|
|
|
intsrc.mpc_irqtype = mp_INT;
|
|
|
|
intsrc.mpc_srcbusirq = i; /* Identity mapped */
|
|
|
|
intsrc.mpc_dstirq = i;
|
|
|
|
|
|
|
|
Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
|
|
|
|
"%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
|
|
|
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
|
|
|
intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
|
|
|
|
intsrc.mpc_dstirq);
|
|
|
|
|
|
|
|
mp_irqs[mp_irq_entries] = intsrc;
|
|
|
|
if (++mp_irq_entries == MAX_IRQ_SOURCES)
|
|
|
|
panic("Max # of irq sources exceeded!\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
[PATCH] x86_64: avoid wasting IRQs
I suggest to change the way IRQs are handed out to PCI devices.
Currently, each I/O APIC pin gets associated with an IRQ, no matter if the
pin is used or not. It is expected that each pin can potentually be
engaged by a device inserted into the corresponding PCI slot. However,
this imposes severe limitation on systems that have designs that employ
many I/O APICs, only utilizing couple lines of each, such as P64H2 chipset.
It is used in ES7000, and currently, there is no way to boot the system
with more that 9 I/O APICs.
The simple change below allows to boot a system with say 64 (or more) I/O
APICs, each providing 1 slot, which otherwise impossible because of the IRQ
gaps created for unused lines on each I/O APIC. It does not resolve the
problem with number of devices that exceeds number of possible IRQs, but
eases up a tension for IRQs on any large system with potentually large
number of devices.
I only implemented this for the ACPI boot, since if the system is this big
and using newer chipsets it is probably (better be!) an ACPI based system
:). The change is completely "mechanical" and does not alter any internal
structures or interrupt model/implementation. The patch works for both
i386 and x86_64 archs. It works with MSIs just fine, and should not
intervene with implementations like shared vectors, when they get worked
out and incorporated.
To illustrate, below is the interrupt distribution for 2-cell ES7000 with
20 I/O APICs, and an Ethernet card in the last slot, which should be eth1
and which was not configured because its IRQ exceeded allowable number (it
actially turned out huge - 480!):
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 65716 30012 30007 30002 30009 30010 30010 30010 IO-APIC-edge timer
4: 373 0 725 280 0 0 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 3 0 0 0 0 0 0 IO-APIC-edge ide0
16: 108 13 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
18: 0 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb3
19: 15 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
96: 4240 397 18 0 0 0 0 0 IO-APIC-level aic7xxx
97: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx
192: 847 0 0 0 0 0 0 0 IO-APIC-level eth0
NMI: 0 0 0 0 0 0 0 0
LOC: 273423 274528 272829 274228 274092 273761 273827 273694
ERR: 7
MIS: 0
Even though the system doesn't have that many devices, some don't get
enabled only because of IRQ numbering model.
This is the IRQ picture after the patch was applied:
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 44169 10004 10004 10001 10004 10003 10004 6135 IO-APIC-edge timer
4: 345 0 0 0 0 244 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 0 3 0 0 0 0 0 IO-APIC-edge ide0
17: 4425 0 9 0 0 0 0 0 IO-APIC-level aic7xxx
18: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx, uhci_hcd:usb3
21: 231 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
22: 26 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
24: 348 0 0 0 0 0 0 0 IO-APIC-level eth0
25: 6 192 0 0 0 0 0 0 IO-APIC-level eth1
NMI: 0 0 0 0 0 0 0 0
LOC: 107981 107636 108899 108698 108489 108326 108331 108254
ERR: 7
MIS: 0
Not only we see the card in the last I/O APIC, but we are not even close to
using up available IRQs, since we didn't waste any.
Signed-off-by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
Acked-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 15:08:41 +08:00
|
|
|
#define MAX_GSI_NUM 4096
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
int mp_register_gsi(u32 gsi, int edge_level, int active_high_low)
|
|
|
|
{
|
|
|
|
int ioapic = -1;
|
|
|
|
int ioapic_pin = 0;
|
|
|
|
int idx, bit = 0;
|
[PATCH] x86_64: avoid wasting IRQs
I suggest to change the way IRQs are handed out to PCI devices.
Currently, each I/O APIC pin gets associated with an IRQ, no matter if the
pin is used or not. It is expected that each pin can potentually be
engaged by a device inserted into the corresponding PCI slot. However,
this imposes severe limitation on systems that have designs that employ
many I/O APICs, only utilizing couple lines of each, such as P64H2 chipset.
It is used in ES7000, and currently, there is no way to boot the system
with more that 9 I/O APICs.
The simple change below allows to boot a system with say 64 (or more) I/O
APICs, each providing 1 slot, which otherwise impossible because of the IRQ
gaps created for unused lines on each I/O APIC. It does not resolve the
problem with number of devices that exceeds number of possible IRQs, but
eases up a tension for IRQs on any large system with potentually large
number of devices.
I only implemented this for the ACPI boot, since if the system is this big
and using newer chipsets it is probably (better be!) an ACPI based system
:). The change is completely "mechanical" and does not alter any internal
structures or interrupt model/implementation. The patch works for both
i386 and x86_64 archs. It works with MSIs just fine, and should not
intervene with implementations like shared vectors, when they get worked
out and incorporated.
To illustrate, below is the interrupt distribution for 2-cell ES7000 with
20 I/O APICs, and an Ethernet card in the last slot, which should be eth1
and which was not configured because its IRQ exceeded allowable number (it
actially turned out huge - 480!):
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 65716 30012 30007 30002 30009 30010 30010 30010 IO-APIC-edge timer
4: 373 0 725 280 0 0 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 3 0 0 0 0 0 0 IO-APIC-edge ide0
16: 108 13 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
18: 0 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb3
19: 15 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
96: 4240 397 18 0 0 0 0 0 IO-APIC-level aic7xxx
97: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx
192: 847 0 0 0 0 0 0 0 IO-APIC-level eth0
NMI: 0 0 0 0 0 0 0 0
LOC: 273423 274528 272829 274228 274092 273761 273827 273694
ERR: 7
MIS: 0
Even though the system doesn't have that many devices, some don't get
enabled only because of IRQ numbering model.
This is the IRQ picture after the patch was applied:
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 44169 10004 10004 10001 10004 10003 10004 6135 IO-APIC-edge timer
4: 345 0 0 0 0 244 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 0 3 0 0 0 0 0 IO-APIC-edge ide0
17: 4425 0 9 0 0 0 0 0 IO-APIC-level aic7xxx
18: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx, uhci_hcd:usb3
21: 231 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
22: 26 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
24: 348 0 0 0 0 0 0 0 IO-APIC-level eth0
25: 6 192 0 0 0 0 0 0 IO-APIC-level eth1
NMI: 0 0 0 0 0 0 0 0
LOC: 107981 107636 108899 108698 108489 108326 108331 108254
ERR: 7
MIS: 0
Not only we see the card in the last I/O APIC, but we are not even close to
using up available IRQs, since we didn't waste any.
Signed-off-by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
Acked-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 15:08:41 +08:00
|
|
|
static int pci_irq = 16;
|
|
|
|
/*
|
|
|
|
* Mapping between Global System Interrupts, which
|
|
|
|
* represent all possible interrupts, to the IRQs
|
|
|
|
* assigned to actual devices.
|
|
|
|
*/
|
|
|
|
static int gsi_to_irq[MAX_GSI_NUM];
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
|
|
|
|
return gsi;
|
|
|
|
|
|
|
|
#ifdef CONFIG_ACPI_BUS
|
|
|
|
/* Don't set up the ACPI SCI because it's already set up */
|
|
|
|
if (acpi_fadt.sci_int == gsi)
|
|
|
|
return gsi;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
ioapic = mp_find_ioapic(gsi);
|
|
|
|
if (ioapic < 0) {
|
|
|
|
printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
|
|
|
|
return gsi;
|
|
|
|
}
|
|
|
|
|
|
|
|
ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Avoid pin reprogramming. PRTs typically include entries
|
|
|
|
* with redundant pin->gsi mappings (but unique PCI devices);
|
|
|
|
* we only program the IOAPIC on the first.
|
|
|
|
*/
|
|
|
|
bit = ioapic_pin % 32;
|
|
|
|
idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
|
|
|
|
if (idx > 3) {
|
|
|
|
printk(KERN_ERR "Invalid reference to IOAPIC pin "
|
|
|
|
"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
|
|
|
|
ioapic_pin);
|
|
|
|
return gsi;
|
|
|
|
}
|
|
|
|
if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
|
|
|
|
Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
|
|
|
|
mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
|
[PATCH] x86_64: avoid wasting IRQs
I suggest to change the way IRQs are handed out to PCI devices.
Currently, each I/O APIC pin gets associated with an IRQ, no matter if the
pin is used or not. It is expected that each pin can potentually be
engaged by a device inserted into the corresponding PCI slot. However,
this imposes severe limitation on systems that have designs that employ
many I/O APICs, only utilizing couple lines of each, such as P64H2 chipset.
It is used in ES7000, and currently, there is no way to boot the system
with more that 9 I/O APICs.
The simple change below allows to boot a system with say 64 (or more) I/O
APICs, each providing 1 slot, which otherwise impossible because of the IRQ
gaps created for unused lines on each I/O APIC. It does not resolve the
problem with number of devices that exceeds number of possible IRQs, but
eases up a tension for IRQs on any large system with potentually large
number of devices.
I only implemented this for the ACPI boot, since if the system is this big
and using newer chipsets it is probably (better be!) an ACPI based system
:). The change is completely "mechanical" and does not alter any internal
structures or interrupt model/implementation. The patch works for both
i386 and x86_64 archs. It works with MSIs just fine, and should not
intervene with implementations like shared vectors, when they get worked
out and incorporated.
To illustrate, below is the interrupt distribution for 2-cell ES7000 with
20 I/O APICs, and an Ethernet card in the last slot, which should be eth1
and which was not configured because its IRQ exceeded allowable number (it
actially turned out huge - 480!):
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 65716 30012 30007 30002 30009 30010 30010 30010 IO-APIC-edge timer
4: 373 0 725 280 0 0 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 3 0 0 0 0 0 0 IO-APIC-edge ide0
16: 108 13 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
18: 0 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb3
19: 15 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
96: 4240 397 18 0 0 0 0 0 IO-APIC-level aic7xxx
97: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx
192: 847 0 0 0 0 0 0 0 IO-APIC-level eth0
NMI: 0 0 0 0 0 0 0 0
LOC: 273423 274528 272829 274228 274092 273761 273827 273694
ERR: 7
MIS: 0
Even though the system doesn't have that many devices, some don't get
enabled only because of IRQ numbering model.
This is the IRQ picture after the patch was applied:
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 44169 10004 10004 10001 10004 10003 10004 6135 IO-APIC-edge timer
4: 345 0 0 0 0 244 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 0 3 0 0 0 0 0 IO-APIC-edge ide0
17: 4425 0 9 0 0 0 0 0 IO-APIC-level aic7xxx
18: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx, uhci_hcd:usb3
21: 231 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
22: 26 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
24: 348 0 0 0 0 0 0 0 IO-APIC-level eth0
25: 6 192 0 0 0 0 0 0 IO-APIC-level eth1
NMI: 0 0 0 0 0 0 0 0
LOC: 107981 107636 108899 108698 108489 108326 108331 108254
ERR: 7
MIS: 0
Not only we see the card in the last I/O APIC, but we are not even close to
using up available IRQs, since we didn't waste any.
Signed-off-by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
Acked-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 15:08:41 +08:00
|
|
|
return gsi_to_irq[gsi];
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
|
|
|
|
|
[PATCH] x86_64: avoid wasting IRQs
I suggest to change the way IRQs are handed out to PCI devices.
Currently, each I/O APIC pin gets associated with an IRQ, no matter if the
pin is used or not. It is expected that each pin can potentually be
engaged by a device inserted into the corresponding PCI slot. However,
this imposes severe limitation on systems that have designs that employ
many I/O APICs, only utilizing couple lines of each, such as P64H2 chipset.
It is used in ES7000, and currently, there is no way to boot the system
with more that 9 I/O APICs.
The simple change below allows to boot a system with say 64 (or more) I/O
APICs, each providing 1 slot, which otherwise impossible because of the IRQ
gaps created for unused lines on each I/O APIC. It does not resolve the
problem with number of devices that exceeds number of possible IRQs, but
eases up a tension for IRQs on any large system with potentually large
number of devices.
I only implemented this for the ACPI boot, since if the system is this big
and using newer chipsets it is probably (better be!) an ACPI based system
:). The change is completely "mechanical" and does not alter any internal
structures or interrupt model/implementation. The patch works for both
i386 and x86_64 archs. It works with MSIs just fine, and should not
intervene with implementations like shared vectors, when they get worked
out and incorporated.
To illustrate, below is the interrupt distribution for 2-cell ES7000 with
20 I/O APICs, and an Ethernet card in the last slot, which should be eth1
and which was not configured because its IRQ exceeded allowable number (it
actially turned out huge - 480!):
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 65716 30012 30007 30002 30009 30010 30010 30010 IO-APIC-edge timer
4: 373 0 725 280 0 0 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 3 0 0 0 0 0 0 IO-APIC-edge ide0
16: 108 13 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
18: 0 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb3
19: 15 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
96: 4240 397 18 0 0 0 0 0 IO-APIC-level aic7xxx
97: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx
192: 847 0 0 0 0 0 0 0 IO-APIC-level eth0
NMI: 0 0 0 0 0 0 0 0
LOC: 273423 274528 272829 274228 274092 273761 273827 273694
ERR: 7
MIS: 0
Even though the system doesn't have that many devices, some don't get
enabled only because of IRQ numbering model.
This is the IRQ picture after the patch was applied:
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 44169 10004 10004 10001 10004 10003 10004 6135 IO-APIC-edge timer
4: 345 0 0 0 0 244 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 0 3 0 0 0 0 0 IO-APIC-edge ide0
17: 4425 0 9 0 0 0 0 0 IO-APIC-level aic7xxx
18: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx, uhci_hcd:usb3
21: 231 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
22: 26 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
24: 348 0 0 0 0 0 0 0 IO-APIC-level eth0
25: 6 192 0 0 0 0 0 0 IO-APIC-level eth1
NMI: 0 0 0 0 0 0 0 0
LOC: 107981 107636 108899 108698 108489 108326 108331 108254
ERR: 7
MIS: 0
Not only we see the card in the last I/O APIC, but we are not even close to
using up available IRQs, since we didn't waste any.
Signed-off-by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
Acked-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 15:08:41 +08:00
|
|
|
if (edge_level) {
|
|
|
|
/*
|
|
|
|
* For PCI devices assign IRQs in order, avoiding gaps
|
|
|
|
* due to unused I/O APIC pins.
|
|
|
|
*/
|
|
|
|
int irq = gsi;
|
2005-07-31 02:25:32 +08:00
|
|
|
if (gsi < MAX_GSI_NUM) {
|
|
|
|
if (gsi > 15)
|
|
|
|
gsi = pci_irq++;
|
|
|
|
#ifdef CONFIG_ACPI_BUS
|
|
|
|
/*
|
|
|
|
* Don't assign IRQ used by ACPI SCI
|
|
|
|
*/
|
|
|
|
if (gsi == acpi_fadt.sci_int)
|
|
|
|
gsi = pci_irq++;
|
|
|
|
#endif
|
|
|
|
gsi_to_irq[irq] = gsi;
|
|
|
|
} else {
|
|
|
|
printk(KERN_ERR "GSI %u is too high\n", gsi);
|
|
|
|
return gsi;
|
|
|
|
}
|
[PATCH] x86_64: avoid wasting IRQs
I suggest to change the way IRQs are handed out to PCI devices.
Currently, each I/O APIC pin gets associated with an IRQ, no matter if the
pin is used or not. It is expected that each pin can potentually be
engaged by a device inserted into the corresponding PCI slot. However,
this imposes severe limitation on systems that have designs that employ
many I/O APICs, only utilizing couple lines of each, such as P64H2 chipset.
It is used in ES7000, and currently, there is no way to boot the system
with more that 9 I/O APICs.
The simple change below allows to boot a system with say 64 (or more) I/O
APICs, each providing 1 slot, which otherwise impossible because of the IRQ
gaps created for unused lines on each I/O APIC. It does not resolve the
problem with number of devices that exceeds number of possible IRQs, but
eases up a tension for IRQs on any large system with potentually large
number of devices.
I only implemented this for the ACPI boot, since if the system is this big
and using newer chipsets it is probably (better be!) an ACPI based system
:). The change is completely "mechanical" and does not alter any internal
structures or interrupt model/implementation. The patch works for both
i386 and x86_64 archs. It works with MSIs just fine, and should not
intervene with implementations like shared vectors, when they get worked
out and incorporated.
To illustrate, below is the interrupt distribution for 2-cell ES7000 with
20 I/O APICs, and an Ethernet card in the last slot, which should be eth1
and which was not configured because its IRQ exceeded allowable number (it
actially turned out huge - 480!):
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 65716 30012 30007 30002 30009 30010 30010 30010 IO-APIC-edge timer
4: 373 0 725 280 0 0 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 3 0 0 0 0 0 0 IO-APIC-edge ide0
16: 108 13 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
18: 0 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb3
19: 15 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
96: 4240 397 18 0 0 0 0 0 IO-APIC-level aic7xxx
97: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx
192: 847 0 0 0 0 0 0 0 IO-APIC-level eth0
NMI: 0 0 0 0 0 0 0 0
LOC: 273423 274528 272829 274228 274092 273761 273827 273694
ERR: 7
MIS: 0
Even though the system doesn't have that many devices, some don't get
enabled only because of IRQ numbering model.
This is the IRQ picture after the patch was applied:
zorro-tb2:~ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
0: 44169 10004 10004 10001 10004 10003 10004 6135 IO-APIC-edge timer
4: 345 0 0 0 0 244 0 0 IO-APIC-edge serial
8: 0 0 0 0 0 0 0 0 IO-APIC-edge rtc
9: 0 0 0 0 0 0 0 0 IO-APIC-level acpi
14: 39 0 3 0 0 0 0 0 IO-APIC-edge ide0
17: 4425 0 9 0 0 0 0 0 IO-APIC-level aic7xxx
18: 15 0 0 0 0 0 0 0 IO-APIC-level aic7xxx, uhci_hcd:usb3
21: 231 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb1
22: 26 0 0 0 0 0 0 0 IO-APIC-level uhci_hcd:usb2
23: 3 0 0 0 0 0 0 0 IO-APIC-level ehci_hcd:usb4
24: 348 0 0 0 0 0 0 0 IO-APIC-level eth0
25: 6 192 0 0 0 0 0 0 IO-APIC-level eth1
NMI: 0 0 0 0 0 0 0 0
LOC: 107981 107636 108899 108698 108489 108326 108331 108254
ERR: 7
MIS: 0
Not only we see the card in the last I/O APIC, but we are not even close to
using up available IRQs, since we didn't waste any.
Signed-off-by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
Acked-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 15:08:41 +08:00
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
|
|
|
|
edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
|
|
|
|
active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
|
|
|
|
return gsi;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /*CONFIG_X86_IO_APIC*/
|
|
|
|
#endif /*CONFIG_ACPI_BOOT*/
|