2014-11-15 00:52:28 +08:00
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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2014-11-15 00:52:29 +08:00
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/**
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* DOC: Panel Self Refresh (PSR/SRD)
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*
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* Since Haswell Display controller supports Panel Self-Refresh on display
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* panels witch have a remote frame buffer (RFB) implemented according to PSR
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* spec in eDP1.3. PSR feature allows the display to go to lower standby states
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* when system is idle but display is on as it eliminates display refresh
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* request to DDR memory completely as long as the frame buffer for that
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* display is unchanged.
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*
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* Panel Self Refresh must be supported by both Hardware (source) and
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* Panel (sink).
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*
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* PSR saves power by caching the framebuffer in the panel RFB, which allows us
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* to power down the link and memory controller. For DSI panels the same idea
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* is called "manual mode".
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*
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* The implementation uses the hardware-based PSR support which automatically
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* enters/exits self-refresh mode. The hardware takes care of sending the
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* required DP aux message and could even retrain the link (that part isn't
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* enabled yet though). The hardware also keeps track of any frontbuffer
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* changes to know when to exit self-refresh mode again. Unfortunately that
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* part doesn't work too well, hence why the i915 PSR support uses the
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* software frontbuffer tracking to make sure it doesn't miss a screen
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* update. For this integration intel_psr_invalidate() and intel_psr_flush()
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* get called by the frontbuffer tracking code. Note that because of locking
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* issues the self-refresh re-enable code is done from a work queue, which
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* must be correctly synchronized/cancelled when shutting down the pipe."
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*/
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2014-11-15 00:52:28 +08:00
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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2018-08-09 22:21:01 +08:00
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static bool psr_global_enabled(u32 debug)
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{
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switch (debug & I915_PSR_DEBUG_MODE_MASK) {
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case I915_PSR_DEBUG_DEFAULT:
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return i915_modparams.enable_psr;
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case I915_PSR_DEBUG_DISABLE:
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return false;
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default:
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return true;
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}
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}
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2018-08-08 22:19:11 +08:00
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static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
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const struct intel_crtc_state *crtc_state)
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{
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2018-09-28 14:11:17 +08:00
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/* Disable PSR2 by default for all platforms */
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if (i915_modparams.enable_psr == -1)
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return false;
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2018-08-08 22:19:11 +08:00
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switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
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case I915_PSR_DEBUG_FORCE_PSR1:
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return false;
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default:
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return crtc_state->has_psr2;
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}
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}
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2018-11-20 17:23:24 +08:00
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static int edp_psr_shift(enum transcoder cpu_transcoder)
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{
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switch (cpu_transcoder) {
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case TRANSCODER_A:
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return EDP_PSR_TRANSCODER_A_SHIFT;
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case TRANSCODER_B:
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return EDP_PSR_TRANSCODER_B_SHIFT;
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case TRANSCODER_C:
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return EDP_PSR_TRANSCODER_C_SHIFT;
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default:
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MISSING_CASE(cpu_transcoder);
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/* fallthrough */
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case TRANSCODER_EDP:
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return EDP_PSR_TRANSCODER_EDP_SHIFT;
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}
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}
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2018-08-22 06:11:56 +08:00
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void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
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2018-04-05 09:37:17 +08:00
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{
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u32 debug_mask, mask;
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2018-11-20 17:23:24 +08:00
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enum transcoder cpu_transcoder;
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u32 transcoders = BIT(TRANSCODER_EDP);
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2018-04-05 09:37:17 +08:00
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2018-11-20 17:23:24 +08:00
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if (INTEL_GEN(dev_priv) >= 8)
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transcoders |= BIT(TRANSCODER_A) |
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BIT(TRANSCODER_B) |
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BIT(TRANSCODER_C);
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debug_mask = 0;
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mask = 0;
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for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
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int shift = edp_psr_shift(cpu_transcoder);
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mask |= EDP_PSR_ERROR(shift);
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debug_mask |= EDP_PSR_POST_EXIT(shift) |
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EDP_PSR_PRE_ENTRY(shift);
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2018-04-05 09:37:17 +08:00
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}
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2018-08-22 06:11:56 +08:00
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if (debug & I915_PSR_DEBUG_IRQ)
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2018-04-05 09:37:17 +08:00
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mask |= debug_mask;
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I915_WRITE(EDP_PSR_IMR, ~mask);
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}
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2018-04-26 05:23:32 +08:00
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static void psr_event_print(u32 val, bool psr2_enabled)
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{
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DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);
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if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
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DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
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if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
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DRM_DEBUG_KMS("\tPSR2 disabled\n");
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if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
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DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
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if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
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DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
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if (val & PSR_EVENT_GRAPHICS_RESET)
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DRM_DEBUG_KMS("\tGraphics reset\n");
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if (val & PSR_EVENT_PCH_INTERRUPT)
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DRM_DEBUG_KMS("\tPCH interrupt\n");
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if (val & PSR_EVENT_MEMORY_UP)
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DRM_DEBUG_KMS("\tMemory up\n");
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if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
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DRM_DEBUG_KMS("\tFront buffer modification\n");
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if (val & PSR_EVENT_WD_TIMER_EXPIRE)
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DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");
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if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
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DRM_DEBUG_KMS("\tPIPE registers updated\n");
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if (val & PSR_EVENT_REGISTER_UPDATE)
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DRM_DEBUG_KMS("\tRegister updated\n");
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if (val & PSR_EVENT_HDCP_ENABLE)
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DRM_DEBUG_KMS("\tHDCP enabled\n");
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if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
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DRM_DEBUG_KMS("\tKVMR session enabled\n");
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if (val & PSR_EVENT_VBI_ENABLE)
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DRM_DEBUG_KMS("\tVBI enabled\n");
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if (val & PSR_EVENT_LPSP_MODE_EXIT)
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DRM_DEBUG_KMS("\tLPSP mode exited\n");
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if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
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DRM_DEBUG_KMS("\tPSR disabled\n");
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}
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2018-04-05 09:37:17 +08:00
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void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
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{
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u32 transcoders = BIT(TRANSCODER_EDP);
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enum transcoder cpu_transcoder;
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2018-04-04 05:24:20 +08:00
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ktime_t time_ns = ktime_get();
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2018-11-22 06:54:39 +08:00
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u32 mask = 0;
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2018-04-05 09:37:17 +08:00
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if (INTEL_GEN(dev_priv) >= 8)
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transcoders |= BIT(TRANSCODER_A) |
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BIT(TRANSCODER_B) |
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BIT(TRANSCODER_C);
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for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
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2018-11-20 17:23:24 +08:00
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int shift = edp_psr_shift(cpu_transcoder);
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2018-11-22 06:54:39 +08:00
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if (psr_iir & EDP_PSR_ERROR(shift)) {
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DRM_WARN("[transcoder %s] PSR aux error\n",
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transcoder_name(cpu_transcoder));
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dev_priv->psr.irq_aux_error = true;
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/*
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* If this interruption is not masked it will keep
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* interrupting so fast that it prevents the scheduled
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* work to run.
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* Also after a PSR error, we don't want to arm PSR
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* again so we don't care about unmask the interruption
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* or unset irq_aux_error.
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*/
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mask |= EDP_PSR_ERROR(shift);
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}
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2018-04-05 09:37:17 +08:00
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2018-11-20 17:23:24 +08:00
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if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
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2018-04-04 05:24:20 +08:00
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dev_priv->psr.last_entry_attempt = time_ns;
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2018-04-05 09:37:17 +08:00
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DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
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transcoder_name(cpu_transcoder));
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2018-04-04 05:24:20 +08:00
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}
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2018-04-05 09:37:17 +08:00
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2018-11-20 17:23:24 +08:00
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if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
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2018-04-04 05:24:20 +08:00
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dev_priv->psr.last_exit = time_ns;
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2018-04-05 09:37:17 +08:00
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DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
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transcoder_name(cpu_transcoder));
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2018-04-26 05:23:32 +08:00
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if (INTEL_GEN(dev_priv) >= 9) {
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u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
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bool psr2_enabled = dev_priv->psr.psr2_enabled;
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I915_WRITE(PSR_EVENT(cpu_transcoder), val);
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psr_event_print(val, psr2_enabled);
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}
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2018-04-04 05:24:20 +08:00
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}
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2018-04-05 09:37:17 +08:00
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}
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2018-11-22 06:54:39 +08:00
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if (mask) {
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mask |= I915_READ(EDP_PSR_IMR);
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I915_WRITE(EDP_PSR_IMR, mask);
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schedule_work(&dev_priv->psr.work);
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}
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2018-04-05 09:37:17 +08:00
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}
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2018-02-24 06:15:17 +08:00
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static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
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{
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uint8_t dprx = 0;
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if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
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&dprx) != 1)
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return false;
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return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
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}
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static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
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{
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uint8_t alpm_caps = 0;
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if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
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&alpm_caps) != 1)
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return false;
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return alpm_caps & DP_ALPM_CAP;
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}
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2018-03-29 06:30:44 +08:00
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static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
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{
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2018-05-12 03:51:44 +08:00
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u8 val = 8; /* assume the worst if we can't read the value */
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2018-03-29 06:30:44 +08:00
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
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val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
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else
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2018-05-12 03:51:44 +08:00
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DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");
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2018-03-29 06:30:44 +08:00
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return val;
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}
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2018-02-24 06:15:17 +08:00
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void intel_psr_init_dpcd(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv =
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to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
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drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
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sizeof(intel_dp->psr_dpcd));
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2018-05-12 03:51:40 +08:00
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if (!intel_dp->psr_dpcd[0])
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return;
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DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",
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intel_dp->psr_dpcd[0]);
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2018-05-12 03:51:41 +08:00
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if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
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DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
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return;
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}
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2018-05-12 03:51:40 +08:00
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dev_priv->psr.sink_support = true;
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2018-05-25 11:30:47 +08:00
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dev_priv->psr.sink_sync_latency =
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intel_dp_get_sink_sync_latency(intel_dp);
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2018-02-24 06:15:17 +08:00
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2018-08-09 22:21:01 +08:00
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WARN_ON(dev_priv->psr.dp);
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dev_priv->psr.dp = intel_dp;
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2018-02-24 06:15:17 +08:00
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if (INTEL_GEN(dev_priv) >= 9 &&
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2018-03-29 06:30:40 +08:00
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(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
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2018-05-12 03:51:45 +08:00
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bool y_req = intel_dp->psr_dpcd[1] &
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DP_PSR2_SU_Y_COORDINATE_REQUIRED;
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bool alpm = intel_dp_get_alpm_status(intel_dp);
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2018-03-29 06:30:40 +08:00
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/*
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* All panels that supports PSR version 03h (PSR2 +
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* Y-coordinate) can handle Y-coordinates in VSC but we are
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* only sure that it is going to be used when required by the
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* panel. This way panel is capable to do selective update
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* without a aux frame sync.
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*
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* To support PSR version 02h and PSR version 03h without
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* Y-coordinate requirement panels we would need to enable
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* GTC first.
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*/
|
2018-05-12 03:51:45 +08:00
|
|
|
dev_priv->psr.sink_psr2_support = y_req && alpm;
|
2018-05-12 03:51:40 +08:00
|
|
|
DRM_DEBUG_KMS("PSR2 %ssupported\n",
|
|
|
|
dev_priv->psr.sink_psr2_support ? "" : "not ");
|
2018-02-24 06:15:17 +08:00
|
|
|
|
2018-03-29 06:30:42 +08:00
|
|
|
if (dev_priv->psr.sink_psr2_support) {
|
2018-02-24 06:15:17 +08:00
|
|
|
dev_priv->psr.colorimetry_support =
|
|
|
|
intel_dp_get_colorimetry_status(intel_dp);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-26 13:25:36 +08:00
|
|
|
static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2015-04-02 13:32:44 +08:00
|
|
|
{
|
2017-01-02 19:30:55 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2017-08-18 21:49:56 +08:00
|
|
|
struct edp_vsc_psr psr_vsc;
|
2015-04-02 13:32:44 +08:00
|
|
|
|
2018-03-29 06:30:42 +08:00
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
2017-09-08 07:00:35 +08:00
|
|
|
/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
|
|
|
|
memset(&psr_vsc, 0, sizeof(psr_vsc));
|
|
|
|
psr_vsc.sdp_header.HB0 = 0;
|
|
|
|
psr_vsc.sdp_header.HB1 = 0x7;
|
2018-03-29 06:30:40 +08:00
|
|
|
if (dev_priv->psr.colorimetry_support) {
|
2017-09-08 07:00:35 +08:00
|
|
|
psr_vsc.sdp_header.HB2 = 0x5;
|
|
|
|
psr_vsc.sdp_header.HB3 = 0x13;
|
2018-03-29 06:30:40 +08:00
|
|
|
} else {
|
2017-09-08 07:00:35 +08:00
|
|
|
psr_vsc.sdp_header.HB2 = 0x4;
|
|
|
|
psr_vsc.sdp_header.HB3 = 0xe;
|
|
|
|
}
|
2017-01-02 19:30:55 +08:00
|
|
|
} else {
|
2017-09-08 07:00:35 +08:00
|
|
|
/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
|
|
|
|
memset(&psr_vsc, 0, sizeof(psr_vsc));
|
|
|
|
psr_vsc.sdp_header.HB0 = 0;
|
|
|
|
psr_vsc.sdp_header.HB1 = 0x7;
|
|
|
|
psr_vsc.sdp_header.HB2 = 0x2;
|
|
|
|
psr_vsc.sdp_header.HB3 = 0x8;
|
2017-01-02 19:30:55 +08:00
|
|
|
}
|
|
|
|
|
2018-09-21 02:51:36 +08:00
|
|
|
intel_dig_port->write_infoframe(&intel_dig_port->base,
|
|
|
|
crtc_state,
|
2017-10-14 03:40:51 +08:00
|
|
|
DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
|
2015-04-02 13:32:44 +08:00
|
|
|
}
|
|
|
|
|
2018-03-13 11:46:45 +08:00
|
|
|
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2018-03-13 11:46:46 +08:00
|
|
|
u32 aux_clock_divider, aux_ctl;
|
|
|
|
int i;
|
2014-11-15 00:52:28 +08:00
|
|
|
static const uint8_t aux_msg[] = {
|
|
|
|
[0] = DP_AUX_NATIVE_WRITE << 4,
|
|
|
|
[1] = DP_SET_POWER >> 8,
|
|
|
|
[2] = DP_SET_POWER & 0xff,
|
|
|
|
[3] = 1 - 1,
|
|
|
|
[4] = DP_SET_POWER_D0,
|
|
|
|
};
|
2018-03-13 11:46:46 +08:00
|
|
|
u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
|
|
|
|
EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
|
|
|
|
EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
|
|
|
|
EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
|
2014-11-15 00:52:28 +08:00
|
|
|
|
|
|
|
BUILD_BUG_ON(sizeof(aux_msg) > 20);
|
2018-03-13 11:46:45 +08:00
|
|
|
for (i = 0; i < sizeof(aux_msg); i += 4)
|
2018-03-13 11:46:46 +08:00
|
|
|
I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
|
2018-03-13 11:46:45 +08:00
|
|
|
intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
|
|
|
|
|
2018-03-13 11:46:46 +08:00
|
|
|
aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
|
|
|
|
|
|
|
|
/* Start with bits set for DDI_AUX_CTL register */
|
2018-05-24 02:04:35 +08:00
|
|
|
aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
|
2018-03-13 11:46:45 +08:00
|
|
|
aux_clock_divider);
|
2018-03-13 11:46:46 +08:00
|
|
|
|
|
|
|
/* Select only valid bits for SRD_AUX_CTL */
|
|
|
|
aux_ctl &= psr_aux_mask;
|
|
|
|
I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
|
2018-03-13 11:46:45 +08:00
|
|
|
}
|
|
|
|
|
2018-06-26 13:25:36 +08:00
|
|
|
static void intel_psr_enable_sink(struct intel_dp *intel_dp)
|
2018-03-13 11:46:45 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2018-03-29 06:30:45 +08:00
|
|
|
u8 dpcd_val = DP_PSR_ENABLE;
|
2018-03-13 11:46:45 +08:00
|
|
|
|
2017-01-02 19:30:58 +08:00
|
|
|
/* Enable ALPM at sink for psr2 */
|
2018-05-12 03:51:45 +08:00
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
|
|
|
|
DP_ALPM_ENABLE);
|
2018-03-29 06:30:45 +08:00
|
|
|
dpcd_val |= DP_PSR_ENABLE_PSR2;
|
2018-05-12 03:51:45 +08:00
|
|
|
}
|
|
|
|
|
2016-05-19 00:47:14 +08:00
|
|
|
if (dev_priv->psr.link_standby)
|
2018-03-29 06:30:45 +08:00
|
|
|
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
|
2018-06-27 04:16:44 +08:00
|
|
|
if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
|
|
|
|
dpcd_val |= DP_PSR_CRC_VERIFICATION;
|
2018-03-29 06:30:45 +08:00
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
|
2016-05-19 00:47:14 +08:00
|
|
|
|
2018-03-13 11:46:46 +08:00
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
|
|
|
|
2017-09-08 07:00:33 +08:00
|
|
|
static void hsw_activate_psr1(struct intel_dp *intel_dp)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2018-05-25 11:30:47 +08:00
|
|
|
u32 max_sleep_time = 0x1f;
|
|
|
|
u32 val = EDP_PSR_ENABLE;
|
2015-04-02 13:32:44 +08:00
|
|
|
|
2018-05-25 11:30:47 +08:00
|
|
|
/* Let's use 6 as the minimum to cover all known cases including the
|
|
|
|
* off-by-one issue that HW has in some cases.
|
2014-11-15 00:52:31 +08:00
|
|
|
*/
|
2018-05-25 11:30:47 +08:00
|
|
|
int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
|
2016-05-19 00:47:11 +08:00
|
|
|
|
2018-05-25 11:30:47 +08:00
|
|
|
/* sink_sync_latency of 8 means source has to wait for more than 8
|
|
|
|
* frames, we'll go with 9 frames for now
|
|
|
|
*/
|
|
|
|
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
|
2016-05-19 00:47:11 +08:00
|
|
|
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
|
2015-12-12 08:31:31 +08:00
|
|
|
|
2018-05-25 11:30:47 +08:00
|
|
|
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
|
2016-10-13 18:03:01 +08:00
|
|
|
if (IS_HASWELL(dev_priv))
|
2015-12-12 08:31:31 +08:00
|
|
|
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2016-02-02 04:02:07 +08:00
|
|
|
if (dev_priv->psr.link_standby)
|
|
|
|
val |= EDP_PSR_LINK_STANDBY;
|
|
|
|
|
2018-05-22 17:27:23 +08:00
|
|
|
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
|
|
|
|
val |= EDP_PSR_TP1_TIME_0us;
|
|
|
|
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
|
2016-05-19 00:47:11 +08:00
|
|
|
val |= EDP_PSR_TP1_TIME_100us;
|
2018-05-22 17:27:23 +08:00
|
|
|
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
|
|
|
|
val |= EDP_PSR_TP1_TIME_500us;
|
2016-05-19 00:47:11 +08:00
|
|
|
else
|
2018-05-22 17:27:23 +08:00
|
|
|
val |= EDP_PSR_TP1_TIME_2500us;
|
2016-05-19 00:47:11 +08:00
|
|
|
|
2018-05-22 17:27:23 +08:00
|
|
|
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
|
|
|
|
val |= EDP_PSR_TP2_TP3_TIME_0us;
|
|
|
|
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
|
2016-05-19 00:47:11 +08:00
|
|
|
val |= EDP_PSR_TP2_TP3_TIME_100us;
|
2018-05-22 17:27:23 +08:00
|
|
|
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
|
|
|
|
val |= EDP_PSR_TP2_TP3_TIME_500us;
|
2016-05-19 00:47:11 +08:00
|
|
|
else
|
2018-05-22 17:27:23 +08:00
|
|
|
val |= EDP_PSR_TP2_TP3_TIME_2500us;
|
2016-05-19 00:47:11 +08:00
|
|
|
|
|
|
|
if (intel_dp_source_supports_hbr2(intel_dp) &&
|
|
|
|
drm_dp_tps3_supported(intel_dp->dpcd))
|
|
|
|
val |= EDP_PSR_TP1_TP3_SEL;
|
|
|
|
else
|
|
|
|
val |= EDP_PSR_TP1_TP2_SEL;
|
|
|
|
|
2018-06-27 04:16:44 +08:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
|
|
val |= EDP_PSR_CRC_ENABLE;
|
|
|
|
|
2017-08-09 05:51:34 +08:00
|
|
|
val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
|
2016-05-19 00:47:11 +08:00
|
|
|
I915_WRITE(EDP_PSR_CTL, val);
|
drm/i915/psr: fix blank screen issue for psr2
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_STATUS register, which has wrong data, resulting
in blankscreen.
hsw_enable_source is split into hsw_enable_source_psr1 and
hsw_enable_source_psr2 for easier code review and maintenance,
as suggested by rodrigo and jim.
v2: (Rodrigo)
- Rename hsw_enable_source_psr* to intel_enable_source_psr*
v3: (Rodrigo)
- In hsw_psr_disable ,
1) for psr active case, handle psr2 followed by psr1.
2) psr inactive case, handle psr2 followed by psr1
v4:(Rodrigo)
- move psr2 restriction(32X20) to match_conditions function
returning false and fully blocking PSR to a new patch before
this one.
v5: in source_psr2, removed val = EDP_PSR_ENABLE
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1484244059-9201-1-git-send-email-vathsala.nagaraju@intel.com
2017-01-13 02:00:59 +08:00
|
|
|
}
|
2016-05-19 00:47:11 +08:00
|
|
|
|
2017-09-08 07:00:33 +08:00
|
|
|
static void hsw_activate_psr2(struct intel_dp *intel_dp)
|
drm/i915/psr: fix blank screen issue for psr2
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_STATUS register, which has wrong data, resulting
in blankscreen.
hsw_enable_source is split into hsw_enable_source_psr1 and
hsw_enable_source_psr2 for easier code review and maintenance,
as suggested by rodrigo and jim.
v2: (Rodrigo)
- Rename hsw_enable_source_psr* to intel_enable_source_psr*
v3: (Rodrigo)
- In hsw_psr_disable ,
1) for psr active case, handle psr2 followed by psr1.
2) psr inactive case, handle psr2 followed by psr1
v4:(Rodrigo)
- move psr2 restriction(32X20) to match_conditions function
returning false and fully blocking PSR to a new patch before
this one.
v5: in source_psr2, removed val = EDP_PSR_ENABLE
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1484244059-9201-1-git-send-email-vathsala.nagaraju@intel.com
2017-01-13 02:00:59 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2018-05-25 11:30:47 +08:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* Let's use 6 as the minimum to cover all known cases including the
|
|
|
|
* off-by-one issue that HW has in some cases.
|
drm/i915/psr: fix blank screen issue for psr2
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_STATUS register, which has wrong data, resulting
in blankscreen.
hsw_enable_source is split into hsw_enable_source_psr1 and
hsw_enable_source_psr2 for easier code review and maintenance,
as suggested by rodrigo and jim.
v2: (Rodrigo)
- Rename hsw_enable_source_psr* to intel_enable_source_psr*
v3: (Rodrigo)
- In hsw_psr_disable ,
1) for psr active case, handle psr2 followed by psr1.
2) psr inactive case, handle psr2 followed by psr1
v4:(Rodrigo)
- move psr2 restriction(32X20) to match_conditions function
returning false and fully blocking PSR to a new patch before
this one.
v5: in source_psr2, removed val = EDP_PSR_ENABLE
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1484244059-9201-1-git-send-email-vathsala.nagaraju@intel.com
2017-01-13 02:00:59 +08:00
|
|
|
*/
|
2018-05-25 11:30:47 +08:00
|
|
|
int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
|
|
|
|
|
|
|
|
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
|
|
|
|
val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
|
2016-05-19 00:47:11 +08:00
|
|
|
|
|
|
|
/* FIXME: selective update is probably totally broken because it doesn't
|
|
|
|
* mesh at all with our frontbuffer tracking. And the hw alone isn't
|
|
|
|
* good enough. */
|
2018-03-29 06:30:41 +08:00
|
|
|
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
|
2018-04-26 05:23:34 +08:00
|
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
|
|
|
|
val |= EDP_Y_COORDINATE_ENABLE;
|
2017-09-26 17:59:13 +08:00
|
|
|
|
2018-03-29 06:30:44 +08:00
|
|
|
val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
|
2016-05-19 00:47:11 +08:00
|
|
|
|
2018-05-22 17:27:23 +08:00
|
|
|
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
|
|
|
|
dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
|
|
|
|
val |= EDP_PSR2_TP2_TIME_50us;
|
|
|
|
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
|
|
|
|
val |= EDP_PSR2_TP2_TIME_100us;
|
|
|
|
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
|
|
|
|
val |= EDP_PSR2_TP2_TIME_500us;
|
2016-05-19 00:47:11 +08:00
|
|
|
else
|
2018-05-22 17:27:23 +08:00
|
|
|
val |= EDP_PSR2_TP2_TIME_2500us;
|
2015-04-02 13:32:44 +08:00
|
|
|
|
2016-05-19 00:47:11 +08:00
|
|
|
I915_WRITE(EDP_PSR2_CTL, val);
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
|
|
|
|
2018-02-28 05:29:13 +08:00
|
|
|
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2018-03-07 04:33:55 +08:00
|
|
|
int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
|
|
|
|
int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
|
|
|
|
int psr_max_h = 0, psr_max_v = 0;
|
2018-02-28 05:29:13 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME psr2_support is messed up. It's both computed
|
|
|
|
* dynamically during PSR enable, and extracted from sink
|
|
|
|
* caps during eDP detection.
|
|
|
|
*/
|
2018-03-29 06:30:42 +08:00
|
|
|
if (!dev_priv->psr.sink_psr2_support)
|
2018-02-28 05:29:13 +08:00
|
|
|
return false;
|
|
|
|
|
2018-03-07 04:33:55 +08:00
|
|
|
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
|
|
|
|
psr_max_h = 4096;
|
|
|
|
psr_max_v = 2304;
|
|
|
|
} else if (IS_GEN9(dev_priv)) {
|
|
|
|
psr_max_h = 3640;
|
|
|
|
psr_max_v = 2304;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
|
|
|
|
DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
|
|
|
|
crtc_hdisplay, crtc_vdisplay,
|
|
|
|
psr_max_h, psr_max_v);
|
2018-02-28 05:29:13 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-10-12 21:02:01 +08:00
|
|
|
void intel_psr_compute_config(struct intel_dp *intel_dp,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2016-05-18 16:34:38 +08:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
2017-10-12 21:02:01 +08:00
|
|
|
&crtc_state->base.adjusted_mode;
|
2016-05-18 16:34:38 +08:00
|
|
|
int psr_setup_time;
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2018-01-04 05:38:23 +08:00
|
|
|
if (!CAN_PSR(dev_priv))
|
2017-10-12 21:02:01 +08:00
|
|
|
return;
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
if (intel_dp != dev_priv->psr.dp)
|
2017-10-12 21:02:01 +08:00
|
|
|
return;
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2016-02-02 04:02:06 +08:00
|
|
|
/*
|
|
|
|
* HSW spec explicitly says PSR is tied to port A.
|
|
|
|
* BDW+ platforms with DDI implementation of PSR have different
|
|
|
|
* PSR registers per transcoder and we only implement transcoder EDP
|
|
|
|
* ones. Since by Display design transcoder EDP is tied to port A
|
|
|
|
* we can safely escape based on the port A.
|
|
|
|
*/
|
2018-05-12 07:00:59 +08:00
|
|
|
if (dig_port->base.port != PORT_A) {
|
2016-02-02 04:02:06 +08:00
|
|
|
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
|
2017-10-12 21:02:01 +08:00
|
|
|
return;
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
|
|
|
|
2018-11-22 06:54:38 +08:00
|
|
|
if (dev_priv->psr.sink_not_reliable) {
|
|
|
|
DRM_DEBUG_KMS("PSR sink implementation is not reliable\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-10-13 18:03:01 +08:00
|
|
|
if (IS_HASWELL(dev_priv) &&
|
2017-10-12 21:02:01 +08:00
|
|
|
I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
|
2015-01-13 02:14:29 +08:00
|
|
|
S3D_ENABLE) {
|
2014-11-15 00:52:28 +08:00
|
|
|
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
|
2017-10-12 21:02:01 +08:00
|
|
|
return;
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
|
|
|
|
2016-10-13 18:03:01 +08:00
|
|
|
if (IS_HASWELL(dev_priv) &&
|
2016-05-18 16:34:38 +08:00
|
|
|
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
2014-11-15 00:52:28 +08:00
|
|
|
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
|
2017-10-12 21:02:01 +08:00
|
|
|
return;
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
|
|
|
|
2016-05-18 16:34:38 +08:00
|
|
|
psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
|
|
|
|
if (psr_setup_time < 0) {
|
|
|
|
DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
|
|
|
|
intel_dp->psr_dpcd[1]);
|
2017-10-12 21:02:01 +08:00
|
|
|
return;
|
2016-05-18 16:34:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
|
|
|
|
adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
|
|
|
|
DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
|
|
|
|
psr_setup_time);
|
2017-10-12 21:02:01 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
crtc_state->has_psr = true;
|
2018-02-28 05:29:13 +08:00
|
|
|
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
|
|
|
|
2014-11-19 23:37:00 +08:00
|
|
|
static void intel_psr_activate(struct intel_dp *intel_dp)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2018-06-26 17:05:22 +08:00
|
|
|
if (INTEL_GEN(dev_priv) >= 9)
|
drm/i915/psr: fix blank screen issue for psr2
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_STATUS register, which has wrong data, resulting
in blankscreen.
hsw_enable_source is split into hsw_enable_source_psr1 and
hsw_enable_source_psr2 for easier code review and maintenance,
as suggested by rodrigo and jim.
v2: (Rodrigo)
- Rename hsw_enable_source_psr* to intel_enable_source_psr*
v3: (Rodrigo)
- In hsw_psr_disable ,
1) for psr active case, handle psr2 followed by psr1.
2) psr inactive case, handle psr2 followed by psr1
v4:(Rodrigo)
- move psr2 restriction(32X20) to match_conditions function
returning false and fully blocking PSR to a new patch before
this one.
v5: in source_psr2, removed val = EDP_PSR_ENABLE
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1484244059-9201-1-git-send-email-vathsala.nagaraju@intel.com
2017-01-13 02:00:59 +08:00
|
|
|
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
|
2018-06-26 17:05:22 +08:00
|
|
|
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
|
2014-11-15 00:52:28 +08:00
|
|
|
WARN_ON(dev_priv->psr.active);
|
|
|
|
lockdep_assert_held(&dev_priv->psr.lock);
|
|
|
|
|
2018-06-26 13:25:36 +08:00
|
|
|
/* psr1 and psr2 are mutually exclusive.*/
|
|
|
|
if (dev_priv->psr.psr2_enabled)
|
|
|
|
hsw_activate_psr2(intel_dp);
|
|
|
|
else
|
|
|
|
hsw_activate_psr1(intel_dp);
|
|
|
|
|
2014-11-15 00:52:28 +08:00
|
|
|
dev_priv->psr.active = true;
|
|
|
|
}
|
|
|
|
|
2018-11-20 02:00:21 +08:00
|
|
|
static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder)
|
|
|
|
{
|
|
|
|
static const i915_reg_t regs[] = {
|
|
|
|
[TRANSCODER_A] = CHICKEN_TRANS_A,
|
|
|
|
[TRANSCODER_B] = CHICKEN_TRANS_B,
|
|
|
|
[TRANSCODER_C] = CHICKEN_TRANS_C,
|
|
|
|
[TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
|
|
|
|
};
|
|
|
|
|
|
|
|
WARN_ON(INTEL_GEN(dev_priv) < 9);
|
|
|
|
|
|
|
|
if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
|
|
|
|
!regs[cpu_transcoder].reg))
|
|
|
|
cpu_transcoder = TRANSCODER_A;
|
|
|
|
|
|
|
|
return regs[cpu_transcoder];
|
|
|
|
}
|
|
|
|
|
2018-06-26 13:25:36 +08:00
|
|
|
static void intel_psr_enable_source(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2017-09-08 07:00:36 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2017-09-08 07:00:36 +08:00
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2018-10-04 04:50:26 +08:00
|
|
|
u32 mask;
|
2017-09-08 07:00:36 +08:00
|
|
|
|
2018-03-13 11:46:46 +08:00
|
|
|
/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
|
|
|
|
* use hardcoded values PSR AUX transactions
|
|
|
|
*/
|
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
|
|
|
hsw_psr_setup_aux(intel_dp);
|
|
|
|
|
2018-03-29 06:30:42 +08:00
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
2018-11-20 02:00:21 +08:00
|
|
|
i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
|
|
|
|
cpu_transcoder);
|
|
|
|
u32 chicken = I915_READ(reg);
|
2018-03-29 06:30:41 +08:00
|
|
|
|
2018-10-27 03:51:42 +08:00
|
|
|
if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
|
2018-03-29 06:30:41 +08:00
|
|
|
chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
|
|
|
|
| PSR2_ADD_VERTICAL_LINE_COUNT);
|
|
|
|
|
|
|
|
else
|
|
|
|
chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
|
2018-11-20 02:00:21 +08:00
|
|
|
I915_WRITE(reg, chicken);
|
2017-09-08 07:00:36 +08:00
|
|
|
}
|
2018-10-04 04:50:25 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
|
|
|
|
* mask LPSP to avoid dependency on other drivers that might block
|
|
|
|
* runtime_pm besides preventing other hw tracking issues now we
|
|
|
|
* can rely on frontbuffer tracking.
|
|
|
|
*/
|
2018-10-04 04:50:26 +08:00
|
|
|
mask = EDP_PSR_DEBUG_MASK_MEMUP |
|
|
|
|
EDP_PSR_DEBUG_MASK_HPD |
|
|
|
|
EDP_PSR_DEBUG_MASK_LPSP |
|
|
|
|
EDP_PSR_DEBUG_MASK_MAX_SLEEP;
|
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) < 11)
|
|
|
|
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
|
|
|
|
|
|
|
|
I915_WRITE(EDP_PSR_DEBUG, mask);
|
2017-09-08 07:00:36 +08:00
|
|
|
}
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = dev_priv->psr.dp;
|
|
|
|
|
|
|
|
if (dev_priv->psr.enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Enabling PSR%s\n",
|
|
|
|
dev_priv->psr.psr2_enabled ? "2" : "1");
|
|
|
|
intel_psr_setup_vsc(intel_dp, crtc_state);
|
|
|
|
intel_psr_enable_sink(intel_dp);
|
|
|
|
intel_psr_enable_source(intel_dp, crtc_state);
|
|
|
|
dev_priv->psr.enabled = true;
|
|
|
|
|
|
|
|
intel_psr_activate(intel_dp);
|
|
|
|
}
|
|
|
|
|
2014-11-15 00:52:29 +08:00
|
|
|
/**
|
|
|
|
* intel_psr_enable - Enable PSR
|
|
|
|
* @intel_dp: Intel DP
|
2017-08-18 21:49:56 +08:00
|
|
|
* @crtc_state: new CRTC state
|
2014-11-15 00:52:29 +08:00
|
|
|
*
|
|
|
|
* This function can only be called after the pipe is fully trained and enabled.
|
|
|
|
*/
|
2017-08-18 21:49:56 +08:00
|
|
|
void intel_psr_enable(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2017-10-12 21:02:01 +08:00
|
|
|
if (!crtc_state->has_psr)
|
2014-11-15 00:52:28 +08:00
|
|
|
return;
|
|
|
|
|
2018-01-04 05:38:24 +08:00
|
|
|
if (WARN_ON(!CAN_PSR(dev_priv)))
|
|
|
|
return;
|
|
|
|
|
2017-09-15 02:16:41 +08:00
|
|
|
WARN_ON(dev_priv->drrs.dp);
|
2018-08-09 22:21:01 +08:00
|
|
|
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
2018-08-09 22:21:01 +08:00
|
|
|
if (dev_priv->psr.prepared) {
|
2014-11-15 00:52:28 +08:00
|
|
|
DRM_DEBUG_KMS("PSR already in use\n");
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
2018-08-08 22:19:11 +08:00
|
|
|
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
|
2014-11-15 00:52:28 +08:00
|
|
|
dev_priv->psr.busy_frontbuffer_bits = 0;
|
2018-08-09 22:21:01 +08:00
|
|
|
dev_priv->psr.prepared = true;
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
if (psr_global_enabled(dev_priv->psr.debug))
|
|
|
|
intel_psr_enable_locked(dev_priv, crtc_state);
|
|
|
|
else
|
|
|
|
DRM_DEBUG_KMS("PSR disabled by flag\n");
|
2015-11-12 03:37:07 +08:00
|
|
|
|
2014-11-15 00:52:28 +08:00
|
|
|
unlock:
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
}
|
|
|
|
|
2018-11-07 03:08:40 +08:00
|
|
|
static void intel_psr_exit(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
2018-11-07 03:08:41 +08:00
|
|
|
if (!dev_priv->psr.active) {
|
|
|
|
if (INTEL_GEN(dev_priv) >= 9)
|
|
|
|
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
|
|
|
|
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
|
2018-11-07 03:08:40 +08:00
|
|
|
return;
|
2018-11-07 03:08:41 +08:00
|
|
|
}
|
2018-11-07 03:08:40 +08:00
|
|
|
|
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
|
|
|
val = I915_READ(EDP_PSR2_CTL);
|
|
|
|
WARN_ON(!(val & EDP_PSR2_ENABLE));
|
|
|
|
I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
|
|
|
|
} else {
|
|
|
|
val = I915_READ(EDP_PSR_CTL);
|
|
|
|
WARN_ON(!(val & EDP_PSR_ENABLE));
|
|
|
|
I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
|
|
|
|
}
|
|
|
|
dev_priv->psr.active = false;
|
|
|
|
}
|
|
|
|
|
2018-11-07 03:08:43 +08:00
|
|
|
static void intel_psr_disable_locked(struct intel_dp *intel_dp)
|
2014-11-19 23:37:00 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2018-11-07 03:08:41 +08:00
|
|
|
i915_reg_t psr_status;
|
|
|
|
u32 psr_status_mask;
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2018-11-07 03:08:43 +08:00
|
|
|
lockdep_assert_held(&dev_priv->psr.lock);
|
|
|
|
|
|
|
|
if (!dev_priv->psr.enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Disabling PSR%s\n",
|
|
|
|
dev_priv->psr.psr2_enabled ? "2" : "1");
|
|
|
|
|
2018-11-07 03:08:41 +08:00
|
|
|
intel_psr_exit(dev_priv);
|
2017-01-16 21:06:22 +08:00
|
|
|
|
2018-11-07 03:08:41 +08:00
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
|
|
|
psr_status = EDP_PSR2_STATUS;
|
|
|
|
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
|
2014-11-15 00:52:28 +08:00
|
|
|
} else {
|
2018-11-07 03:08:41 +08:00
|
|
|
psr_status = EDP_PSR_STATUS;
|
|
|
|
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
2018-11-07 03:08:41 +08:00
|
|
|
|
|
|
|
/* Wait till PSR is idle */
|
|
|
|
if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
|
|
|
|
2000))
|
|
|
|
DRM_ERROR("Timed out waiting PSR idle state\n");
|
2018-06-27 04:16:41 +08:00
|
|
|
|
|
|
|
/* Disable PSR on Sink */
|
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
dev_priv->psr.enabled = false;
|
2018-06-27 04:16:41 +08:00
|
|
|
}
|
|
|
|
|
2014-11-19 23:37:00 +08:00
|
|
|
/**
|
|
|
|
* intel_psr_disable - Disable PSR
|
|
|
|
* @intel_dp: Intel DP
|
2017-08-18 21:49:56 +08:00
|
|
|
* @old_crtc_state: old CRTC state
|
2014-11-19 23:37:00 +08:00
|
|
|
*
|
|
|
|
* This function needs to be called before disabling pipe.
|
|
|
|
*/
|
2017-08-18 21:49:56 +08:00
|
|
|
void intel_psr_disable(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *old_crtc_state)
|
2014-11-19 23:37:00 +08:00
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2014-11-19 23:37:00 +08:00
|
|
|
|
2017-10-12 21:02:01 +08:00
|
|
|
if (!old_crtc_state->has_psr)
|
2017-09-08 07:00:31 +08:00
|
|
|
return;
|
|
|
|
|
2018-01-04 05:38:24 +08:00
|
|
|
if (WARN_ON(!CAN_PSR(dev_priv)))
|
|
|
|
return;
|
|
|
|
|
2014-11-19 23:37:00 +08:00
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
2018-08-09 22:21:01 +08:00
|
|
|
if (!dev_priv->psr.prepared) {
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-06-27 04:16:41 +08:00
|
|
|
intel_psr_disable_locked(intel_dp);
|
2018-08-09 22:21:01 +08:00
|
|
|
|
|
|
|
dev_priv->psr.prepared = false;
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
2018-06-19 06:02:07 +08:00
|
|
|
cancel_work_sync(&dev_priv->psr.work);
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
|
|
|
|
2018-08-25 07:08:44 +08:00
|
|
|
/**
|
|
|
|
* intel_psr_wait_for_idle - wait for PSR1 to idle
|
|
|
|
* @new_crtc_state: new CRTC state
|
|
|
|
* @out_value: PSR status in case of failure
|
|
|
|
*
|
|
|
|
* This function is expected to be called from pipe_update_start() where it is
|
|
|
|
* not expected to race with PSR enable or disable.
|
|
|
|
*
|
|
|
|
* Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
|
|
|
|
*/
|
2018-08-22 06:11:54 +08:00
|
|
|
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
|
|
|
|
u32 *out_value)
|
2018-06-28 04:02:49 +08:00
|
|
|
{
|
2018-07-12 13:33:23 +08:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2018-06-28 04:02:49 +08:00
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
|
2018-07-12 13:33:23 +08:00
|
|
|
return 0;
|
|
|
|
|
2018-08-25 07:08:43 +08:00
|
|
|
/* FIXME: Update this for PSR2 if we need to wait for idle */
|
|
|
|
if (READ_ONCE(dev_priv->psr.psr2_enabled))
|
|
|
|
return 0;
|
2018-06-28 04:02:49 +08:00
|
|
|
|
|
|
|
/*
|
2018-08-25 07:08:44 +08:00
|
|
|
* From bspec: Panel Self Refresh (BDW+)
|
|
|
|
* Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
|
|
|
|
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
|
|
|
|
* defensive enough to cover everything.
|
2018-06-28 04:02:49 +08:00
|
|
|
*/
|
2018-08-22 06:11:54 +08:00
|
|
|
|
2018-08-25 07:08:43 +08:00
|
|
|
return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS,
|
|
|
|
EDP_PSR_STATUS_STATE_MASK,
|
2018-08-22 06:11:54 +08:00
|
|
|
EDP_PSR_STATUS_STATE_IDLE, 2, 50,
|
|
|
|
out_value);
|
2018-06-28 04:02:49 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
2018-04-05 19:49:15 +08:00
|
|
|
i915_reg_t reg;
|
|
|
|
u32 mask;
|
|
|
|
int err;
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
if (!dev_priv->psr.enabled)
|
2018-04-05 19:49:15 +08:00
|
|
|
return false;
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2018-05-12 07:00:59 +08:00
|
|
|
if (dev_priv->psr.psr2_enabled) {
|
|
|
|
reg = EDP_PSR2_STATUS;
|
|
|
|
mask = EDP_PSR2_STATUS_STATE_MASK;
|
2014-11-19 23:37:47 +08:00
|
|
|
} else {
|
2018-05-12 07:00:59 +08:00
|
|
|
reg = EDP_PSR_STATUS;
|
|
|
|
mask = EDP_PSR_STATUS_STATE_MASK;
|
2014-11-15 00:52:28 +08:00
|
|
|
}
|
2018-04-05 19:49:15 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
|
|
|
|
err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
|
|
|
|
if (err)
|
|
|
|
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
|
|
|
|
|
|
|
|
/* After the unlocked wait, verify that PSR is still wanted! */
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
2018-04-05 19:49:15 +08:00
|
|
|
return err == 0 && dev_priv->psr.enabled;
|
|
|
|
}
|
2014-11-15 00:52:28 +08:00
|
|
|
|
2018-08-08 22:19:11 +08:00
|
|
|
static bool switching_psr(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
u32 mode)
|
|
|
|
{
|
|
|
|
/* Can't switch psr state anyway if PSR2 is not supported. */
|
|
|
|
if (!crtc_state || !crtc_state->has_psr2)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (dev_priv->psr.psr2_enabled && mode == I915_PSR_DEBUG_FORCE_PSR1)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (!dev_priv->psr.psr2_enabled && mode != I915_PSR_DEBUG_FORCE_PSR1)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx,
|
|
|
|
u64 val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = &dev_priv->drm;
|
|
|
|
struct drm_connector_state *conn_state;
|
2018-08-08 22:19:11 +08:00
|
|
|
struct intel_crtc_state *crtc_state = NULL;
|
2018-09-05 00:29:02 +08:00
|
|
|
struct drm_crtc_commit *commit;
|
2018-08-09 22:21:01 +08:00
|
|
|
struct drm_crtc *crtc;
|
|
|
|
struct intel_dp *dp;
|
|
|
|
int ret;
|
|
|
|
bool enable;
|
2018-08-08 22:19:11 +08:00
|
|
|
u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
|
2018-08-09 22:21:01 +08:00
|
|
|
|
|
|
|
if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
|
2018-08-08 22:19:11 +08:00
|
|
|
mode > I915_PSR_DEBUG_FORCE_PSR1) {
|
2018-08-09 22:21:01 +08:00
|
|
|
DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = drm_modeset_lock(&dev->mode_config.connection_mutex, ctx);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* dev_priv->psr.dp should be set once and then never touched again. */
|
|
|
|
dp = READ_ONCE(dev_priv->psr.dp);
|
|
|
|
conn_state = dp->attached_connector->base.state;
|
|
|
|
crtc = conn_state->crtc;
|
|
|
|
if (crtc) {
|
|
|
|
ret = drm_modeset_lock(&crtc->mutex, ctx);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2018-08-08 22:19:11 +08:00
|
|
|
crtc_state = to_intel_crtc_state(crtc->state);
|
2018-09-05 00:29:02 +08:00
|
|
|
commit = crtc_state->base.commit;
|
|
|
|
} else {
|
|
|
|
commit = conn_state->commit;
|
|
|
|
}
|
|
|
|
if (commit) {
|
|
|
|
ret = wait_for_completion_interruptible(&commit->hw_done);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2018-08-09 22:21:01 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev_priv->psr.lock);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
enable = psr_global_enabled(val);
|
|
|
|
|
2018-08-08 22:19:11 +08:00
|
|
|
if (!enable || switching_psr(dev_priv, crtc_state, mode))
|
2018-08-09 22:21:01 +08:00
|
|
|
intel_psr_disable_locked(dev_priv->psr.dp);
|
|
|
|
|
|
|
|
dev_priv->psr.debug = val;
|
2018-08-08 22:19:11 +08:00
|
|
|
if (crtc)
|
|
|
|
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
|
|
|
|
|
2018-08-22 06:11:56 +08:00
|
|
|
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
|
2018-08-09 22:21:01 +08:00
|
|
|
|
|
|
|
if (dev_priv->psr.prepared && enable)
|
2018-08-08 22:19:11 +08:00
|
|
|
intel_psr_enable_locked(dev_priv, crtc_state);
|
2018-08-09 22:21:01 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-11-22 06:54:39 +08:00
|
|
|
static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_psr *psr = &dev_priv->psr;
|
|
|
|
|
|
|
|
intel_psr_disable_locked(psr->dp);
|
|
|
|
psr->sink_not_reliable = true;
|
|
|
|
/* let's make sure that sink is awaken */
|
|
|
|
drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
|
|
|
|
}
|
|
|
|
|
2018-04-05 19:49:15 +08:00
|
|
|
static void intel_psr_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv =
|
2018-06-14 03:26:00 +08:00
|
|
|
container_of(work, typeof(*dev_priv), psr.work);
|
2018-04-05 19:49:15 +08:00
|
|
|
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
|
2018-06-14 03:26:00 +08:00
|
|
|
if (!dev_priv->psr.enabled)
|
|
|
|
goto unlock;
|
|
|
|
|
2018-11-22 06:54:39 +08:00
|
|
|
if (READ_ONCE(dev_priv->psr.irq_aux_error))
|
|
|
|
intel_psr_handle_irq(dev_priv);
|
|
|
|
|
2018-04-05 19:49:15 +08:00
|
|
|
/*
|
|
|
|
* We have to make sure PSR is ready for re-enable
|
|
|
|
* otherwise it keeps disabled until next full enable/disable cycle.
|
|
|
|
* PSR might take some time to get fully disabled
|
|
|
|
* and be ready for re-enable.
|
|
|
|
*/
|
2018-06-28 04:02:49 +08:00
|
|
|
if (!__psr_wait_for_idle_locked(dev_priv))
|
2014-11-15 00:52:28 +08:00
|
|
|
goto unlock;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The delayed work can race with an invalidate hence we need to
|
|
|
|
* recheck. Since psr_flush first clears this and then reschedules we
|
|
|
|
* won't ever miss a flush when bailing out here.
|
|
|
|
*/
|
2018-06-25 13:47:40 +08:00
|
|
|
if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
|
2014-11-15 00:52:28 +08:00
|
|
|
goto unlock;
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
intel_psr_activate(dev_priv->psr.dp);
|
2014-11-15 00:52:28 +08:00
|
|
|
unlock:
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
}
|
|
|
|
|
2014-11-15 00:52:29 +08:00
|
|
|
/**
|
|
|
|
* intel_psr_invalidate - Invalidade PSR
|
2016-08-04 23:32:38 +08:00
|
|
|
* @dev_priv: i915 device
|
2014-11-15 00:52:29 +08:00
|
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
2018-03-07 11:34:20 +08:00
|
|
|
* @origin: which operation caused the invalidate
|
2014-11-15 00:52:29 +08:00
|
|
|
*
|
|
|
|
* Since the hardware frontbuffer tracking has gaps we need to integrate
|
|
|
|
* with the software frontbuffer tracking. This function gets called every
|
|
|
|
* time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
|
|
|
|
* disabled if the frontbuffer mask contains a buffer relevant to PSR.
|
|
|
|
*
|
|
|
|
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
|
|
|
|
*/
|
2016-08-04 23:32:38 +08:00
|
|
|
void intel_psr_invalidate(struct drm_i915_private *dev_priv,
|
2018-03-07 11:34:20 +08:00
|
|
|
unsigned frontbuffer_bits, enum fb_op_origin origin)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
|
|
|
struct drm_crtc *crtc;
|
|
|
|
enum pipe pipe;
|
|
|
|
|
2018-01-04 05:38:23 +08:00
|
|
|
if (!CAN_PSR(dev_priv))
|
2017-09-08 07:00:31 +08:00
|
|
|
return;
|
|
|
|
|
2018-05-12 07:00:59 +08:00
|
|
|
if (origin == ORIGIN_FLIP)
|
2018-03-07 11:34:20 +08:00
|
|
|
return;
|
|
|
|
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
if (!dev_priv->psr.enabled) {
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
|
2014-11-15 00:52:28 +08:00
|
|
|
pipe = to_intel_crtc(crtc)->pipe;
|
|
|
|
|
|
|
|
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
|
|
|
|
dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
|
2015-06-18 16:30:26 +08:00
|
|
|
|
|
|
|
if (frontbuffer_bits)
|
2016-08-04 23:32:38 +08:00
|
|
|
intel_psr_exit(dev_priv);
|
2015-06-18 16:30:26 +08:00
|
|
|
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
}
|
|
|
|
|
2014-11-15 00:52:29 +08:00
|
|
|
/**
|
|
|
|
* intel_psr_flush - Flush PSR
|
2016-08-04 23:32:38 +08:00
|
|
|
* @dev_priv: i915 device
|
2014-11-15 00:52:29 +08:00
|
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
2015-07-09 07:21:31 +08:00
|
|
|
* @origin: which operation caused the flush
|
2014-11-15 00:52:29 +08:00
|
|
|
*
|
|
|
|
* Since the hardware frontbuffer tracking has gaps we need to integrate
|
|
|
|
* with the software frontbuffer tracking. This function gets called every
|
|
|
|
* time frontbuffer rendering has completed and flushed out to memory. PSR
|
|
|
|
* can be enabled again if no other frontbuffer relevant to PSR is dirty.
|
|
|
|
*
|
|
|
|
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
|
|
|
|
*/
|
2016-08-04 23:32:38 +08:00
|
|
|
void intel_psr_flush(struct drm_i915_private *dev_priv,
|
2015-07-09 07:21:31 +08:00
|
|
|
unsigned frontbuffer_bits, enum fb_op_origin origin)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
|
|
|
struct drm_crtc *crtc;
|
|
|
|
enum pipe pipe;
|
|
|
|
|
2018-01-04 05:38:23 +08:00
|
|
|
if (!CAN_PSR(dev_priv))
|
2017-09-08 07:00:31 +08:00
|
|
|
return;
|
|
|
|
|
2018-05-12 07:00:59 +08:00
|
|
|
if (origin == ORIGIN_FLIP)
|
2018-03-07 11:34:20 +08:00
|
|
|
return;
|
|
|
|
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
if (!dev_priv->psr.enabled) {
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc;
|
2014-11-15 00:52:28 +08:00
|
|
|
pipe = to_intel_crtc(crtc)->pipe;
|
2015-06-18 16:30:26 +08:00
|
|
|
|
|
|
|
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
|
2014-11-15 00:52:28 +08:00
|
|
|
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
|
|
|
|
|
2015-11-19 03:21:12 +08:00
|
|
|
/* By definition flush = invalidate + flush */
|
2018-03-09 08:52:18 +08:00
|
|
|
if (frontbuffer_bits) {
|
2018-10-04 04:50:28 +08:00
|
|
|
/*
|
|
|
|
* Display WA #0884: all
|
|
|
|
* This documented WA for bxt can be safely applied
|
|
|
|
* broadly so we can force HW tracking to exit PSR
|
|
|
|
* instead of disabling and re-enabling.
|
|
|
|
* Workaround tells us to write 0 to CUR_SURFLIVE_A,
|
|
|
|
* but it makes more sense write to the current active
|
|
|
|
* pipe.
|
|
|
|
*/
|
|
|
|
I915_WRITE(CURSURFLIVE(pipe), 0);
|
2018-03-09 08:52:18 +08:00
|
|
|
}
|
2014-11-19 23:37:47 +08:00
|
|
|
|
2014-11-15 00:52:28 +08:00
|
|
|
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
|
2018-06-14 03:26:00 +08:00
|
|
|
schedule_work(&dev_priv->psr.work);
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
}
|
|
|
|
|
2014-11-15 00:52:29 +08:00
|
|
|
/**
|
|
|
|
* intel_psr_init - Init basic PSR work and mutex.
|
2016-11-29 19:48:47 +08:00
|
|
|
* @dev_priv: i915 device private
|
2014-11-15 00:52:29 +08:00
|
|
|
*
|
|
|
|
* This function is called only once at driver load to initialize basic
|
|
|
|
* PSR stuff.
|
|
|
|
*/
|
2016-11-23 22:21:44 +08:00
|
|
|
void intel_psr_init(struct drm_i915_private *dev_priv)
|
2014-11-15 00:52:28 +08:00
|
|
|
{
|
2017-09-08 07:00:31 +08:00
|
|
|
if (!HAS_PSR(dev_priv))
|
|
|
|
return;
|
|
|
|
|
2015-11-12 02:34:15 +08:00
|
|
|
dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
|
|
|
|
HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
|
|
|
|
|
2018-01-04 05:38:24 +08:00
|
|
|
if (!dev_priv->psr.sink_support)
|
|
|
|
return;
|
|
|
|
|
2018-09-28 14:11:17 +08:00
|
|
|
if (i915_modparams.enable_psr == -1)
|
|
|
|
if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
|
|
|
|
i915_modparams.enable_psr = 0;
|
2016-02-12 20:08:11 +08:00
|
|
|
|
2016-02-02 04:02:08 +08:00
|
|
|
/* Set link_standby x link_off defaults */
|
2016-10-13 18:03:00 +08:00
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
2016-02-02 04:02:07 +08:00
|
|
|
/* HSW and BDW require workarounds that we don't implement. */
|
|
|
|
dev_priv->psr.link_standby = false;
|
|
|
|
else
|
|
|
|
/* For new platforms let's respect VBT back again */
|
|
|
|
dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
|
|
|
|
|
2018-06-14 03:26:00 +08:00
|
|
|
INIT_WORK(&dev_priv->psr.work, intel_psr_work);
|
2014-11-15 00:52:28 +08:00
|
|
|
mutex_init(&dev_priv->psr.lock);
|
|
|
|
}
|
2018-06-27 04:16:41 +08:00
|
|
|
|
|
|
|
void intel_psr_short_pulse(struct intel_dp *intel_dp)
|
|
|
|
{
|
2018-08-28 06:30:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
2018-06-27 04:16:41 +08:00
|
|
|
struct i915_psr *psr = &dev_priv->psr;
|
|
|
|
u8 val;
|
2018-06-27 04:16:42 +08:00
|
|
|
const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
|
2018-06-27 04:16:44 +08:00
|
|
|
DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
|
|
|
|
DP_PSR_LINK_CRC_ERROR;
|
2018-06-27 04:16:41 +08:00
|
|
|
|
|
|
|
if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
|
|
|
|
return;
|
|
|
|
|
|
|
|
mutex_lock(&psr->lock);
|
|
|
|
|
2018-08-09 22:21:01 +08:00
|
|
|
if (!psr->enabled || psr->dp != intel_dp)
|
2018-06-27 04:16:41 +08:00
|
|
|
goto exit;
|
|
|
|
|
|
|
|
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) {
|
|
|
|
DRM_ERROR("PSR_STATUS dpcd read failed\n");
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
|
|
|
|
DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
|
|
|
|
intel_psr_disable_locked(intel_dp);
|
2018-11-22 06:54:38 +08:00
|
|
|
psr->sink_not_reliable = true;
|
2018-06-27 04:16:41 +08:00
|
|
|
}
|
|
|
|
|
2018-06-27 04:16:42 +08:00
|
|
|
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
|
|
|
|
DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n");
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (val & DP_PSR_RFB_STORAGE_ERROR)
|
|
|
|
DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
|
|
|
|
if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
|
|
|
|
DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
|
2018-06-27 04:16:44 +08:00
|
|
|
if (val & DP_PSR_LINK_CRC_ERROR)
|
|
|
|
DRM_ERROR("PSR Link CRC error, disabling PSR\n");
|
2018-06-27 04:16:42 +08:00
|
|
|
|
|
|
|
if (val & ~errors)
|
|
|
|
DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
|
|
|
|
val & ~errors);
|
2018-11-22 06:54:38 +08:00
|
|
|
if (val & errors) {
|
2018-06-27 04:16:42 +08:00
|
|
|
intel_psr_disable_locked(intel_dp);
|
2018-11-22 06:54:38 +08:00
|
|
|
psr->sink_not_reliable = true;
|
|
|
|
}
|
2018-06-27 04:16:42 +08:00
|
|
|
/* clear status register */
|
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
|
2018-06-27 04:16:41 +08:00
|
|
|
exit:
|
|
|
|
mutex_unlock(&psr->lock);
|
|
|
|
}
|
2018-11-22 06:54:37 +08:00
|
|
|
|
|
|
|
bool intel_psr_enabled(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
|
|
ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|