2020-03-28 18:04:46 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/**
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* debug.h - DesignWare USB3 DRD Controller Debug Header
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*
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2020-07-11 21:58:04 +08:00
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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2014-08-20 05:37:22 +08:00
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#ifndef __DWC3_DEBUG_H
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#define __DWC3_DEBUG_H
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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#include "core.h"
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2014-08-20 05:37:22 +08:00
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/**
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* dwc3_gadget_ep_cmd_string - returns endpoint command string
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* @cmd: command code
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*/
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static inline const char *
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dwc3_gadget_ep_cmd_string(u8 cmd)
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{
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switch (cmd) {
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case DWC3_DEPCMD_DEPSTARTCFG:
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return "Start New Configuration";
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case DWC3_DEPCMD_ENDTRANSFER:
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return "End Transfer";
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case DWC3_DEPCMD_UPDATETRANSFER:
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return "Update Transfer";
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case DWC3_DEPCMD_STARTTRANSFER:
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return "Start Transfer";
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case DWC3_DEPCMD_CLEARSTALL:
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return "Clear Stall";
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case DWC3_DEPCMD_SETSTALL:
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return "Set Stall";
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case DWC3_DEPCMD_GETEPSTATE:
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return "Get Endpoint State";
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case DWC3_DEPCMD_SETTRANSFRESOURCE:
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return "Set Endpoint Transfer Resource";
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case DWC3_DEPCMD_SETEPCONFIG:
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return "Set Endpoint Configuration";
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default:
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return "UNKNOWN command";
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}
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}
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/**
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* dwc3_gadget_generic_cmd_string - returns generic command string
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* @cmd: command code
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*/
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static inline const char *
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dwc3_gadget_generic_cmd_string(u8 cmd)
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{
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switch (cmd) {
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case DWC3_DGCMD_SET_LMP:
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return "Set LMP";
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case DWC3_DGCMD_SET_PERIODIC_PAR:
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return "Set Periodic Parameters";
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case DWC3_DGCMD_XMIT_FUNCTION:
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return "Transmit Function Wake Device Notification";
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case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO:
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return "Set Scratchpad Buffer Array Address Lo";
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case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI:
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return "Set Scratchpad Buffer Array Address Hi";
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case DWC3_DGCMD_SELECTED_FIFO_FLUSH:
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return "Selected FIFO Flush";
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case DWC3_DGCMD_ALL_FIFO_FLUSH:
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return "All FIFO Flush";
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case DWC3_DGCMD_SET_ENDPOINT_NRDY:
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return "Set Endpoint NRDY";
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2020-05-06 10:47:09 +08:00
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case DWC3_DGCMD_SET_ENDPOINT_PRIME:
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return "Set Endpoint Prime";
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2014-08-20 05:37:22 +08:00
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case DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK:
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return "Run SoC Bus Loopback Test";
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default:
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return "UNKNOWN";
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}
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}
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/**
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* dwc3_gadget_link_string - returns link name
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* @link_state: link state code
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*/
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static inline const char *
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dwc3_gadget_link_string(enum dwc3_link_state link_state)
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{
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switch (link_state) {
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case DWC3_LINK_STATE_U0:
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return "U0";
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case DWC3_LINK_STATE_U1:
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return "U1";
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case DWC3_LINK_STATE_U2:
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return "U2";
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case DWC3_LINK_STATE_U3:
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return "U3";
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case DWC3_LINK_STATE_SS_DIS:
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return "SS.Disabled";
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case DWC3_LINK_STATE_RX_DET:
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return "RX.Detect";
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case DWC3_LINK_STATE_SS_INACT:
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return "SS.Inactive";
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case DWC3_LINK_STATE_POLL:
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return "Polling";
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case DWC3_LINK_STATE_RECOV:
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return "Recovery";
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case DWC3_LINK_STATE_HRESET:
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return "Hot Reset";
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case DWC3_LINK_STATE_CMPLY:
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return "Compliance";
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case DWC3_LINK_STATE_LPBK:
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return "Loopback";
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case DWC3_LINK_STATE_RESET:
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return "Reset";
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case DWC3_LINK_STATE_RESUME:
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return "Resume";
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default:
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2019-10-23 03:10:16 +08:00
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return "UNKNOWN link state";
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2014-08-20 05:37:22 +08:00
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}
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}
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2018-11-08 09:55:19 +08:00
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/**
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* dwc3_gadget_hs_link_string - returns highspeed and below link name
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* @link_state: link state code
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*/
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static inline const char *
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dwc3_gadget_hs_link_string(enum dwc3_link_state link_state)
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{
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switch (link_state) {
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case DWC3_LINK_STATE_U0:
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return "On";
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case DWC3_LINK_STATE_U2:
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return "Sleep";
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case DWC3_LINK_STATE_U3:
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return "Suspend";
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case DWC3_LINK_STATE_SS_DIS:
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return "Disconnected";
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case DWC3_LINK_STATE_RX_DET:
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return "Early Suspend";
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case DWC3_LINK_STATE_RECOV:
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return "Recovery";
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case DWC3_LINK_STATE_RESET:
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return "Reset";
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case DWC3_LINK_STATE_RESUME:
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return "Resume";
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default:
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2019-10-23 03:10:16 +08:00
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return "UNKNOWN link state";
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2018-11-08 09:55:19 +08:00
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}
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}
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2017-03-31 19:44:09 +08:00
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/**
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* dwc3_trb_type_string - returns TRB type as a string
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* @type: the type of the TRB
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*/
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static inline const char *dwc3_trb_type_string(unsigned int type)
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{
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switch (type) {
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case DWC3_TRBCTL_NORMAL:
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return "normal";
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case DWC3_TRBCTL_CONTROL_SETUP:
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return "setup";
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case DWC3_TRBCTL_CONTROL_STATUS2:
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return "status2";
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case DWC3_TRBCTL_CONTROL_STATUS3:
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return "status3";
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case DWC3_TRBCTL_CONTROL_DATA:
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return "data";
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case DWC3_TRBCTL_ISOCHRONOUS_FIRST:
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return "isoc-first";
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case DWC3_TRBCTL_ISOCHRONOUS:
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return "isoc";
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case DWC3_TRBCTL_LINK_TRB:
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return "link";
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default:
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return "UNKNOWN";
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}
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}
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2016-09-26 18:22:21 +08:00
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static inline const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
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{
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switch (state) {
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case EP0_UNCONNECTED:
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return "Unconnected";
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case EP0_SETUP_PHASE:
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return "Setup Phase";
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case EP0_DATA_PHASE:
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return "Data Phase";
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case EP0_STATUS_PHASE:
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return "Status Phase";
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default:
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return "UNKNOWN";
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}
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}
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2014-08-20 05:37:22 +08:00
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/**
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* dwc3_gadget_event_string - returns event name
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* @event: the event code
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*/
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2019-02-04 21:43:38 +08:00
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static inline const char *dwc3_gadget_event_string(char *str, size_t size,
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const struct dwc3_event_devt *event)
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2014-08-20 05:37:22 +08:00
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{
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2016-05-23 16:10:08 +08:00
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enum dwc3_link_state state = event->event_info & DWC3_LINK_STATE_MASK;
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switch (event->type) {
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_DISCONNECT:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Disconnect: [%s]",
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2016-05-23 16:10:08 +08:00
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_RESET:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Reset [%s]",
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dwc3_gadget_link_string(state));
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2016-05-23 16:10:08 +08:00
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_CONNECT_DONE:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Connection Done [%s]",
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2016-05-23 16:10:08 +08:00
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Link Change [%s]",
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2016-05-23 16:10:08 +08:00
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_WAKEUP:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "WakeUp [%s]",
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dwc3_gadget_link_string(state));
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2016-05-23 16:10:08 +08:00
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_EOPF:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "End-Of-Frame [%s]",
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2016-05-23 16:10:08 +08:00
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_SOF:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Start-Of-Frame [%s]",
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2016-05-23 16:10:08 +08:00
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Erratic Error [%s]",
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2016-05-23 16:10:08 +08:00
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_CMD_CMPL:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Command Complete [%s]",
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2016-05-23 16:10:08 +08:00
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dwc3_gadget_link_string(state));
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break;
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2014-08-20 05:37:22 +08:00
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case DWC3_DEVICE_EVENT_OVERFLOW:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "Overflow [%s]",
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dwc3_gadget_link_string(state));
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2016-05-23 16:10:08 +08:00
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break;
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default:
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2019-02-04 21:43:38 +08:00
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snprintf(str, size, "UNKNOWN");
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2014-08-20 05:37:22 +08:00
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}
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2016-05-23 16:10:08 +08:00
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return str;
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2014-08-20 05:37:22 +08:00
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}
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/**
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* dwc3_ep_event_string - returns event name
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* @event: then event code
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*/
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2019-02-04 21:43:38 +08:00
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static inline const char *dwc3_ep_event_string(char *str, size_t size,
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const struct dwc3_event_depevt *event, u32 ep0state)
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2014-08-20 05:37:22 +08:00
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{
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2016-05-23 16:10:08 +08:00
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u8 epnum = event->endpoint_number;
|
2016-09-26 18:23:34 +08:00
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|
|
size_t len;
|
2016-05-23 16:10:08 +08:00
|
|
|
int status;
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|
|
|
2020-02-10 17:51:39 +08:00
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|
|
len = scnprintf(str, size, "ep%d%s: ", epnum >> 1,
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2016-08-24 19:32:39 +08:00
|
|
|
(epnum & 1) ? "in" : "out");
|
2016-05-23 16:10:08 +08:00
|
|
|
|
2018-04-06 16:03:19 +08:00
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|
|
status = event->status;
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|
|
|
|
2016-05-23 16:10:08 +08:00
|
|
|
switch (event->endpoint_event) {
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_XFERCOMPLETE:
|
2020-02-10 17:51:39 +08:00
|
|
|
len += scnprintf(str + len, size - len,
|
|
|
|
"Transfer Complete (%c%c%c)",
|
2018-04-06 16:03:19 +08:00
|
|
|
status & DEPEVT_STATUS_SHORT ? 'S' : 's',
|
|
|
|
status & DEPEVT_STATUS_IOC ? 'I' : 'i',
|
|
|
|
status & DEPEVT_STATUS_LST ? 'L' : 'l');
|
|
|
|
|
2016-09-26 18:23:34 +08:00
|
|
|
if (epnum <= 1)
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len, " [%s]",
|
2019-02-04 21:43:38 +08:00
|
|
|
dwc3_ep0_state_string(ep0state));
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_XFERINPROGRESS:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len,
|
|
|
|
"Transfer In Progress [%d] (%c%c%c)",
|
2018-04-11 15:31:53 +08:00
|
|
|
event->parameters,
|
2018-04-06 16:03:19 +08:00
|
|
|
status & DEPEVT_STATUS_SHORT ? 'S' : 's',
|
|
|
|
status & DEPEVT_STATUS_IOC ? 'I' : 'i',
|
|
|
|
status & DEPEVT_STATUS_LST ? 'M' : 'm');
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_XFERNOTREADY:
|
2020-02-10 17:51:39 +08:00
|
|
|
len += scnprintf(str + len, size - len,
|
|
|
|
"Transfer Not Ready [%d]%s",
|
2018-04-11 15:31:53 +08:00
|
|
|
event->parameters,
|
|
|
|
status & DEPEVT_STATUS_TRANSFER_ACTIVE ?
|
2018-04-06 16:03:19 +08:00
|
|
|
" (Active)" : " (Not Active)");
|
2016-09-26 17:54:04 +08:00
|
|
|
|
|
|
|
/* Control Endpoints */
|
|
|
|
if (epnum <= 1) {
|
|
|
|
int phase = DEPEVT_STATUS_CONTROL_PHASE(event->status);
|
|
|
|
|
|
|
|
switch (phase) {
|
|
|
|
case DEPEVT_STATUS_CONTROL_DATA:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len,
|
2019-02-05 15:00:14 +08:00
|
|
|
" [Data Phase]");
|
2016-09-26 17:54:04 +08:00
|
|
|
break;
|
|
|
|
case DEPEVT_STATUS_CONTROL_STATUS:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len,
|
2019-02-05 15:00:14 +08:00
|
|
|
" [Status Phase]");
|
2016-09-26 17:54:04 +08:00
|
|
|
}
|
|
|
|
}
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_RXTXFIFOEVT:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len, "FIFO");
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_STREAMEVT:
|
2016-05-23 16:10:08 +08:00
|
|
|
status = event->status;
|
|
|
|
|
|
|
|
switch (status) {
|
|
|
|
case DEPEVT_STREAMEVT_FOUND:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len, " Stream %d Found",
|
2016-05-23 16:10:08 +08:00
|
|
|
event->parameters);
|
|
|
|
break;
|
|
|
|
case DEPEVT_STREAMEVT_NOTFOUND:
|
|
|
|
default:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len, " Stream Not Found");
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
2014-08-20 05:37:22 +08:00
|
|
|
case DWC3_DEPEVT_EPCMDCMPLT:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len, "Endpoint Command Complete");
|
2016-05-23 16:10:08 +08:00
|
|
|
break;
|
|
|
|
default:
|
2020-02-10 17:51:39 +08:00
|
|
|
scnprintf(str + len, size - len, "UNKNOWN");
|
2014-08-20 05:37:22 +08:00
|
|
|
}
|
|
|
|
|
2016-05-23 16:10:08 +08:00
|
|
|
return str;
|
2014-08-20 05:37:22 +08:00
|
|
|
}
|
|
|
|
|
2014-08-20 05:49:20 +08:00
|
|
|
/**
|
|
|
|
* dwc3_gadget_event_type_string - return event name
|
|
|
|
* @event: the event code
|
|
|
|
*/
|
|
|
|
static inline const char *dwc3_gadget_event_type_string(u8 event)
|
|
|
|
{
|
|
|
|
switch (event) {
|
|
|
|
case DWC3_DEVICE_EVENT_DISCONNECT:
|
|
|
|
return "Disconnect";
|
|
|
|
case DWC3_DEVICE_EVENT_RESET:
|
|
|
|
return "Reset";
|
|
|
|
case DWC3_DEVICE_EVENT_CONNECT_DONE:
|
|
|
|
return "Connect Done";
|
|
|
|
case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
|
|
|
|
return "Link Status Change";
|
|
|
|
case DWC3_DEVICE_EVENT_WAKEUP:
|
|
|
|
return "Wake-Up";
|
|
|
|
case DWC3_DEVICE_EVENT_HIBER_REQ:
|
|
|
|
return "Hibernation";
|
|
|
|
case DWC3_DEVICE_EVENT_EOPF:
|
|
|
|
return "End of Periodic Frame";
|
|
|
|
case DWC3_DEVICE_EVENT_SOF:
|
|
|
|
return "Start of Frame";
|
|
|
|
case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
|
|
|
|
return "Erratic Error";
|
|
|
|
case DWC3_DEVICE_EVENT_CMD_CMPL:
|
|
|
|
return "Command Complete";
|
|
|
|
case DWC3_DEVICE_EVENT_OVERFLOW:
|
|
|
|
return "Overflow";
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-02-04 21:43:38 +08:00
|
|
|
static inline const char *dwc3_decode_event(char *str, size_t size, u32 event,
|
|
|
|
u32 ep0state)
|
2016-05-23 16:10:08 +08:00
|
|
|
{
|
2020-08-13 13:24:21 +08:00
|
|
|
union dwc3_event evt;
|
|
|
|
|
|
|
|
memcpy(&evt, &event, sizeof(event));
|
2016-05-23 16:10:08 +08:00
|
|
|
|
|
|
|
if (evt.type.is_devspec)
|
2019-02-04 21:43:38 +08:00
|
|
|
return dwc3_gadget_event_string(str, size, &evt.devt);
|
2016-05-23 16:10:08 +08:00
|
|
|
else
|
2019-02-04 21:43:38 +08:00
|
|
|
return dwc3_ep_event_string(str, size, &evt.depevt, ep0state);
|
2016-05-23 16:10:08 +08:00
|
|
|
}
|
|
|
|
|
2016-05-23 19:02:33 +08:00
|
|
|
static inline const char *dwc3_ep_cmd_status_string(int status)
|
|
|
|
{
|
|
|
|
switch (status) {
|
|
|
|
case -ETIMEDOUT:
|
|
|
|
return "Timed Out";
|
|
|
|
case 0:
|
|
|
|
return "Successful";
|
|
|
|
case DEPEVT_TRANSFER_NO_RESOURCE:
|
|
|
|
return "No Resource";
|
|
|
|
case DEPEVT_TRANSFER_BUS_EXPIRY:
|
|
|
|
return "Bus Expiry";
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-23 19:16:19 +08:00
|
|
|
static inline const char *dwc3_gadget_generic_cmd_status_string(int status)
|
|
|
|
{
|
|
|
|
switch (status) {
|
|
|
|
case -ETIMEDOUT:
|
|
|
|
return "Timed Out";
|
|
|
|
case 0:
|
|
|
|
return "Successful";
|
|
|
|
case 1:
|
|
|
|
return "Error";
|
|
|
|
default:
|
|
|
|
return "UNKNOWN";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-09-30 19:12:34 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
2020-08-13 13:33:05 +08:00
|
|
|
extern void dwc3_debugfs_init(struct dwc3 *d);
|
|
|
|
extern void dwc3_debugfs_exit(struct dwc3 *d);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#else
|
2016-04-12 19:10:18 +08:00
|
|
|
static inline void dwc3_debugfs_init(struct dwc3 *d)
|
|
|
|
{ }
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
static inline void dwc3_debugfs_exit(struct dwc3 *d)
|
|
|
|
{ }
|
|
|
|
#endif
|
2014-08-20 05:37:22 +08:00
|
|
|
#endif /* __DWC3_DEBUG_H */
|