889 lines
20 KiB
C
889 lines
20 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Lightning Mountain SoC LED Serial Shift Output Controller driver
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*
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* Copyright (c) 2020 Intel Corporation.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/leds.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/sizes.h>
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#include <linux/uaccess.h>
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#define SSO_DEV_NAME "lgm-sso"
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#define LED_BLINK_H8_0 0x0
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#define LED_BLINK_H8_1 0x4
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#define GET_FREQ_OFFSET(pin, src) (((pin) * 6) + ((src) * 2))
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#define GET_SRC_OFFSET(pinc) (((pin) * 6) + 4)
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#define DUTY_CYCLE(x) (0x8 + ((x) * 4))
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#define SSO_CON0 0x2B0
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#define SSO_CON0_RZFL BIT(26)
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#define SSO_CON0_BLINK_R BIT(30)
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#define SSO_CON0_SWU BIT(31)
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#define SSO_CON1 0x2B4
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#define SSO_CON1_FCDSC GENMASK(21, 20) /* Fixed Divider Shift Clock */
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#define SSO_CON1_FPID GENMASK(24, 23)
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#define SSO_CON1_GPTD GENMASK(26, 25)
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#define SSO_CON1_US GENMASK(31, 30)
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#define SSO_CPU 0x2B8
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#define SSO_CON2 0x2C4
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#define SSO_CON3 0x2C8
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/* Driver MACRO */
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#define MAX_PIN_NUM_PER_BANK SZ_32
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#define MAX_GROUP_NUM SZ_4
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#define PINS_PER_GROUP SZ_8
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#define FPID_FREQ_RANK_MAX SZ_4
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#define SSO_LED_MAX_NUM SZ_32
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#define MAX_FREQ_RANK 10
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#define DEF_GPTC_CLK_RATE 200000000
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#define SSO_DEF_BRIGHTNESS LED_HALF
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#define DATA_CLK_EDGE 0 /* 0-rising, 1-falling */
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static const u32 freq_div_tbl[] = {4000, 2000, 1000, 800};
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static const int freq_tbl[] = {2, 4, 8, 10, 50000, 100000, 200000, 250000};
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static const int shift_clk_freq_tbl[] = {25000000, 12500000, 6250000, 3125000};
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/*
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* Update Source to update the SOUTs
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* SW - Software has to update the SWU bit
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* GPTC - General Purpose timer is used as clock source
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* FPID - Divided FSC clock (FPID) is used as clock source
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*/
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enum {
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US_SW = 0,
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US_GPTC = 1,
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US_FPID = 2
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};
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enum {
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MAX_FPID_FREQ_RANK = 5, /* 1 to 4 */
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MAX_GPTC_FREQ_RANK = 9, /* 5 to 8 */
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MAX_GPTC_HS_FREQ_RANK = 10, /* 9 to 10 */
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};
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enum {
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LED_GRP0_PIN_MAX = 24,
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LED_GRP1_PIN_MAX = 29,
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LED_GRP2_PIN_MAX = 32,
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};
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enum {
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LED_GRP0_0_23,
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LED_GRP1_24_28,
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LED_GRP2_29_31,
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LED_GROUP_MAX,
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};
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enum {
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CLK_SRC_FPID = 0,
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CLK_SRC_GPTC = 1,
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CLK_SRC_GPTC_HS = 2,
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};
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struct sso_led_priv;
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struct sso_led_desc {
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const char *name;
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const char *default_trigger;
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unsigned int brightness;
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unsigned int blink_rate;
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unsigned int retain_state_suspended:1;
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unsigned int retain_state_shutdown:1;
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unsigned int panic_indicator:1;
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unsigned int hw_blink:1;
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unsigned int hw_trig:1;
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unsigned int blinking:1;
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int freq_idx;
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u32 pin;
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};
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struct sso_led {
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struct list_head list;
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struct led_classdev cdev;
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struct gpio_desc *gpiod;
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struct sso_led_desc desc;
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struct sso_led_priv *priv;
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};
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struct sso_gpio {
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struct gpio_chip chip;
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int shift_clk_freq;
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int edge;
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int freq;
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u32 pins;
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u32 alloc_bitmap;
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};
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struct sso_led_priv {
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struct regmap *mmap;
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struct device *dev;
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struct platform_device *pdev;
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struct clk *gclk;
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struct clk *fpid_clk;
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u32 fpid_clkrate;
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u32 gptc_clkrate;
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u32 freq[MAX_FREQ_RANK];
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struct list_head led_list;
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struct sso_gpio gpio;
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};
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static int sso_get_blink_rate_idx(struct sso_led_priv *priv, u32 rate)
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{
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int i;
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for (i = 0; i < MAX_FREQ_RANK; i++) {
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if (rate <= priv->freq[i])
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return i;
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}
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return -1;
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}
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static unsigned int sso_led_pin_to_group(u32 pin)
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{
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if (pin < LED_GRP0_PIN_MAX)
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return LED_GRP0_0_23;
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else if (pin < LED_GRP1_PIN_MAX)
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return LED_GRP1_24_28;
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else
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return LED_GRP2_29_31;
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}
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static u32 sso_led_get_freq_src(int freq_idx)
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{
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if (freq_idx < MAX_FPID_FREQ_RANK)
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return CLK_SRC_FPID;
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else if (freq_idx < MAX_GPTC_FREQ_RANK)
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return CLK_SRC_GPTC;
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else
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return CLK_SRC_GPTC_HS;
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}
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static u32 sso_led_pin_blink_off(u32 pin, unsigned int group)
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{
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if (group == LED_GRP2_29_31)
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return pin - LED_GRP1_PIN_MAX;
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else if (group == LED_GRP1_24_28)
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return pin - LED_GRP0_PIN_MAX;
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else /* led 0 - 23 in led 32 location */
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return SSO_LED_MAX_NUM - LED_GRP1_PIN_MAX;
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}
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static struct sso_led
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*cdev_to_sso_led_data(struct led_classdev *led_cdev)
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{
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return container_of(led_cdev, struct sso_led, cdev);
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}
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static void sso_led_freq_set(struct sso_led_priv *priv, u32 pin, int freq_idx)
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{
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u32 reg, off, freq_src, val_freq;
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u32 low, high, val;
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unsigned int group;
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if (!freq_idx)
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return;
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group = sso_led_pin_to_group(pin);
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freq_src = sso_led_get_freq_src(freq_idx);
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off = sso_led_pin_blink_off(pin, group);
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if (group == LED_GRP0_0_23)
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return;
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else if (group == LED_GRP1_24_28)
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reg = LED_BLINK_H8_0;
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else
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reg = LED_BLINK_H8_1;
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if (freq_src == CLK_SRC_FPID)
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val_freq = freq_idx - 1;
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else if (freq_src == CLK_SRC_GPTC)
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val_freq = freq_idx - MAX_FPID_FREQ_RANK;
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/* set blink rate idx */
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if (freq_src != CLK_SRC_GPTC_HS) {
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low = GET_FREQ_OFFSET(off, freq_src);
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high = low + 2;
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val = val_freq << high;
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regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val);
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}
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/* select clock source */
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low = GET_SRC_OFFSET(off);
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high = low + 2;
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val = freq_src << high;
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regmap_update_bits(priv->mmap, reg, GENMASK(high, low), val);
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}
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static void sso_led_brightness_set(struct led_classdev *led_cdev,
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enum led_brightness brightness)
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{
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struct sso_led_priv *priv;
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struct sso_led_desc *desc;
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struct sso_led *led;
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int val;
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led = cdev_to_sso_led_data(led_cdev);
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priv = led->priv;
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desc = &led->desc;
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desc->brightness = brightness;
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regmap_write(priv->mmap, DUTY_CYCLE(desc->pin), brightness);
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if (brightness == LED_OFF)
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val = 0;
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else
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val = 1;
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/* HW blink off */
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if (desc->hw_blink && !val && desc->blinking) {
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desc->blinking = 0;
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regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin), 0);
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} else if (desc->hw_blink && val && !desc->blinking) {
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desc->blinking = 1;
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regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin),
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1 << desc->pin);
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}
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if (!desc->hw_trig && led->gpiod)
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gpiod_set_value(led->gpiod, val);
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}
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static enum led_brightness sso_led_brightness_get(struct led_classdev *led_cdev)
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{
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struct sso_led *led = cdev_to_sso_led_data(led_cdev);
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return (enum led_brightness)led->desc.brightness;
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}
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static int
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delay_to_freq_idx(struct sso_led *led, unsigned long *delay_on,
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unsigned long *delay_off)
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{
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struct sso_led_priv *priv = led->priv;
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unsigned long delay;
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int freq_idx;
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u32 freq;
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if (!*delay_on && !*delay_off) {
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*delay_on = *delay_off = (1000 / priv->freq[0]) / 2;
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return 0;
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}
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delay = *delay_on + *delay_off;
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freq = 1000 / delay;
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freq_idx = sso_get_blink_rate_idx(priv, freq);
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if (freq_idx == -1)
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freq_idx = MAX_FREQ_RANK - 1;
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delay = 1000 / priv->freq[freq_idx];
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*delay_on = *delay_off = delay / 2;
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if (!*delay_on)
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*delay_on = *delay_off = 1;
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return freq_idx;
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}
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static int
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sso_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
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unsigned long *delay_off)
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{
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struct sso_led_priv *priv;
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struct sso_led *led;
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int freq_idx;
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led = cdev_to_sso_led_data(led_cdev);
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priv = led->priv;
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freq_idx = delay_to_freq_idx(led, delay_on, delay_off);
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sso_led_freq_set(priv, led->desc.pin, freq_idx);
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regmap_update_bits(priv->mmap, SSO_CON2, BIT(led->desc.pin),
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1 << led->desc.pin);
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led->desc.freq_idx = freq_idx;
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led->desc.blink_rate = priv->freq[freq_idx];
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led->desc.blinking = 1;
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return 1;
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}
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static void sso_led_hw_cfg(struct sso_led_priv *priv, struct sso_led *led)
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{
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struct sso_led_desc *desc = &led->desc;
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/* set freq */
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if (desc->hw_blink) {
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sso_led_freq_set(priv, desc->pin, desc->freq_idx);
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regmap_update_bits(priv->mmap, SSO_CON2, BIT(desc->pin),
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1 << desc->pin);
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}
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if (desc->hw_trig)
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regmap_update_bits(priv->mmap, SSO_CON3, BIT(desc->pin),
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1 << desc->pin);
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/* set brightness */
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regmap_write(priv->mmap, DUTY_CYCLE(desc->pin), desc->brightness);
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/* enable output */
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if (!desc->hw_trig && desc->brightness)
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gpiod_set_value(led->gpiod, 1);
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}
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static int sso_create_led(struct sso_led_priv *priv, struct sso_led *led,
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struct fwnode_handle *child)
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{
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struct sso_led_desc *desc = &led->desc;
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struct led_init_data init_data;
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int err;
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init_data.fwnode = child;
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init_data.devicename = SSO_DEV_NAME;
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init_data.default_label = ":";
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led->cdev.default_trigger = desc->default_trigger;
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led->cdev.brightness_set = sso_led_brightness_set;
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led->cdev.brightness_get = sso_led_brightness_get;
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led->cdev.brightness = desc->brightness;
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led->cdev.max_brightness = LED_FULL;
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if (desc->retain_state_shutdown)
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led->cdev.flags |= LED_RETAIN_AT_SHUTDOWN;
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if (desc->retain_state_suspended)
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led->cdev.flags |= LED_CORE_SUSPENDRESUME;
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if (desc->panic_indicator)
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led->cdev.flags |= LED_PANIC_INDICATOR;
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if (desc->hw_blink)
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led->cdev.blink_set = sso_led_blink_set;
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sso_led_hw_cfg(priv, led);
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err = devm_led_classdev_register_ext(priv->dev, &led->cdev, &init_data);
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if (err)
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return err;
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list_add(&led->list, &priv->led_list);
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return 0;
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}
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static void sso_init_freq(struct sso_led_priv *priv)
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{
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int i;
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priv->freq[0] = 0;
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for (i = 1; i < MAX_FREQ_RANK; i++) {
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if (i < MAX_FPID_FREQ_RANK) {
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priv->freq[i] = priv->fpid_clkrate / freq_div_tbl[i - 1];
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} else if (i < MAX_GPTC_FREQ_RANK) {
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priv->freq[i] = priv->gptc_clkrate /
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freq_div_tbl[i - MAX_FPID_FREQ_RANK];
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} else if (i < MAX_GPTC_HS_FREQ_RANK) {
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priv->freq[i] = priv->gptc_clkrate;
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}
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}
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}
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static int sso_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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struct sso_led_priv *priv = gpiochip_get_data(chip);
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if (priv->gpio.alloc_bitmap & BIT(offset))
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return -EINVAL;
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priv->gpio.alloc_bitmap |= BIT(offset);
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regmap_write(priv->mmap, DUTY_CYCLE(offset), 0xFF);
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return 0;
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}
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static void sso_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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struct sso_led_priv *priv = gpiochip_get_data(chip);
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priv->gpio.alloc_bitmap &= ~BIT(offset);
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regmap_write(priv->mmap, DUTY_CYCLE(offset), 0x0);
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}
|
||
|
|
||
|
static int sso_gpio_get_dir(struct gpio_chip *chip, unsigned int offset)
|
||
|
{
|
||
|
return GPIOF_DIR_OUT;
|
||
|
}
|
||
|
|
||
|
static int
|
||
|
sso_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, int value)
|
||
|
{
|
||
|
struct sso_led_priv *priv = gpiochip_get_data(chip);
|
||
|
bool bit = !!value;
|
||
|
|
||
|
regmap_update_bits(priv->mmap, SSO_CPU, BIT(offset), bit << offset);
|
||
|
if (!priv->gpio.freq)
|
||
|
regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_SWU,
|
||
|
SSO_CON0_SWU);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int sso_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||
|
{
|
||
|
struct sso_led_priv *priv = gpiochip_get_data(chip);
|
||
|
u32 reg_val;
|
||
|
|
||
|
regmap_read(priv->mmap, SSO_CPU, ®_val);
|
||
|
|
||
|
return !!(reg_val & BIT(offset));
|
||
|
}
|
||
|
|
||
|
static void sso_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||
|
{
|
||
|
struct sso_led_priv *priv = gpiochip_get_data(chip);
|
||
|
|
||
|
regmap_update_bits(priv->mmap, SSO_CPU, BIT(offset), value << offset);
|
||
|
if (!priv->gpio.freq)
|
||
|
regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_SWU,
|
||
|
SSO_CON0_SWU);
|
||
|
}
|
||
|
|
||
|
static int sso_gpio_gc_init(struct device *dev, struct sso_led_priv *priv)
|
||
|
{
|
||
|
struct gpio_chip *gc = &priv->gpio.chip;
|
||
|
|
||
|
gc->request = sso_gpio_request;
|
||
|
gc->free = sso_gpio_free;
|
||
|
gc->get_direction = sso_gpio_get_dir;
|
||
|
gc->direction_output = sso_gpio_dir_out;
|
||
|
gc->get = sso_gpio_get;
|
||
|
gc->set = sso_gpio_set;
|
||
|
|
||
|
gc->label = "lgm-sso";
|
||
|
gc->base = -1;
|
||
|
/* To exclude pins from control, use "gpio-reserved-ranges" */
|
||
|
gc->ngpio = priv->gpio.pins;
|
||
|
gc->parent = dev;
|
||
|
gc->owner = THIS_MODULE;
|
||
|
gc->of_node = dev->of_node;
|
||
|
|
||
|
return devm_gpiochip_add_data(dev, gc, priv);
|
||
|
}
|
||
|
|
||
|
static int sso_gpio_get_freq_idx(int freq)
|
||
|
{
|
||
|
int idx;
|
||
|
|
||
|
for (idx = 0; idx < ARRAY_SIZE(freq_tbl); idx++) {
|
||
|
if (freq <= freq_tbl[idx])
|
||
|
return idx;
|
||
|
}
|
||
|
|
||
|
return -1;
|
||
|
}
|
||
|
|
||
|
static void sso_register_shift_clk(struct sso_led_priv *priv)
|
||
|
{
|
||
|
int idx, size = ARRAY_SIZE(shift_clk_freq_tbl);
|
||
|
u32 val = 0;
|
||
|
|
||
|
for (idx = 0; idx < size; idx++) {
|
||
|
if (shift_clk_freq_tbl[idx] <= priv->gpio.shift_clk_freq) {
|
||
|
val = idx;
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (idx == size)
|
||
|
dev_warn(priv->dev, "%s: Invalid freq %d\n",
|
||
|
__func__, priv->gpio.shift_clk_freq);
|
||
|
|
||
|
regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_FCDSC,
|
||
|
FIELD_PREP(SSO_CON1_FCDSC, val));
|
||
|
}
|
||
|
|
||
|
static int sso_gpio_freq_set(struct sso_led_priv *priv)
|
||
|
{
|
||
|
int freq_idx;
|
||
|
u32 val;
|
||
|
|
||
|
freq_idx = sso_gpio_get_freq_idx(priv->gpio.freq);
|
||
|
if (freq_idx == -1)
|
||
|
freq_idx = ARRAY_SIZE(freq_tbl) - 1;
|
||
|
|
||
|
val = freq_idx % FPID_FREQ_RANK_MAX;
|
||
|
|
||
|
if (!priv->gpio.freq) {
|
||
|
regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R, 0);
|
||
|
regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US,
|
||
|
FIELD_PREP(SSO_CON1_US, US_SW));
|
||
|
} else if (freq_idx < FPID_FREQ_RANK_MAX) {
|
||
|
regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R,
|
||
|
SSO_CON0_BLINK_R);
|
||
|
regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US,
|
||
|
FIELD_PREP(SSO_CON1_US, US_FPID));
|
||
|
regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_FPID,
|
||
|
FIELD_PREP(SSO_CON1_FPID, val));
|
||
|
} else {
|
||
|
regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_BLINK_R,
|
||
|
SSO_CON0_BLINK_R);
|
||
|
regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_US,
|
||
|
FIELD_PREP(SSO_CON1_US, US_GPTC));
|
||
|
regmap_update_bits(priv->mmap, SSO_CON1, SSO_CON1_GPTD,
|
||
|
FIELD_PREP(SSO_CON1_GPTD, val));
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int sso_gpio_hw_init(struct sso_led_priv *priv)
|
||
|
{
|
||
|
u32 activate;
|
||
|
int i, err;
|
||
|
|
||
|
/* Clear all duty cycles */
|
||
|
for (i = 0; i < priv->gpio.pins; i++) {
|
||
|
err = regmap_write(priv->mmap, DUTY_CYCLE(i), 0);
|
||
|
if (err)
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
/* 4 groups for total 32 pins */
|
||
|
for (i = 1; i <= MAX_GROUP_NUM; i++) {
|
||
|
activate = !!(i * PINS_PER_GROUP <= priv->gpio.pins ||
|
||
|
priv->gpio.pins > (i - 1) * PINS_PER_GROUP);
|
||
|
err = regmap_update_bits(priv->mmap, SSO_CON1, BIT(i - 1),
|
||
|
activate << (i - 1));
|
||
|
if (err)
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
/* NO HW directly controlled pin by default */
|
||
|
err = regmap_write(priv->mmap, SSO_CON3, 0);
|
||
|
if (err)
|
||
|
return err;
|
||
|
|
||
|
/* NO BLINK for all pins */
|
||
|
err = regmap_write(priv->mmap, SSO_CON2, 0);
|
||
|
if (err)
|
||
|
return err;
|
||
|
|
||
|
/* OUTPUT 0 by default */
|
||
|
err = regmap_write(priv->mmap, SSO_CPU, 0);
|
||
|
if (err)
|
||
|
return err;
|
||
|
|
||
|
/* update edge */
|
||
|
err = regmap_update_bits(priv->mmap, SSO_CON0, SSO_CON0_RZFL,
|
||
|
FIELD_PREP(SSO_CON0_RZFL, priv->gpio.edge));
|
||
|
if (err)
|
||
|
return err;
|
||
|
|
||
|
/* Set GPIO update rate */
|
||
|
sso_gpio_freq_set(priv);
|
||
|
|
||
|
/* Register shift clock */
|
||
|
sso_register_shift_clk(priv);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void sso_led_shutdown(struct sso_led *led)
|
||
|
{
|
||
|
struct sso_led_priv *priv = led->priv;
|
||
|
|
||
|
/* unregister led */
|
||
|
devm_led_classdev_unregister(priv->dev, &led->cdev);
|
||
|
|
||
|
/* clear HW control bit */
|
||
|
if (led->desc.hw_trig)
|
||
|
regmap_update_bits(priv->mmap, SSO_CON3, BIT(led->desc.pin), 0);
|
||
|
|
||
|
if (led->gpiod)
|
||
|
devm_gpiod_put(priv->dev, led->gpiod);
|
||
|
|
||
|
led->priv = NULL;
|
||
|
}
|
||
|
|
||
|
static int
|
||
|
__sso_led_dt_parse(struct sso_led_priv *priv, struct fwnode_handle *fw_ssoled)
|
||
|
{
|
||
|
struct fwnode_handle *fwnode_child;
|
||
|
struct device *dev = priv->dev;
|
||
|
struct sso_led_desc *desc;
|
||
|
struct sso_led *led;
|
||
|
struct list_head *p;
|
||
|
const char *tmp;
|
||
|
u32 prop;
|
||
|
int ret;
|
||
|
|
||
|
fwnode_for_each_child_node(fw_ssoled, fwnode_child) {
|
||
|
led = devm_kzalloc(dev, sizeof(*led), GFP_KERNEL);
|
||
|
if (!led)
|
||
|
return -ENOMEM;
|
||
|
|
||
|
INIT_LIST_HEAD(&led->list);
|
||
|
led->priv = priv;
|
||
|
desc = &led->desc;
|
||
|
|
||
|
led->gpiod = devm_fwnode_get_gpiod_from_child(dev, NULL,
|
||
|
fwnode_child,
|
||
|
GPIOD_ASIS, NULL);
|
||
|
if (IS_ERR(led->gpiod)) {
|
||
|
dev_err(dev, "led: get gpio fail!\n");
|
||
|
goto __dt_err;
|
||
|
}
|
||
|
|
||
|
fwnode_property_read_string(fwnode_child,
|
||
|
"linux,default-trigger",
|
||
|
&desc->default_trigger);
|
||
|
|
||
|
if (fwnode_property_present(fwnode_child,
|
||
|
"retain-state-suspended"))
|
||
|
desc->retain_state_suspended = 1;
|
||
|
|
||
|
if (fwnode_property_present(fwnode_child,
|
||
|
"retain-state-shutdown"))
|
||
|
desc->retain_state_shutdown = 1;
|
||
|
|
||
|
if (fwnode_property_present(fwnode_child, "panic-indicator"))
|
||
|
desc->panic_indicator = 1;
|
||
|
|
||
|
ret = fwnode_property_read_u32(fwnode_child, "reg", &prop);
|
||
|
if (ret != 0 || prop >= SSO_LED_MAX_NUM) {
|
||
|
dev_err(dev, "invalid LED pin:%u\n", prop);
|
||
|
goto __dt_err;
|
||
|
}
|
||
|
desc->pin = prop;
|
||
|
|
||
|
if (fwnode_property_present(fwnode_child, "intel,sso-hw-blink"))
|
||
|
desc->hw_blink = 1;
|
||
|
|
||
|
desc->hw_trig = fwnode_property_read_bool(fwnode_child,
|
||
|
"intel,sso-hw-trigger");
|
||
|
if (desc->hw_trig) {
|
||
|
desc->default_trigger = NULL;
|
||
|
desc->retain_state_shutdown = 0;
|
||
|
desc->retain_state_suspended = 0;
|
||
|
desc->panic_indicator = 0;
|
||
|
desc->hw_blink = 0;
|
||
|
}
|
||
|
|
||
|
if (fwnode_property_read_u32(fwnode_child,
|
||
|
"intel,sso-blink-rate-hz", &prop)) {
|
||
|
/* default first freq rate */
|
||
|
desc->freq_idx = 0;
|
||
|
desc->blink_rate = priv->freq[desc->freq_idx];
|
||
|
} else {
|
||
|
desc->freq_idx = sso_get_blink_rate_idx(priv, prop);
|
||
|
if (desc->freq_idx == -1)
|
||
|
desc->freq_idx = MAX_FREQ_RANK - 1;
|
||
|
|
||
|
desc->blink_rate = priv->freq[desc->freq_idx];
|
||
|
}
|
||
|
|
||
|
if (!fwnode_property_read_string(fwnode_child, "default-state", &tmp)) {
|
||
|
if (!strcmp(tmp, "on"))
|
||
|
desc->brightness = LED_FULL;
|
||
|
}
|
||
|
|
||
|
if (sso_create_led(priv, led, fwnode_child))
|
||
|
goto __dt_err;
|
||
|
}
|
||
|
fwnode_handle_put(fw_ssoled);
|
||
|
|
||
|
return 0;
|
||
|
__dt_err:
|
||
|
fwnode_handle_put(fw_ssoled);
|
||
|
/* unregister leds */
|
||
|
list_for_each(p, &priv->led_list) {
|
||
|
led = list_entry(p, struct sso_led, list);
|
||
|
sso_led_shutdown(led);
|
||
|
}
|
||
|
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
static int sso_led_dt_parse(struct sso_led_priv *priv)
|
||
|
{
|
||
|
struct fwnode_handle *fwnode = dev_fwnode(priv->dev);
|
||
|
struct fwnode_handle *fw_ssoled;
|
||
|
struct device *dev = priv->dev;
|
||
|
int count;
|
||
|
int ret;
|
||
|
|
||
|
count = device_get_child_node_count(dev);
|
||
|
if (!count)
|
||
|
return 0;
|
||
|
|
||
|
fw_ssoled = fwnode_get_named_child_node(fwnode, "ssoled");
|
||
|
if (fw_ssoled) {
|
||
|
ret = __sso_led_dt_parse(priv, fw_ssoled);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int sso_probe_gpios(struct sso_led_priv *priv)
|
||
|
{
|
||
|
struct device *dev = priv->dev;
|
||
|
int ret;
|
||
|
|
||
|
if (device_property_read_u32(dev, "ngpios", &priv->gpio.pins))
|
||
|
priv->gpio.pins = MAX_PIN_NUM_PER_BANK;
|
||
|
|
||
|
if (priv->gpio.pins > MAX_PIN_NUM_PER_BANK)
|
||
|
return -EINVAL;
|
||
|
|
||
|
if (device_property_read_u32(dev, "intel,sso-update-rate-hz",
|
||
|
&priv->gpio.freq))
|
||
|
priv->gpio.freq = 0;
|
||
|
|
||
|
priv->gpio.edge = DATA_CLK_EDGE;
|
||
|
priv->gpio.shift_clk_freq = -1;
|
||
|
|
||
|
ret = sso_gpio_hw_init(priv);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
return sso_gpio_gc_init(dev, priv);
|
||
|
}
|
||
|
|
||
|
static void sso_clk_disable(void *data)
|
||
|
{
|
||
|
struct sso_led_priv *priv = data;
|
||
|
|
||
|
clk_disable_unprepare(priv->fpid_clk);
|
||
|
clk_disable_unprepare(priv->gclk);
|
||
|
}
|
||
|
|
||
|
static int intel_sso_led_probe(struct platform_device *pdev)
|
||
|
{
|
||
|
struct device *dev = &pdev->dev;
|
||
|
struct sso_led_priv *priv;
|
||
|
int ret;
|
||
|
|
||
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||
|
if (!priv)
|
||
|
return -ENOMEM;
|
||
|
|
||
|
priv->pdev = pdev;
|
||
|
priv->dev = dev;
|
||
|
|
||
|
/* gate clock */
|
||
|
priv->gclk = devm_clk_get(dev, "sso");
|
||
|
if (IS_ERR(priv->gclk)) {
|
||
|
dev_err(dev, "get sso gate clock failed!\n");
|
||
|
return PTR_ERR(priv->gclk);
|
||
|
}
|
||
|
|
||
|
ret = clk_prepare_enable(priv->gclk);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Failed to prepate/enable sso gate clock!\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
priv->fpid_clk = devm_clk_get(dev, "fpid");
|
||
|
if (IS_ERR(priv->fpid_clk)) {
|
||
|
dev_err(dev, "Failed to get fpid clock!\n");
|
||
|
return PTR_ERR(priv->fpid_clk);
|
||
|
}
|
||
|
|
||
|
ret = clk_prepare_enable(priv->fpid_clk);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Failed to prepare/enable fpid clock!\n");
|
||
|
return ret;
|
||
|
}
|
||
|
priv->fpid_clkrate = clk_get_rate(priv->fpid_clk);
|
||
|
|
||
|
ret = devm_add_action_or_reset(dev, sso_clk_disable, priv);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Failed to devm_add_action_or_reset, %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
priv->mmap = syscon_node_to_regmap(dev->of_node);
|
||
|
if (IS_ERR(priv->mmap)) {
|
||
|
dev_err(dev, "Failed to map iomem!\n");
|
||
|
return PTR_ERR(priv->mmap);
|
||
|
}
|
||
|
|
||
|
ret = sso_probe_gpios(priv);
|
||
|
if (ret) {
|
||
|
regmap_exit(priv->mmap);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
INIT_LIST_HEAD(&priv->led_list);
|
||
|
|
||
|
platform_set_drvdata(pdev, priv);
|
||
|
sso_init_freq(priv);
|
||
|
|
||
|
priv->gptc_clkrate = DEF_GPTC_CLK_RATE;
|
||
|
|
||
|
ret = sso_led_dt_parse(priv);
|
||
|
if (ret) {
|
||
|
regmap_exit(priv->mmap);
|
||
|
return ret;
|
||
|
}
|
||
|
dev_info(priv->dev, "sso LED init success!\n");
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int intel_sso_led_remove(struct platform_device *pdev)
|
||
|
{
|
||
|
struct sso_led_priv *priv;
|
||
|
struct list_head *pos, *n;
|
||
|
struct sso_led *led;
|
||
|
|
||
|
priv = platform_get_drvdata(pdev);
|
||
|
|
||
|
list_for_each_safe(pos, n, &priv->led_list) {
|
||
|
list_del(pos);
|
||
|
led = list_entry(pos, struct sso_led, list);
|
||
|
sso_led_shutdown(led);
|
||
|
}
|
||
|
|
||
|
clk_disable_unprepare(priv->fpid_clk);
|
||
|
clk_disable_unprepare(priv->gclk);
|
||
|
regmap_exit(priv->mmap);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static const struct of_device_id of_sso_led_match[] = {
|
||
|
{ .compatible = "intel,lgm-ssoled" },
|
||
|
{}
|
||
|
};
|
||
|
|
||
|
MODULE_DEVICE_TABLE(of, of_sso_led_match);
|
||
|
|
||
|
static struct platform_driver intel_sso_led_driver = {
|
||
|
.probe = intel_sso_led_probe,
|
||
|
.remove = intel_sso_led_remove,
|
||
|
.driver = {
|
||
|
.name = "lgm-ssoled",
|
||
|
.of_match_table = of_match_ptr(of_sso_led_match),
|
||
|
},
|
||
|
};
|
||
|
|
||
|
module_platform_driver(intel_sso_led_driver);
|
||
|
|
||
|
MODULE_DESCRIPTION("Intel SSO LED/GPIO driver");
|
||
|
MODULE_LICENSE("GPL v2");
|