ARM: bcm2835: add interrupt controller driver
The BCM2835 contains a custom interrupt controller, which supports 72
interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence the symbol naming in the
code.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved implementation to drivers/irchip/.
* Added devicetree documentation, and hence removed list of IRQs from
bcm2835.dtsi.
* Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce
the size of the hwirq space, and pass the total size of the hwirq space
to irq_domain_add_linear(), rather than just the number of valid hwirqs;
the two are different due to the hwirq space being sparse.
* Added the interrupt controller DT node to the top-level of the DT,
rather than nesting it inside a /axi node. Hence, changed the reg value
since /axi had a ranges property. This seems simpler to me, but I'm not
sure if everyone will like this change or not.
* Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence
removing the need to patch include/linux/irqdomain.h or
kernel/irq/irqdomain.c.
* Simplified armctrl_of_init() using of_iomap().
* Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros.
* Renamed armctrl_handle_irq() to prevent possible symbol clashes.
* Made armctrl_of_init() static.
* Removed comment "Each bank is registered as a separate interrupt
controller" since this is no longer true.
* Removed FSF address from license header.
* Added my name to copyright header.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-09-13 09:57:26 +08:00
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BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
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The BCM2835 contains a custom top-level interrupt controller, which supports
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72 interrupt sources using a 2-level register scheme. The interrupt
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controller, or the HW block containing it, is referred to occasionally
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as "armctrl" in the SoC documentation, hence naming of this binding.
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Required properties:
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2012-10-03 09:26:37 +08:00
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- compatible : should be "brcm,bcm2835-armctrl-ic"
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ARM: bcm2835: add interrupt controller driver
The BCM2835 contains a custom interrupt controller, which supports 72
interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence the symbol naming in the
code.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved implementation to drivers/irchip/.
* Added devicetree documentation, and hence removed list of IRQs from
bcm2835.dtsi.
* Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce
the size of the hwirq space, and pass the total size of the hwirq space
to irq_domain_add_linear(), rather than just the number of valid hwirqs;
the two are different due to the hwirq space being sparse.
* Added the interrupt controller DT node to the top-level of the DT,
rather than nesting it inside a /axi node. Hence, changed the reg value
since /axi had a ranges property. This seems simpler to me, but I'm not
sure if everyone will like this change or not.
* Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence
removing the need to patch include/linux/irqdomain.h or
kernel/irq/irqdomain.c.
* Simplified armctrl_of_init() using of_iomap().
* Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros.
* Renamed armctrl_handle_irq() to prevent possible symbol clashes.
* Made armctrl_of_init() static.
* Removed comment "Each bank is registered as a separate interrupt
controller" since this is no longer true.
* Removed FSF address from license header.
* Added my name to copyright header.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-09-13 09:57:26 +08:00
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 2.
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The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
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pending" register, or 1/2 respectively for interrupts in the "IRQ pending
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1/2" register.
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The 2nd cell contains the interrupt number within the bank. Valid values
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are 0..7 for bank 0, and 0..31 for bank 1.
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The interrupt sources are as follows:
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Bank 0:
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0: ARM_TIMER
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1: ARM_MAILBOX
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2: ARM_DOORBELL_0
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3: ARM_DOORBELL_1
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4: VPU0_HALTED
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5: VPU1_HALTED
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6: ILLEGAL_TYPE0
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7: ILLEGAL_TYPE1
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Bank 1:
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0: TIMER0
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1: TIMER1
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2: TIMER2
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3: TIMER3
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4: CODEC0
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5: CODEC1
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6: CODEC2
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7: VC_JPEG
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8: ISP
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9: VC_USB
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10: VC_3D
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11: TRANSPOSER
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12: MULTICORESYNC0
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13: MULTICORESYNC1
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14: MULTICORESYNC2
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15: MULTICORESYNC3
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16: DMA0
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17: DMA1
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18: VC_DMA2
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19: VC_DMA3
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20: DMA4
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21: DMA5
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22: DMA6
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23: DMA7
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24: DMA8
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25: DMA9
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26: DMA10
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27: DMA11
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28: DMA12
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29: AUX
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30: ARM
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31: VPUDMA
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Bank 2:
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0: HOSTPORT
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1: VIDEOSCALER
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2: CCP2TX
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3: SDC
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4: DSI0
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5: AVE
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6: CAM0
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7: CAM1
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8: HDMI0
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9: HDMI1
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10: PIXELVALVE1
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11: I2CSPISLV
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12: DSI1
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13: PWA0
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14: PWA1
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15: CPR
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16: SMI
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17: GPIO0
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18: GPIO1
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19: GPIO2
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20: GPIO3
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21: VC_I2C
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22: VC_SPI
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23: VC_I2SPCM
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24: VC_SDIO
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25: VC_UART
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26: SLIMBUS
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27: VEC
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28: CPG
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29: RNG
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30: VC_ARASANSDIO
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31: AVSPMON
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Example:
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intc: interrupt-controller {
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compatible = "brcm,bcm2835-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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