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OpenCloudOS-Kernel/drivers/pinctrl/mvebu/pinctrl-armada-38x.c

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pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
/*
* Marvell Armada 380/385 pinctrl driver based on mvebu pinctrl core
*
* Copyright (C) 2013 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mvebu.h"
enum {
V_88F6810 = BIT(0),
V_88F6820 = BIT(1),
V_88F6828 = BIT(2),
V_88F6810_PLUS = (V_88F6810 | V_88F6820 | V_88F6828),
V_88F6820_PLUS = (V_88F6820 | V_88F6828),
};
static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
MPP_MODE(0,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6810_PLUS)),
MPP_MODE(1,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6810_PLUS)),
MPP_MODE(2,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6810_PLUS)),
MPP_MODE(3,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6810_PLUS)),
MPP_MODE(4,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge", "mdc", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS)),
MPP_MODE(5,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge", "mdio", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS)),
MPP_MODE(6,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txclkout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge0", "crs", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6810_PLUS)),
MPP_MODE(7,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6810_PLUS)),
MPP_MODE(8,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6810_PLUS)),
MPP_MODE(9,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6810_PLUS)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6810_PLUS)),
MPP_MODE(11,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6810_PLUS)),
MPP_MODE(12,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(13,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(14,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:03 +08:00
MPP_VAR_FUNCTION(3, "dram", "vttctrl", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins: 'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc. In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63. Since only the subnames are changed, this commit does not affect DT compatibility. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:06 +08:00
MPP_VAR_FUNCTION(5, "dev", "we1", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(15,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(16,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS),
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:03 +08:00
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(17,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add sata functions The latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:20 +08:00
MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "sata0", "prsnt", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(18,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS),
pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:02 +08:00
MPP_VAR_FUNCTION(2, "ptp", "trig", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(19,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS),
pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:02 +08:00
MPP_VAR_FUNCTION(2, "ptp", "evreq", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
pinctrl: mvebu: a38x: Add UART1 muxing options The MPP19 and MMP20 pins also have the ability to be muxed to the uart1 function. Add this case to the pinctrl driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-05 22:44:57 +08:00
MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(20,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
pinctrl: mvebu: a38x: Add UART1 muxing options The MPP19 and MMP20 pins also have the ability to be muxed to the uart1 function. Add this case to the pinctrl driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-05 22:44:57 +08:00
MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(21,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add sata functions The latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:20 +08:00
MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "sata1", "prsnt", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(22,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6810_PLUS)),
MPP_MODE(23,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6810_PLUS)),
MPP_MODE(24,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6810_PLUS)),
MPP_MODE(25,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6810_PLUS)),
MPP_MODE(26,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6810_PLUS)),
MPP_MODE(27,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txclkout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6810_PLUS)),
MPP_MODE(28,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6810_PLUS)),
MPP_MODE(29,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6810_PLUS)),
MPP_MODE(30,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins: 'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc. In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63. Since only the subnames are changed, this commit does not affect DT compatibility. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:06 +08:00
MPP_VAR_FUNCTION(5, "dev", "oe", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(31,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6810_PLUS)),
MPP_MODE(32,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins: 'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc. In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63. Since only the subnames are changed, this commit does not affect DT compatibility. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:06 +08:00
MPP_VAR_FUNCTION(5, "dev", "we0", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(33,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:03 +08:00
MPP_VAR_FUNCTION(1, "dram", "deccerr", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)),
MPP_MODE(34,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6810_PLUS)),
MPP_MODE(35,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)),
MPP_MODE(36,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:02 +08:00
MPP_VAR_FUNCTION(1, "ptp", "trig", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)),
MPP_MODE(37,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ptp", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)),
MPP_MODE(38,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:02 +08:00
MPP_VAR_FUNCTION(1, "ptp", "evreq", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6810_PLUS)),
MPP_MODE(39,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6810_PLUS)),
MPP_MODE(40,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxd3", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6810_PLUS)),
MPP_MODE(41,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add nand functions The latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:21 +08:00
MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb0", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(42,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6810_PLUS)),
MPP_MODE(43,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS),
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:03 +08:00
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add nand functions The latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:21 +08:00
MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "nand", "rb1", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(44,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(45,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:22 +08:00
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(46,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:22 +08:00
MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(47,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)),
MPP_MODE(48,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:03 +08:00
MPP_VAR_FUNCTION(2, "dram", "vttctrl", V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:08 +08:00
MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(49,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828),
MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828),
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:08 +08:00
MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(50,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:08 +08:00
MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)),
MPP_MODE(51,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:08 +08:00
MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ptp functions The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:23 +08:00
MPP_VAR_FUNCTION(5, "dram", "deccerr", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "trig", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(52,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:08 +08:00
MPP_VAR_FUNCTION(3, "tdm", "int", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ptp functions The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:23 +08:00
MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "clk", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(53,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS),
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:08 +08:00
MPP_VAR_FUNCTION(3, "tdm", "rst", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ptp functions The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:23 +08:00
MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ptp", "evreq", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(54,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: fix PCIe functions A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:46:53 +08:00
MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)),
MPP_MODE(55,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:22 +08:00
MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(56,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS),
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:03 +08:00
MPP_VAR_FUNCTION(3, "dram", "deccerr", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:22 +08:00
MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(57,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:22 +08:00
MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(58,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS),
MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS),
pinctrl: mvebu: armada-38x: add ua1 functions The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:22 +08:00
MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS),
MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
MPP_MODE(59,
MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS),
MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS),
MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)),
};
static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info;
pinctrl: constify of_device_id array of_device_id is always used as const. (See driver.of_match_table and open firmware functions) Signed-off-by: Fabian Frederick <fabf@skynet.be> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Lee Jones <lee@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-17 03:59:09 +08:00
static const struct of_device_id armada_38x_pinctrl_of_match[] = {
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
{
.compatible = "marvell,mv88f6810-pinctrl",
.data = (void *) V_88F6810,
},
{
.compatible = "marvell,mv88f6820-pinctrl",
.data = (void *) V_88F6820,
},
{
.compatible = "marvell,mv88f6828-pinctrl",
.data = (void *) V_88F6828,
},
{ },
};
pinctrl: mvebu: constify mvebu_mpp_ctrl structures As the mvebu_mpp_ctrl structures contain function pointers, it is preferable for these to be made read-only to prevent the function pointers being modified. So make these const. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-13 19:03:15 +08:00
static const struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = {
pinctrl: mvebu: switch drivers to generic simple mmio Move the mvebu pinctrl drivers over to the generic simple mmio implementation, saving a substantial number of lines of code in the process. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-13 19:03:30 +08:00
MPP_FUNC_CTRL(0, 59, NULL, mvebu_mmio_mpp_ctrl),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
};
static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = {
MPP_GPIO_RANGE(0, 0, 0, 32),
pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10 00:47:00 +08:00
MPP_GPIO_RANGE(1, 32, 32, 28),
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
};
static int armada_38x_pinctrl_probe(struct platform_device *pdev)
{
struct mvebu_pinctrl_soc_info *soc = &armada_38x_pinctrl_info;
const struct of_device_id *match =
of_match_device(armada_38x_pinctrl_of_match, &pdev->dev);
if (!match)
return -ENODEV;
soc->variant = (unsigned) match->data & 0xff;
soc->controls = armada_38x_mpp_controls;
soc->ncontrols = ARRAY_SIZE(armada_38x_mpp_controls);
soc->gpioranges = armada_38x_mpp_gpio_ranges;
soc->ngpioranges = ARRAY_SIZE(armada_38x_mpp_gpio_ranges);
soc->modes = armada_38x_mpp_modes;
soc->nmodes = armada_38x_mpp_controls[0].npins;
pdev->dev.platform_data = soc;
pinctrl: mvebu: switch drivers to generic simple mmio Move the mvebu pinctrl drivers over to the generic simple mmio implementation, saving a substantial number of lines of code in the process. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-13 19:03:30 +08:00
return mvebu_pinctrl_simple_mmio_probe(pdev);
pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385 The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing, it is similar to Armada 370 and XP for the register layout, only different in the number of available pins and their functions. Therefore, we simply use the existing drivers/pinctrl/mvebu/ infrastructure, with no other changes that the list of pins and corresponding functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-02-11 01:04:56 +08:00
}
static struct platform_driver armada_38x_pinctrl_driver = {
.driver = {
.name = "armada-38x-pinctrl",
.of_match_table = of_match_ptr(armada_38x_pinctrl_of_match),
},
.probe = armada_38x_pinctrl_probe,
};
pinctrl: mvebu: make bool drivers explicitly non-modular None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get the exact same change, so they are handled in batch. Changes are (1) use builtin_platform_driver, (2) dont use module.h (3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE, and (5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags. For the dove driver we explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. We deleted the MODULE_LICENSE etc. tags since all that information is already contained at the top of the file in the comments. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-02-06 16:03:50 +08:00
builtin_platform_driver(armada_38x_pinctrl_driver);