2019-05-27 14:55:06 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2015-10-23 18:52:00 +08:00
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <linux/clk.h>
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#include <linux/i2c.h>
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2016-09-23 21:34:41 +08:00
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#include <linux/iopoll.h>
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2015-10-23 18:52:00 +08:00
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define UNIPHIER_FI2C_CR 0x00 /* control register */
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#define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
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#define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
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#define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
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#define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
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#define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
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#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
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#define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
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#define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
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#define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
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#define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
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#define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
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#define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
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#define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */
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#define UNIPHIER_FI2C_INT 0x20 /* interrupt status */
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#define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */
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#define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */
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#define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */
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#define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */
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#define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */
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#define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */
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#define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */
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#define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */
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#define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */
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#define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */
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#define UNIPHIER_FI2C_SR 0x2c /* status register */
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#define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */
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#define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */
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#define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */
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#define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */
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#define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */
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#define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */
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#define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */
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#define UNIPHIER_FI2C_RST 0x34 /* reset control */
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#define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */
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#define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */
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#define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */
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#define UNIPHIER_FI2C_BM 0x38 /* bus monitor */
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#define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */
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#define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */
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#define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */
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#define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */
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#define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */
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#define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */
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#define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */
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#define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */
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#define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */
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#define UNIPHIER_FI2C_BRST 0x50 /* bus reset */
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#define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */
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#define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */
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#define UNIPHIER_FI2C_INT_FAULTS \
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(UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
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#define UNIPHIER_FI2C_INT_STOP \
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(UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
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#define UNIPHIER_FI2C_RD BIT(0)
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#define UNIPHIER_FI2C_STOP BIT(1)
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#define UNIPHIER_FI2C_MANUAL_NACK BIT(2)
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#define UNIPHIER_FI2C_BYTE_WISE BIT(3)
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#define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4)
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#define UNIPHIER_FI2C_DEFAULT_SPEED 100000
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#define UNIPHIER_FI2C_MAX_SPEED 400000
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#define UNIPHIER_FI2C_FIFO_SIZE 8
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struct uniphier_fi2c_priv {
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struct completion comp;
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struct i2c_adapter adap;
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void __iomem *membase;
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struct clk *clk;
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unsigned int len;
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u8 *buf;
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u32 enabled_irqs;
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int error;
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unsigned int flags;
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unsigned int busy_cnt;
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2017-07-31 13:53:07 +08:00
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unsigned int clk_cycle;
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2018-10-16 11:01:47 +08:00
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spinlock_t lock; /* IRQ synchronization */
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2015-10-23 18:52:00 +08:00
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};
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static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
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bool first)
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{
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int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
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/*
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* TX-FIFO stores slave address in it for the first access.
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* Decrement the counter.
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*/
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if (first)
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fifo_space--;
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while (priv->len) {
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if (fifo_space-- <= 0)
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break;
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writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
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priv->len--;
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}
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}
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static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
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{
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int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
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1 : UNIPHIER_FI2C_FIFO_SIZE;
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while (priv->len) {
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if (fifo_left-- <= 0)
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break;
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*priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
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priv->len--;
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}
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}
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static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
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{
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writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
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}
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2018-10-16 11:01:49 +08:00
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static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv,
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u32 mask)
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2015-10-23 18:52:00 +08:00
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{
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2018-10-16 11:01:49 +08:00
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writel(mask, priv->membase + UNIPHIER_FI2C_IC);
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2015-10-23 18:52:00 +08:00
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}
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static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
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{
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
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uniphier_fi2c_set_irqs(priv);
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writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
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priv->membase + UNIPHIER_FI2C_CR);
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}
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static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
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{
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struct uniphier_fi2c_priv *priv = dev_id;
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u32 irq_status;
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2018-10-16 11:01:47 +08:00
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spin_lock(&priv->lock);
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2015-10-23 18:52:00 +08:00
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irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
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2018-10-16 11:01:47 +08:00
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irq_status &= priv->enabled_irqs;
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2015-10-23 18:52:00 +08:00
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if (irq_status & UNIPHIER_FI2C_INT_STOP)
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goto complete;
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if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
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priv->error = -EAGAIN;
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goto complete;
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}
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if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
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priv->error = -ENXIO;
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if (priv->flags & UNIPHIER_FI2C_RD) {
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/*
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* work around a hardware bug:
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* The receive-completed interrupt is never set even if
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* STOP condition is detected after the address phase
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* of read transaction fails to get ACK.
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* To avoid time-out error, we issue STOP here,
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* but do not wait for its completion.
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* It should be checked after exiting this handler.
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*/
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uniphier_fi2c_stop(priv);
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priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
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goto complete;
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}
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goto stop;
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}
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if (irq_status & UNIPHIER_FI2C_INT_TE) {
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if (!priv->len)
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goto data_done;
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uniphier_fi2c_fill_txfifo(priv, false);
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goto handled;
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}
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if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
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uniphier_fi2c_drain_rxfifo(priv);
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i2c: uniphier-f: fix timeout error after reading 8 bytes
I was totally screwed up in commit eaba68785c2d ("i2c: uniphier-f:
fix race condition when IRQ is cleared"). Since that commit, if the
number of read bytes is multiple of the FIFO size (8, 16, 24... bytes),
the STOP condition could be issued twice, depending on the timing.
If this happens, the controller will go wrong, resulting in the timeout
error.
It was more than 3 years ago when I wrote this driver, so my memory
about this hardware was vague. Please let me correct the description
in the commit log of eaba68785c2d.
Clearing the IRQ status on exiting the IRQ handler is absolutely
fine. This controller makes a pause while any IRQ status is asserted.
If the IRQ status is cleared first, the hardware may start the next
transaction before the IRQ handler finishes what it supposed to do.
This partially reverts the bad commit with clear comments so that I
will never repeat this mistake.
I also investigated what is happening at the last moment of the read
mode. The UNIPHIER_FI2C_INT_RF interrupt is asserted a bit earlier
(by half a period of the clock cycle) than UNIPHIER_FI2C_INT_RB.
I consulted a hardware engineer, and I got the following information:
UNIPHIER_FI2C_INT_RF
asserted at the falling edge of SCL at the 8th bit.
UNIPHIER_FI2C_INT_RB
asserted at the rising edge of SCL at the 9th (ACK) bit.
In order to avoid calling uniphier_fi2c_stop() twice, check the latter
interrupt. I also commented this because it is obscure hardware internal.
Fixes: eaba68785c2d ("i2c: uniphier-f: fix race condition when IRQ is cleared")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-06 11:55:25 +08:00
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/*
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* If the number of bytes to read is multiple of the FIFO size
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* (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little
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* earlier than INT_RB. We wait for INT_RB to confirm the
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* completion of the current message.
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*/
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if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB))
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2015-10-23 18:52:00 +08:00
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goto data_done;
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if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
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if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
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!(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
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uniphier_fi2c_set_irqs(priv);
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priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
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}
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2019-09-05 12:46:48 +08:00
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if (priv->len <= 1)
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2015-10-23 18:52:00 +08:00
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writel(UNIPHIER_FI2C_CR_MST |
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UNIPHIER_FI2C_CR_NACK,
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priv->membase + UNIPHIER_FI2C_CR);
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}
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goto handled;
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}
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2018-10-16 11:01:47 +08:00
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spin_unlock(&priv->lock);
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2015-10-23 18:52:00 +08:00
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return IRQ_NONE;
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data_done:
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if (priv->flags & UNIPHIER_FI2C_STOP) {
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stop:
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uniphier_fi2c_stop(priv);
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} else {
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complete:
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priv->enabled_irqs = 0;
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uniphier_fi2c_set_irqs(priv);
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complete(&priv->comp);
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}
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handled:
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i2c: uniphier-f: fix timeout error after reading 8 bytes
I was totally screwed up in commit eaba68785c2d ("i2c: uniphier-f:
fix race condition when IRQ is cleared"). Since that commit, if the
number of read bytes is multiple of the FIFO size (8, 16, 24... bytes),
the STOP condition could be issued twice, depending on the timing.
If this happens, the controller will go wrong, resulting in the timeout
error.
It was more than 3 years ago when I wrote this driver, so my memory
about this hardware was vague. Please let me correct the description
in the commit log of eaba68785c2d.
Clearing the IRQ status on exiting the IRQ handler is absolutely
fine. This controller makes a pause while any IRQ status is asserted.
If the IRQ status is cleared first, the hardware may start the next
transaction before the IRQ handler finishes what it supposed to do.
This partially reverts the bad commit with clear comments so that I
will never repeat this mistake.
I also investigated what is happening at the last moment of the read
mode. The UNIPHIER_FI2C_INT_RF interrupt is asserted a bit earlier
(by half a period of the clock cycle) than UNIPHIER_FI2C_INT_RB.
I consulted a hardware engineer, and I got the following information:
UNIPHIER_FI2C_INT_RF
asserted at the falling edge of SCL at the 8th bit.
UNIPHIER_FI2C_INT_RB
asserted at the rising edge of SCL at the 9th (ACK) bit.
In order to avoid calling uniphier_fi2c_stop() twice, check the latter
interrupt. I also commented this because it is obscure hardware internal.
Fixes: eaba68785c2d ("i2c: uniphier-f: fix race condition when IRQ is cleared")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-06 11:55:25 +08:00
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/*
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* This controller makes a pause while any bit of the IRQ status is
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* asserted. Clear the asserted bit to kick the controller just before
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* exiting the handler.
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*/
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uniphier_fi2c_clear_irqs(priv, irq_status);
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2018-10-16 11:01:47 +08:00
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spin_unlock(&priv->lock);
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2015-10-23 18:52:00 +08:00
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return IRQ_HANDLED;
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}
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2018-12-06 11:55:26 +08:00
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static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,
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bool repeat)
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2015-10-23 18:52:00 +08:00
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{
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priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
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i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
uniphier_fi2c_set_irqs(priv);
|
|
|
|
|
2015-10-23 18:52:00 +08:00
|
|
|
/* do not use TX byte counter */
|
|
|
|
writel(0, priv->membase + UNIPHIER_FI2C_TBC);
|
|
|
|
/* set slave address */
|
|
|
|
writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
|
|
|
|
priv->membase + UNIPHIER_FI2C_DTTX);
|
2018-12-06 11:55:26 +08:00
|
|
|
/*
|
|
|
|
* First chunk of data. For a repeated START condition, do not write
|
|
|
|
* data to the TX fifo here to avoid the timing issue.
|
|
|
|
*/
|
|
|
|
if (!repeat)
|
|
|
|
uniphier_fi2c_fill_txfifo(priv, true);
|
2015-10-23 18:52:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
|
|
|
|
{
|
|
|
|
priv->flags |= UNIPHIER_FI2C_RD;
|
|
|
|
|
|
|
|
if (likely(priv->len < 256)) {
|
|
|
|
/*
|
|
|
|
* If possible, use RX byte counter.
|
|
|
|
* It can automatically handle NACK for the last byte.
|
|
|
|
*/
|
|
|
|
writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
|
|
|
|
priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
|
|
|
|
UNIPHIER_FI2C_INT_RB;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* The byte counter can not count over 256. In this case,
|
|
|
|
* do not use it at all. Drain data when FIFO gets full,
|
|
|
|
* but treat the last portion as a special case.
|
|
|
|
*/
|
|
|
|
writel(0, priv->membase + UNIPHIER_FI2C_RBC);
|
|
|
|
priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
|
|
|
|
priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
|
|
|
|
}
|
|
|
|
|
i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
uniphier_fi2c_set_irqs(priv);
|
|
|
|
|
2015-10-23 18:52:00 +08:00
|
|
|
/* set slave address with RD bit */
|
|
|
|
writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
|
|
|
|
priv->membase + UNIPHIER_FI2C_DTTX);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
|
|
|
|
{
|
|
|
|
writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
|
|
|
|
{
|
|
|
|
writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
|
|
|
|
priv->membase + UNIPHIER_FI2C_BRST);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
|
|
|
|
{
|
|
|
|
uniphier_fi2c_reset(priv);
|
|
|
|
i2c_recover_bus(&priv->adap);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
|
i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
struct i2c_msg *msg, bool repeat,
|
|
|
|
bool stop)
|
2015-10-23 18:52:00 +08:00
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
|
|
|
bool is_read = msg->flags & I2C_M_RD;
|
2018-10-16 11:01:47 +08:00
|
|
|
unsigned long time_left, flags;
|
2015-10-23 18:52:00 +08:00
|
|
|
|
|
|
|
priv->len = msg->len;
|
|
|
|
priv->buf = msg->buf;
|
|
|
|
priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
|
|
|
|
priv->error = 0;
|
|
|
|
priv->flags = 0;
|
|
|
|
|
|
|
|
if (stop)
|
|
|
|
priv->flags |= UNIPHIER_FI2C_STOP;
|
|
|
|
|
|
|
|
reinit_completion(&priv->comp);
|
2018-10-16 11:01:49 +08:00
|
|
|
uniphier_fi2c_clear_irqs(priv, U32_MAX);
|
2015-10-23 18:52:00 +08:00
|
|
|
writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
|
|
|
|
priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */
|
|
|
|
|
i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
|
2015-10-23 18:52:00 +08:00
|
|
|
if (is_read)
|
|
|
|
uniphier_fi2c_rx_init(priv, msg->addr);
|
|
|
|
else
|
2018-12-06 11:55:26 +08:00
|
|
|
uniphier_fi2c_tx_init(priv, msg->addr, repeat);
|
2015-10-23 18:52:00 +08:00
|
|
|
|
i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
/*
|
|
|
|
* For a repeated START condition, writing a slave address to the FIFO
|
|
|
|
* kicks the controller. So, the UNIPHIER_FI2C_CR register should be
|
|
|
|
* written only for a non-repeated START condition.
|
|
|
|
*/
|
|
|
|
if (!repeat)
|
|
|
|
writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
|
|
|
|
priv->membase + UNIPHIER_FI2C_CR);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
2015-10-23 18:52:00 +08:00
|
|
|
|
|
|
|
time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
|
2018-10-16 11:01:47 +08:00
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
priv->enabled_irqs = 0;
|
|
|
|
uniphier_fi2c_set_irqs(priv);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
|
2015-10-23 18:52:00 +08:00
|
|
|
if (!time_left) {
|
|
|
|
dev_err(&adap->dev, "transaction timeout.\n");
|
|
|
|
uniphier_fi2c_recover(priv);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
|
2016-09-23 21:34:41 +08:00
|
|
|
u32 status;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,
|
|
|
|
status,
|
|
|
|
(status & UNIPHIER_FI2C_SR_STS) &&
|
|
|
|
!(status & UNIPHIER_FI2C_SR_BB),
|
|
|
|
1, 20);
|
|
|
|
if (ret) {
|
2015-10-23 18:52:00 +08:00
|
|
|
dev_err(&adap->dev,
|
|
|
|
"stop condition was not completed.\n");
|
|
|
|
uniphier_fi2c_recover(priv);
|
2016-09-23 21:34:41 +08:00
|
|
|
return ret;
|
2015-10-23 18:52:00 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return priv->error;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
|
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
|
|
|
|
|
|
|
if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
|
|
|
|
if (priv->busy_cnt++ > 3) {
|
|
|
|
/*
|
|
|
|
* If bus busy continues too long, it is probably
|
|
|
|
* in a wrong state. Try bus recovery.
|
|
|
|
*/
|
|
|
|
uniphier_fi2c_recover(priv);
|
|
|
|
priv->busy_cnt = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->busy_cnt = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
|
|
|
|
struct i2c_msg *msgs, int num)
|
|
|
|
{
|
|
|
|
struct i2c_msg *msg, *emsg = msgs + num;
|
i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
bool repeat = false;
|
2015-10-23 18:52:00 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = uniphier_fi2c_check_bus_busy(adap);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for (msg = msgs; msg < emsg; msg++) {
|
2018-08-31 22:30:48 +08:00
|
|
|
/* Emit STOP if it is the last message or I2C_M_STOP is set. */
|
|
|
|
bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
|
2015-10-23 18:52:00 +08:00
|
|
|
|
i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
|
2015-10-23 18:52:00 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
i2c: uniphier-f: fix occasional timeout error
Currently, a timeout error could happen at a repeated START condition.
For a (non-repeated) START condition, the controller starts sending
data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
START condition, the hardware starts running when the slave address is
written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
actually unneeded.
Because the hardware is already running before the IRQ is enabled for
a repeated START, the driver may miss the IRQ event. In most cases,
this problem does not show up since modern CPUs are much faster than
the I2C transfer. However, it is still possible that a context switch
happens after the controller starts, but before the IRQ register is
set up.
To fix this,
- Do not write UNIPHIER_FI2C_CR for repeated START conditions.
- Enable IRQ *before* writing the slave address to the TX FIFO.
- Disable IRQ for the current CPU while queuing up the TX FIFO;
If the CPU is interrupted by some task, the interrupt handler
might be invoked due to the empty TX FIFO before completing the
setup.
Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-16 11:01:48 +08:00
|
|
|
|
|
|
|
repeat = !stop;
|
2015-10-23 18:52:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
|
|
|
|
{
|
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_algorithm uniphier_fi2c_algo = {
|
|
|
|
.master_xfer = uniphier_fi2c_master_xfer,
|
|
|
|
.functionality = uniphier_fi2c_functionality,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
|
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
|
|
|
|
|
|
|
return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
|
|
|
|
UNIPHIER_FI2C_BM_SCLS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
|
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
|
|
|
|
|
|
|
writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
|
|
|
|
priv->membase + UNIPHIER_FI2C_BRST);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
|
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
|
|
|
|
|
|
|
|
return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
|
|
|
|
UNIPHIER_FI2C_BM_SDAS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
|
|
|
|
{
|
|
|
|
uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
|
|
|
|
.recover_bus = i2c_generic_scl_recovery,
|
|
|
|
.get_scl = uniphier_fi2c_get_scl,
|
|
|
|
.set_scl = uniphier_fi2c_set_scl,
|
|
|
|
.get_sda = uniphier_fi2c_get_sda,
|
|
|
|
.unprepare_recovery = uniphier_fi2c_unprepare_recovery,
|
|
|
|
};
|
|
|
|
|
2017-07-31 13:53:07 +08:00
|
|
|
static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)
|
2015-10-23 18:52:00 +08:00
|
|
|
{
|
2017-07-31 13:53:07 +08:00
|
|
|
unsigned int cyc = priv->clk_cycle;
|
2016-09-01 19:46:30 +08:00
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
|
|
|
|
tmp |= UNIPHIER_FI2C_CR_MST;
|
|
|
|
writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
|
2015-10-23 18:52:00 +08:00
|
|
|
|
|
|
|
uniphier_fi2c_reset(priv);
|
|
|
|
|
2018-12-06 11:55:28 +08:00
|
|
|
/*
|
|
|
|
* Standard-mode: tLOW + tHIGH = 10 us
|
|
|
|
* Fast-mode: tLOW + tHIGH = 2.5 us
|
|
|
|
*/
|
2017-07-31 13:53:07 +08:00
|
|
|
writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
|
2018-12-06 11:55:28 +08:00
|
|
|
/*
|
|
|
|
* Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us
|
|
|
|
* Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us
|
|
|
|
* "tLow/tHIGH = 5/4" meets both.
|
|
|
|
*/
|
|
|
|
writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);
|
|
|
|
/*
|
|
|
|
* Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us
|
|
|
|
* Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us
|
|
|
|
*/
|
2017-07-31 13:53:07 +08:00
|
|
|
writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
|
2018-12-06 11:55:28 +08:00
|
|
|
/*
|
|
|
|
* Standard-mode: tSU;DAT = 250 ns
|
|
|
|
* Fast-mode: tSU;DAT = 100 ns
|
|
|
|
*/
|
2017-07-31 13:53:07 +08:00
|
|
|
writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
|
2015-10-23 18:52:00 +08:00
|
|
|
|
|
|
|
uniphier_fi2c_prepare_operation(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_fi2c_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct uniphier_fi2c_priv *priv;
|
2016-09-01 19:46:29 +08:00
|
|
|
u32 bus_speed;
|
|
|
|
unsigned long clk_rate;
|
|
|
|
int irq, ret;
|
2015-10-23 18:52:00 +08:00
|
|
|
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2019-09-05 11:45:32 +08:00
|
|
|
priv->membase = devm_platform_ioremap_resource(pdev, 0);
|
2015-10-23 18:52:00 +08:00
|
|
|
if (IS_ERR(priv->membase))
|
|
|
|
return PTR_ERR(priv->membase);
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
2016-04-21 14:12:44 +08:00
|
|
|
dev_err(dev, "failed to get IRQ number\n");
|
2015-10-23 18:52:00 +08:00
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
2016-09-01 19:46:29 +08:00
|
|
|
if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
|
|
|
|
bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED;
|
|
|
|
|
|
|
|
if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) {
|
|
|
|
dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
|
|
if (IS_ERR(priv->clk)) {
|
|
|
|
dev_err(dev, "failed to get clock\n");
|
|
|
|
return PTR_ERR(priv->clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
clk_rate = clk_get_rate(priv->clk);
|
|
|
|
if (!clk_rate) {
|
|
|
|
dev_err(dev, "input clock rate should not be zero\n");
|
|
|
|
ret = -EINVAL;
|
2016-11-04 18:49:21 +08:00
|
|
|
goto disable_clk;
|
2016-09-01 19:46:29 +08:00
|
|
|
}
|
|
|
|
|
2017-07-31 13:53:07 +08:00
|
|
|
priv->clk_cycle = clk_rate / bus_speed;
|
2015-10-23 18:52:00 +08:00
|
|
|
init_completion(&priv->comp);
|
2018-10-16 11:01:47 +08:00
|
|
|
spin_lock_init(&priv->lock);
|
2015-10-23 18:52:00 +08:00
|
|
|
priv->adap.owner = THIS_MODULE;
|
|
|
|
priv->adap.algo = &uniphier_fi2c_algo;
|
|
|
|
priv->adap.dev.parent = dev;
|
|
|
|
priv->adap.dev.of_node = dev->of_node;
|
|
|
|
strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
|
|
|
|
priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
|
|
|
|
i2c_set_adapdata(&priv->adap, priv);
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
|
2017-07-31 13:53:07 +08:00
|
|
|
uniphier_fi2c_hw_init(priv);
|
2015-10-23 18:52:00 +08:00
|
|
|
|
|
|
|
ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
|
|
|
|
pdev->name, priv);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to request irq %d\n", irq);
|
2016-11-04 18:49:21 +08:00
|
|
|
goto disable_clk;
|
2015-10-23 18:52:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = i2c_add_adapter(&priv->adap);
|
2016-11-04 18:49:21 +08:00
|
|
|
disable_clk:
|
2015-10-23 18:52:00 +08:00
|
|
|
if (ret)
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_fi2c_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
i2c_del_adapter(&priv->adap);
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-07-31 13:53:07 +08:00
|
|
|
static int __maybe_unused uniphier_fi2c_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __maybe_unused uniphier_fi2c_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
uniphier_fi2c_hw_init(priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dev_pm_ops uniphier_fi2c_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)
|
|
|
|
};
|
|
|
|
|
2015-10-23 18:52:00 +08:00
|
|
|
static const struct of_device_id uniphier_fi2c_match[] = {
|
|
|
|
{ .compatible = "socionext,uniphier-fi2c" },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
|
|
|
|
|
|
|
|
static struct platform_driver uniphier_fi2c_drv = {
|
|
|
|
.probe = uniphier_fi2c_probe,
|
|
|
|
.remove = uniphier_fi2c_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "uniphier-fi2c",
|
|
|
|
.of_match_table = uniphier_fi2c_match,
|
2017-07-31 13:53:07 +08:00
|
|
|
.pm = &uniphier_fi2c_pm_ops,
|
2015-10-23 18:52:00 +08:00
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(uniphier_fi2c_drv);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
|
|
|
MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
|
|
|
|
MODULE_LICENSE("GPL");
|