2019-06-01 16:08:55 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2016-06-23 00:25:06 +08:00
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/*
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* bpf_jit.h: BPF JIT compiler for PPC
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2011-07-20 23:51:00 +08:00
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*
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* Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
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2016-06-23 00:25:07 +08:00
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* 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
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2011-07-20 23:51:00 +08:00
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*/
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#ifndef _BPF_JIT_H
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#define _BPF_JIT_H
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#ifndef __ASSEMBLY__
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2016-06-23 00:25:07 +08:00
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#include <asm/types.h>
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2020-06-24 19:30:35 +08:00
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#include <asm/ppc-opcode.h>
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2016-06-23 00:25:07 +08:00
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#ifdef PPC64_ELF_ABI_v1
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2011-07-20 23:51:00 +08:00
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#define FUNCTION_DESCR_SIZE 24
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2015-02-17 15:04:40 +08:00
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#else
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#define FUNCTION_DESCR_SIZE 0
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#endif
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2011-07-20 23:51:00 +08:00
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#define PLANT_INSTR(d, idx, instr) \
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do { if (d) { (d)[idx] = instr; } idx++; } while (0)
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#define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
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/* Long jump; (unconditional 'branch') */
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2021-10-06 04:25:21 +08:00
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#define PPC_JMP(dest) \
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do { \
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long offset = (long)(dest) - (ctx->idx * 4); \
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if (!is_offset_in_branch_range(offset)) { \
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pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
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return -ERANGE; \
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} \
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2021-10-12 20:30:52 +08:00
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EMIT(PPC_RAW_BRANCH(offset)); \
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2021-10-06 04:25:21 +08:00
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} while (0)
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2021-04-12 19:44:18 +08:00
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/* blr; (unconditional 'branch' with link) to absolute address */
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#define PPC_BL_ABS(dest) EMIT(PPC_INST_BL | \
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(((dest) - (unsigned long)(image + ctx->idx)) & 0x03fffffc))
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2011-07-20 23:51:00 +08:00
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/* "cond" here covers BO:BI fields. */
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2021-10-06 04:25:21 +08:00
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#define PPC_BCC_SHORT(cond, dest) \
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do { \
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long offset = (long)(dest) - (ctx->idx * 4); \
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if (!is_offset_in_cond_branch_range(offset)) { \
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pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
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return -ERANGE; \
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} \
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EMIT(PPC_INST_BRANCH_COND | (((cond) & 0x3ff) << 16) | (offset & 0xfffc)); \
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} while (0)
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2016-06-23 00:25:02 +08:00
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/* Sign-extended 32-bit immediate load */
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#define PPC_LI32(d, i) do { \
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if ((int)(uintptr_t)(i) >= -32768 && \
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(int)(uintptr_t)(i) < 32768) \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_LI(d, i)); \
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2016-06-23 00:25:02 +08:00
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else { \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_LIS(d, IMM_H(i))); \
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2016-06-23 00:25:02 +08:00
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if (IMM_L(i)) \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_ORI(d, d, IMM_L(i))); \
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2011-07-20 23:51:00 +08:00
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} } while(0)
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2016-06-23 00:25:02 +08:00
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2021-03-23 00:37:52 +08:00
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#ifdef CONFIG_PPC32
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#define PPC_EX32(r, i) EMIT(PPC_RAW_LI((r), (i) < 0 ? -1 : 0))
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#endif
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2011-07-20 23:51:00 +08:00
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#define PPC_LI64(d, i) do { \
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2016-06-23 00:25:03 +08:00
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if ((long)(i) >= -2147483648 && \
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(long)(i) < 2147483648) \
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2011-07-20 23:51:00 +08:00
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PPC_LI32(d, i); \
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else { \
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2016-06-23 00:25:03 +08:00
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if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_LI(d, ((uintptr_t)(i) >> 32) & \
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0xffff)); \
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2016-06-23 00:25:03 +08:00
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else { \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_LIS(d, ((uintptr_t)(i) >> 48))); \
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2016-06-23 00:25:03 +08:00
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if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_ORI(d, d, \
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((uintptr_t)(i) >> 32) & 0xffff)); \
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2016-06-23 00:25:03 +08:00
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} \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_SLDI(d, d, 32)); \
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2011-07-20 23:51:00 +08:00
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if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_ORIS(d, d, \
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((uintptr_t)(i) >> 16) & 0xffff)); \
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2011-07-20 23:51:00 +08:00
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if ((uintptr_t)(i) & 0x000000000000ffffULL) \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_ORI(d, d, (uintptr_t)(i) & \
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0xffff)); \
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2016-06-23 00:25:03 +08:00
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} } while (0)
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2011-07-20 23:51:00 +08:00
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2015-02-17 15:04:40 +08:00
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#ifdef CONFIG_PPC64
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#define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0)
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#else
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#define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0)
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#endif
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2011-07-20 23:51:00 +08:00
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/*
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* The fly in the ointment of code size changing from pass to pass is
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* avoided by padding the short branch case with a NOP. If code size differs
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* with different branch reaches we will have the issue of code moving from
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* one pass to the next and will need a few passes to converge on a stable
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* state.
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*/
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#define PPC_BCC(cond, dest) do { \
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2021-10-06 04:25:20 +08:00
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if (is_offset_in_cond_branch_range((long)(dest) - (ctx->idx * 4))) { \
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2011-07-20 23:51:00 +08:00
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PPC_BCC_SHORT(cond, dest); \
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2020-06-24 19:30:36 +08:00
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EMIT(PPC_RAW_NOP()); \
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2011-07-20 23:51:00 +08:00
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} else { \
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/* Flip the 'T or F' bit to invert comparison */ \
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PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \
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PPC_JMP(dest); \
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} } while(0)
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/* To create a branch condition, select a bit of cr0... */
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#define CR0_LT 0
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#define CR0_GT 1
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#define CR0_EQ 2
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/* ...and modify BO[3] */
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#define COND_CMP_TRUE 0x100
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#define COND_CMP_FALSE 0x000
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/* Together, they make all required comparisons: */
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#define COND_GT (CR0_GT | COND_CMP_TRUE)
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#define COND_GE (CR0_LT | COND_CMP_FALSE)
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#define COND_EQ (CR0_EQ | COND_CMP_TRUE)
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#define COND_NE (CR0_EQ | COND_CMP_FALSE)
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#define COND_LT (CR0_LT | COND_CMP_TRUE)
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2017-08-10 07:40:00 +08:00
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#define COND_LE (CR0_GT | COND_CMP_FALSE)
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2011-07-20 23:51:00 +08:00
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2021-03-23 00:37:50 +08:00
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#define SEEN_FUNC 0x20000000 /* might call external helpers */
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2021-10-12 20:30:49 +08:00
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#define SEEN_TAILCALL 0x40000000 /* uses tail calls */
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2021-03-23 00:37:48 +08:00
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powerpc/bpf: Reallocate BPF registers to volatile registers when possible on PPC32
When the BPF routine doesn't call any function, the non volatile
registers can be reallocated to volatile registers in order to
avoid having to save them/restore on the stack.
Before this patch, the test #359 ADD default X is:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 92 e1 00 2c stw r23,44(r1)
14: 93 01 00 30 stw r24,48(r1)
18: 93 21 00 34 stw r25,52(r1)
1c: 93 41 00 38 stw r26,56(r1)
20: 39 80 00 00 li r12,0
24: 39 60 00 00 li r11,0
28: 3b 40 00 00 li r26,0
2c: 3b 20 00 00 li r25,0
30: 7c 98 23 78 mr r24,r4
34: 7c 77 1b 78 mr r23,r3
38: 39 80 00 42 li r12,66
3c: 39 60 00 00 li r11,0
40: 7d 8c d2 14 add r12,r12,r26
44: 39 60 00 00 li r11,0
48: 7d 83 63 78 mr r3,r12
4c: 82 e1 00 2c lwz r23,44(r1)
50: 83 01 00 30 lwz r24,48(r1)
54: 83 21 00 34 lwz r25,52(r1)
58: 83 41 00 38 lwz r26,56(r1)
5c: 38 21 00 50 addi r1,r1,80
60: 4e 80 00 20 blr
After this patch, the same test has become:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 39 80 00 00 li r12,0
14: 39 60 00 00 li r11,0
18: 39 00 00 00 li r8,0
1c: 38 e0 00 00 li r7,0
20: 7c 86 23 78 mr r6,r4
24: 7c 65 1b 78 mr r5,r3
28: 39 80 00 42 li r12,66
2c: 39 60 00 00 li r11,0
30: 7d 8c 42 14 add r12,r12,r8
34: 39 60 00 00 li r11,0
38: 7d 83 63 78 mr r3,r12
3c: 38 21 00 50 addi r1,r1,80
40: 4e 80 00 20 blr
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b94562d7d2bb21aec89de0c40bb3cd91054b65a2.1616430991.git.christophe.leroy@csgroup.eu
2021-03-23 00:37:53 +08:00
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#define SEEN_VREG_MASK 0x1ff80000 /* Volatile registers r3-r12 */
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#define SEEN_NVREG_MASK 0x0003ffff /* Non volatile registers r14-r31 */
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#ifdef CONFIG_PPC64
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extern const int b2p[MAX_BPF_JIT_REG + 2];
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#else
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extern const int b2p[MAX_BPF_JIT_REG + 1];
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#endif
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2021-03-23 00:37:48 +08:00
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struct codegen_context {
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/*
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* This is used to track register usage as well
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* as calls to external helpers.
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* - register usage is tracked with corresponding
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2021-03-23 00:37:50 +08:00
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* bits (r3-r31)
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2021-03-23 00:37:48 +08:00
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* - rest of the bits can be used to track other
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2021-03-23 00:37:50 +08:00
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* things -- for now, we use bits 0 to 2
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2021-03-23 00:37:48 +08:00
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* encoded in SEEN_* macros above
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*/
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unsigned int seen;
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unsigned int idx;
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unsigned int stack_size;
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powerpc/bpf: Reallocate BPF registers to volatile registers when possible on PPC32
When the BPF routine doesn't call any function, the non volatile
registers can be reallocated to volatile registers in order to
avoid having to save them/restore on the stack.
Before this patch, the test #359 ADD default X is:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 92 e1 00 2c stw r23,44(r1)
14: 93 01 00 30 stw r24,48(r1)
18: 93 21 00 34 stw r25,52(r1)
1c: 93 41 00 38 stw r26,56(r1)
20: 39 80 00 00 li r12,0
24: 39 60 00 00 li r11,0
28: 3b 40 00 00 li r26,0
2c: 3b 20 00 00 li r25,0
30: 7c 98 23 78 mr r24,r4
34: 7c 77 1b 78 mr r23,r3
38: 39 80 00 42 li r12,66
3c: 39 60 00 00 li r11,0
40: 7d 8c d2 14 add r12,r12,r26
44: 39 60 00 00 li r11,0
48: 7d 83 63 78 mr r3,r12
4c: 82 e1 00 2c lwz r23,44(r1)
50: 83 01 00 30 lwz r24,48(r1)
54: 83 21 00 34 lwz r25,52(r1)
58: 83 41 00 38 lwz r26,56(r1)
5c: 38 21 00 50 addi r1,r1,80
60: 4e 80 00 20 blr
After this patch, the same test has become:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 39 80 00 00 li r12,0
14: 39 60 00 00 li r11,0
18: 39 00 00 00 li r8,0
1c: 38 e0 00 00 li r7,0
20: 7c 86 23 78 mr r6,r4
24: 7c 65 1b 78 mr r5,r3
28: 39 80 00 42 li r12,66
2c: 39 60 00 00 li r11,0
30: 7d 8c 42 14 add r12,r12,r8
34: 39 60 00 00 li r11,0
38: 7d 83 63 78 mr r3,r12
3c: 38 21 00 50 addi r1,r1,80
40: 4e 80 00 20 blr
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b94562d7d2bb21aec89de0c40bb3cd91054b65a2.1616430991.git.christophe.leroy@csgroup.eu
2021-03-23 00:37:53 +08:00
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int b2p[ARRAY_SIZE(b2p)];
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2021-10-12 20:30:53 +08:00
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unsigned int exentry_idx;
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2021-03-23 00:37:48 +08:00
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};
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bpf ppc32: Add BPF_PROBE_MEM support for JIT
BPF load instruction with BPF_PROBE_MEM mode can cause a fault
inside kernel. Append exception table for such instructions
within BPF program.
Unlike other archs which uses extable 'fixup' field to pass dest_reg
and nip, BPF exception table on PowerPC follows the generic PowerPC
exception table design, where it populates both fixup and extable
sections within BPF program. fixup section contains 3 instructions,
first 2 instructions clear dest_reg (lower & higher 32-bit registers)
and last instruction jumps to next instruction in the BPF code.
extable 'insn' field contains relative offset of the instruction and
'fixup' field contains relative offset of the fixup entry. Example
layout of BPF program with extable present:
+------------------+
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0x4020 -->| lwz r28,4(r4) |
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0x40ac -->| lwz r3,0(r24) |
| lwz r4,4(r24) |
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|------------------|
0x4278 -->| li r28,0 | \
| li r27,0 | | fixup entry
| b 0x4024 | /
0x4284 -->| li r4,0 |
| li r3,0 |
| b 0x40b4 |
|------------------|
0x4290 -->| insn=0xfffffd90 | \ extable entry
| fixup=0xffffffe4 | /
0x4298 -->| insn=0xfffffe14 |
| fixup=0xffffffe8 |
+------------------+
(Addresses shown here are chosen random, not real)
Signed-off-by: Hari Bathini <hbathini@linux.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211012123056.485795-8-hbathini@linux.ibm.com
2021-10-12 20:30:55 +08:00
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#ifdef CONFIG_PPC32
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#define BPF_FIXUP_LEN 3 /* Three instructions => 12 bytes */
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#else
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2021-10-12 20:30:53 +08:00
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#define BPF_FIXUP_LEN 2 /* Two instructions => 8 bytes */
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bpf ppc32: Add BPF_PROBE_MEM support for JIT
BPF load instruction with BPF_PROBE_MEM mode can cause a fault
inside kernel. Append exception table for such instructions
within BPF program.
Unlike other archs which uses extable 'fixup' field to pass dest_reg
and nip, BPF exception table on PowerPC follows the generic PowerPC
exception table design, where it populates both fixup and extable
sections within BPF program. fixup section contains 3 instructions,
first 2 instructions clear dest_reg (lower & higher 32-bit registers)
and last instruction jumps to next instruction in the BPF code.
extable 'insn' field contains relative offset of the instruction and
'fixup' field contains relative offset of the fixup entry. Example
layout of BPF program with extable present:
+------------------+
| |
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0x4020 -->| lwz r28,4(r4) |
| |
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0x40ac -->| lwz r3,0(r24) |
| lwz r4,4(r24) |
| |
| |
|------------------|
0x4278 -->| li r28,0 | \
| li r27,0 | | fixup entry
| b 0x4024 | /
0x4284 -->| li r4,0 |
| li r3,0 |
| b 0x40b4 |
|------------------|
0x4290 -->| insn=0xfffffd90 | \ extable entry
| fixup=0xffffffe4 | /
0x4298 -->| insn=0xfffffe14 |
| fixup=0xffffffe8 |
+------------------+
(Addresses shown here are chosen random, not real)
Signed-off-by: Hari Bathini <hbathini@linux.ibm.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211012123056.485795-8-hbathini@linux.ibm.com
2021-10-12 20:30:55 +08:00
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#endif
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2021-10-12 20:30:53 +08:00
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2021-03-23 00:37:48 +08:00
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static inline void bpf_flush_icache(void *start, void *end)
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{
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smp_wmb(); /* smp write barrier */
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flush_icache_range((unsigned long)start, (unsigned long)end);
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}
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static inline bool bpf_is_seen_register(struct codegen_context *ctx, int i)
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{
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return ctx->seen & (1 << (31 - i));
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}
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static inline void bpf_set_seen_register(struct codegen_context *ctx, int i)
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{
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ctx->seen |= 1 << (31 - i);
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}
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powerpc/bpf: Reallocate BPF registers to volatile registers when possible on PPC32
When the BPF routine doesn't call any function, the non volatile
registers can be reallocated to volatile registers in order to
avoid having to save them/restore on the stack.
Before this patch, the test #359 ADD default X is:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 92 e1 00 2c stw r23,44(r1)
14: 93 01 00 30 stw r24,48(r1)
18: 93 21 00 34 stw r25,52(r1)
1c: 93 41 00 38 stw r26,56(r1)
20: 39 80 00 00 li r12,0
24: 39 60 00 00 li r11,0
28: 3b 40 00 00 li r26,0
2c: 3b 20 00 00 li r25,0
30: 7c 98 23 78 mr r24,r4
34: 7c 77 1b 78 mr r23,r3
38: 39 80 00 42 li r12,66
3c: 39 60 00 00 li r11,0
40: 7d 8c d2 14 add r12,r12,r26
44: 39 60 00 00 li r11,0
48: 7d 83 63 78 mr r3,r12
4c: 82 e1 00 2c lwz r23,44(r1)
50: 83 01 00 30 lwz r24,48(r1)
54: 83 21 00 34 lwz r25,52(r1)
58: 83 41 00 38 lwz r26,56(r1)
5c: 38 21 00 50 addi r1,r1,80
60: 4e 80 00 20 blr
After this patch, the same test has become:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 39 80 00 00 li r12,0
14: 39 60 00 00 li r11,0
18: 39 00 00 00 li r8,0
1c: 38 e0 00 00 li r7,0
20: 7c 86 23 78 mr r6,r4
24: 7c 65 1b 78 mr r5,r3
28: 39 80 00 42 li r12,66
2c: 39 60 00 00 li r11,0
30: 7d 8c 42 14 add r12,r12,r8
34: 39 60 00 00 li r11,0
38: 7d 83 63 78 mr r3,r12
3c: 38 21 00 50 addi r1,r1,80
40: 4e 80 00 20 blr
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b94562d7d2bb21aec89de0c40bb3cd91054b65a2.1616430991.git.christophe.leroy@csgroup.eu
2021-03-23 00:37:53 +08:00
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static inline void bpf_clear_seen_register(struct codegen_context *ctx, int i)
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{
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ctx->seen &= ~(1 << (31 - i));
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}
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2021-03-23 00:37:49 +08:00
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void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func);
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int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx,
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2021-10-12 20:30:53 +08:00
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u32 *addrs, int pass);
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2021-03-23 00:37:49 +08:00
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void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx);
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void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx);
|
powerpc/bpf: Reallocate BPF registers to volatile registers when possible on PPC32
When the BPF routine doesn't call any function, the non volatile
registers can be reallocated to volatile registers in order to
avoid having to save them/restore on the stack.
Before this patch, the test #359 ADD default X is:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 92 e1 00 2c stw r23,44(r1)
14: 93 01 00 30 stw r24,48(r1)
18: 93 21 00 34 stw r25,52(r1)
1c: 93 41 00 38 stw r26,56(r1)
20: 39 80 00 00 li r12,0
24: 39 60 00 00 li r11,0
28: 3b 40 00 00 li r26,0
2c: 3b 20 00 00 li r25,0
30: 7c 98 23 78 mr r24,r4
34: 7c 77 1b 78 mr r23,r3
38: 39 80 00 42 li r12,66
3c: 39 60 00 00 li r11,0
40: 7d 8c d2 14 add r12,r12,r26
44: 39 60 00 00 li r11,0
48: 7d 83 63 78 mr r3,r12
4c: 82 e1 00 2c lwz r23,44(r1)
50: 83 01 00 30 lwz r24,48(r1)
54: 83 21 00 34 lwz r25,52(r1)
58: 83 41 00 38 lwz r26,56(r1)
5c: 38 21 00 50 addi r1,r1,80
60: 4e 80 00 20 blr
After this patch, the same test has become:
0: 7c 64 1b 78 mr r4,r3
4: 38 60 00 00 li r3,0
8: 94 21 ff b0 stwu r1,-80(r1)
c: 60 00 00 00 nop
10: 39 80 00 00 li r12,0
14: 39 60 00 00 li r11,0
18: 39 00 00 00 li r8,0
1c: 38 e0 00 00 li r7,0
20: 7c 86 23 78 mr r6,r4
24: 7c 65 1b 78 mr r5,r3
28: 39 80 00 42 li r12,66
2c: 39 60 00 00 li r11,0
30: 7d 8c 42 14 add r12,r12,r8
34: 39 60 00 00 li r11,0
38: 7d 83 63 78 mr r3,r12
3c: 38 21 00 50 addi r1,r1,80
40: 4e 80 00 20 blr
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b94562d7d2bb21aec89de0c40bb3cd91054b65a2.1616430991.git.christophe.leroy@csgroup.eu
2021-03-23 00:37:53 +08:00
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void bpf_jit_realloc_regs(struct codegen_context *ctx);
|
2021-03-23 00:37:49 +08:00
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2021-10-12 20:30:53 +08:00
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int bpf_add_extable_entry(struct bpf_prog *fp, u32 *image, int pass, struct codegen_context *ctx,
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int insn_idx, int jmp_off, int dst_reg);
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2011-07-20 23:51:00 +08:00
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#endif
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#endif
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