2019-05-27 14:55:01 +08:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2005-09-26 14:04:21 +08:00
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/*
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* FPU support code, moved here from head.S so that it can be used
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* by chips which use other head-whatever.S files.
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*
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2006-08-30 12:45:35 +08:00
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Copyright (C) 1996 Paul Mackerras.
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* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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2005-09-26 14:04:21 +08:00
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*/
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2005-10-10 20:20:10 +08:00
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#include <asm/reg.h>
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2005-09-26 14:04:21 +08:00
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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2010-11-18 23:06:17 +08:00
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#include <asm/ptrace.h>
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2016-01-14 12:33:46 +08:00
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#include <asm/export.h>
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2018-07-06 00:24:57 +08:00
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#include <asm/asm-compat.h>
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2018-07-06 00:25:01 +08:00
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#include <asm/feature-fixups.h>
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2005-09-26 14:04:21 +08:00
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2008-06-25 12:07:18 +08:00
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#ifdef CONFIG_VSX
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2012-06-25 21:33:23 +08:00
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#define __REST_32FPVSRS(n,c,base) \
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2008-06-25 12:07:18 +08:00
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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2012-06-25 21:33:23 +08:00
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#define __SAVE_32FPVSRS(n,c,base) \
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2008-06-25 12:07:18 +08:00
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS(n,base); \
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b 3f; \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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2012-06-25 21:33:23 +08:00
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#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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2008-06-25 12:07:18 +08:00
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#endif
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2012-06-25 21:33:23 +08:00
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#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
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#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
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2008-06-25 12:07:18 +08:00
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2013-09-10 18:21:10 +08:00
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/*
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* Load state from memory into FP registers including FPSCR.
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(load_fp_state)
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lfd fr0,FPSTATE_FPSCR(r3)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R3)
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blr
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2016-01-14 12:33:46 +08:00
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EXPORT_SYMBOL(load_fp_state)
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powerpc/64: Don't trace code that runs with the soft irq mask unreconciled
"Reconciling" in terms of interrupt handling, is to bring the soft irq
mask state in to synch with the hardware, after an interrupt causes
MSR[EE] to be cleared (while the soft mask may be enabled, and hard
irqs not marked disabled).
General kernel code should not be called while unreconciled, because
local_irq_disable, etc. manipulations can cause surprising irq traces,
and it's fragile because the soft irq code does not really expect to
be called in this situation.
When exiting from an interrupt, MSR[EE] is cleared to prevent races,
but soft irq state is enabled for the returned-to context, so this is
now an unreconciled state. restore_math is called in this state, and
that can be ftraced, and the ftrace subsystem disables local irqs.
Mark restore_math and its callees as notrace. Restore a sanity check
in the soft irq code that had to be disabled for this case, by commit
4da1f79227ad4 ("powerpc/64: Disable irq restore warning for now").
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-05-02 13:21:07 +08:00
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_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */
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2013-09-10 18:21:10 +08:00
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/*
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* Store FP state into memory, including FPSCR
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(store_fp_state)
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SAVE_32FPVSRS(0, R4, R3)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r3)
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blr
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2016-01-14 12:33:46 +08:00
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EXPORT_SYMBOL(store_fp_state)
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2013-09-10 18:21:10 +08:00
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2005-09-26 14:04:21 +08:00
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Load up this task's FP registers from its thread_struct,
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* enable the FPU for the current task and return to the task.
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2013-10-23 16:40:02 +08:00
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* Note that on 32-bit this can only use registers that will be
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* restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
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2005-09-26 14:04:21 +08:00
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*/
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2005-10-06 08:59:19 +08:00
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_GLOBAL(load_up_fpu)
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2005-09-26 14:04:21 +08:00
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mfmsr r5
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powerpc/64s/interrupt: handle MSR EE and RI in interrupt entry wrapper
The mtmsrd to enable MSR[RI] can be combined with the mtmsrd to enable
MSR[EE] in interrupt entry code, for those interrupts which enable EE.
This helps performance of important synchronous interrupts (e.g., page
faults).
This is similar to what commit dd152f70bdc1 ("powerpc/64s: system call
avoid setting MSR[RI] until we set MSR[EE]") does for system calls.
Do this by enabling EE and RI together at the beginning of the entry
wrapper if PACA_IRQ_HARD_DIS is clear, and only enabling RI if it is
set.
Asynchronous interrupts set PACA_IRQ_HARD_DIS, but synchronous ones
leave it unchanged, so by default they always get EE=1 unless they have
interrupted a caller that is hard disabled. When the sync interrupt
later calls interrupt_cond_local_irq_enable(), it will not require
another mtmsrd because MSR[EE] was already enabled here.
This avoids one mtmsrd L=1 for synchronous interrupts on 64s, which
saves about 20 cycles on POWER9. And for kernel-mode interrupts, both
synchronous and asynchronous, this saves an additional 40 cycles due to
the mtmsrd being moved ahead of mfspr SPRN_AMR, which prevents a SPR
scoreboard stall.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210922145452.352571-3-npiggin@gmail.com
2021-09-22 22:54:48 +08:00
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#ifdef CONFIG_PPC_BOOK3S_64
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/* interrupt doesn't set MSR[RI] and HPT can fault on current access */
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ori r5,r5,MSR_FP|MSR_RI
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#else
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2005-09-26 14:04:21 +08:00
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ori r5,r5,MSR_FP
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powerpc/64s/interrupt: handle MSR EE and RI in interrupt entry wrapper
The mtmsrd to enable MSR[RI] can be combined with the mtmsrd to enable
MSR[EE] in interrupt entry code, for those interrupts which enable EE.
This helps performance of important synchronous interrupts (e.g., page
faults).
This is similar to what commit dd152f70bdc1 ("powerpc/64s: system call
avoid setting MSR[RI] until we set MSR[EE]") does for system calls.
Do this by enabling EE and RI together at the beginning of the entry
wrapper if PACA_IRQ_HARD_DIS is clear, and only enabling RI if it is
set.
Asynchronous interrupts set PACA_IRQ_HARD_DIS, but synchronous ones
leave it unchanged, so by default they always get EE=1 unless they have
interrupted a caller that is hard disabled. When the sync interrupt
later calls interrupt_cond_local_irq_enable(), it will not require
another mtmsrd because MSR[EE] was already enabled here.
This avoids one mtmsrd L=1 for synchronous interrupts on 64s, which
saves about 20 cycles on POWER9. And for kernel-mode interrupts, both
synchronous and asynchronous, this saves an additional 40 cycles due to
the mtmsrd being moved ahead of mfspr SPRN_AMR, which prevents a SPR
scoreboard stall.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210922145452.352571-3-npiggin@gmail.com
2021-09-22 22:54:48 +08:00
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#endif
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2008-06-25 12:07:18 +08:00
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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2005-09-26 14:04:21 +08:00
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MTMSRD(r5) /* enable use of fpu now */
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isync
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/* enable use of FP after return */
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2005-10-06 08:59:19 +08:00
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#ifdef CONFIG_PPC32
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2021-08-18 16:47:28 +08:00
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addi r5,r2,THREAD
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2005-09-26 14:04:21 +08:00
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r9,r9,MSR_FP /* enable FP for current */
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or r9,r9,r4
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2005-10-06 08:59:19 +08:00
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#else
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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2006-02-07 10:55:30 +08:00
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lwz r4,THREAD_FPEXC_MODE(r5)
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2005-10-06 08:59:19 +08:00
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ori r12,r12,MSR_FP
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or r12,r12,r4
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std r12,_MSR(r1)
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2021-06-17 23:51:03 +08:00
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#ifdef CONFIG_PPC_BOOK3S_64
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li r4,0
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stb r4,PACASRR_VALID(r13)
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#endif
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2005-10-06 08:59:19 +08:00
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#endif
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2020-06-24 07:41:39 +08:00
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li r4,1
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2016-02-29 14:53:47 +08:00
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stb r4,THREAD_LOAD_FP(r5)
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2013-10-23 16:40:02 +08:00
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addi r10,r5,THREAD_FPSTATE
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lfd fr0,FPSTATE_FPSCR(r10)
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2006-06-10 18:18:39 +08:00
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MTFSF_L(fr0)
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2013-10-23 16:40:02 +08:00
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REST_32FPVSRS(0, R4, R10)
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2005-09-26 14:04:21 +08:00
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/* restore registers and return */
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/* we haven't used ctr or xer or lr */
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2008-06-25 12:07:18 +08:00
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blr
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2020-04-01 00:03:44 +08:00
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_ASM_NOKPROBE_SYMBOL(load_up_fpu)
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2005-09-26 14:04:21 +08:00
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/*
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2016-02-29 14:53:49 +08:00
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* save_fpu(tsk)
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* Save the floating-point registers in its thread_struct.
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2005-09-26 14:04:21 +08:00
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* Enables the FPU for use in the kernel on return.
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*/
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2016-02-29 14:53:49 +08:00
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_GLOBAL(save_fpu)
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2005-09-26 14:04:21 +08:00
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addi r3,r3,THREAD /* want THREAD of task */
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2013-09-10 18:21:10 +08:00
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PPC_LL r6,THREAD_FPSAVEAREA(r3)
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[PATCH] powerpc: Consolidate asm compatibility macros
This patch consolidates macros used to generate assembly for
compatibility across different CPUs or configs. A new header,
asm-powerpc/asm-compat.h contains the main compatibility macros. It
uses some preprocessor magic to make the macros suitable both for use
in .S files, and in inline asm in .c files. Headers (bitops.h,
uaccess.h, atomic.h, bug.h) which had their own such compatibility
macros are changed to use asm-compat.h.
ppc_asm.h is now for use in .S files *only*, and a #error enforces
that. As such, we're a lot more careless about namespace pollution
here than in asm-compat.h.
While we're at it, this patch adds a call to the PPC405_ERR77 macro in
futex.h which should have had it already, but didn't.
Built and booted on pSeries, Maple and iSeries (ARCH=powerpc). Built
for 32-bit powermac (ARCH=powerpc) and Walnut (ARCH=ppc).
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-10 09:56:55 +08:00
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PPC_LL r5,PT_REGS(r3)
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2013-09-10 18:21:10 +08:00
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PPC_LCMPI 0,r6,0
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bne 2f
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2013-09-10 18:20:42 +08:00
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addi r6,r3,THREAD_FPSTATE
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2016-02-29 14:53:49 +08:00
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2: SAVE_32FPVSRS(0, R4, R6)
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2005-09-26 14:04:21 +08:00
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mffs fr0
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2013-09-10 18:20:42 +08:00
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stfd fr0,FPSTATE_FPSCR(r6)
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2005-09-26 14:04:21 +08:00
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blr
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