51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
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/*
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* include/asm-v850/ma1.h -- V850E/MA1 cpu chip
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_MA1_H__
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#define __V850_MA1_H__
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/* Inherit more generic details from MA series. */
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#include <asm/ma.h>
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#define CPU_MODEL "v850e/ma1"
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#define CPU_MODEL_LONG "NEC V850E/MA1"
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/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
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#define IRQ_INTOV(n) (n) /* 0-3 */
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#define IRQ_INTOV_NUM 4
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#define IRQ_INTP(n) (0x4 + (n)) /* Pnnn (pin) interrupts */
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#define IRQ_INTP_NUM 24
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#define IRQ_INTCMD(n) (0x1c + (n)) /* interval timer interrupts 0-3 */
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#define IRQ_INTCMD_NUM 4
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#define IRQ_INTDMA(n) (0x20 + (n)) /* DMA interrupts 0-3 */
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#define IRQ_INTDMA_NUM 4
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#define IRQ_INTCSI(n) (0x24 + (n)*4)/* CSI 0-2 transmit/receive completion */
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#define IRQ_INTCSI_NUM 3
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#define IRQ_INTSER(n) (0x25 + (n)*4) /* UART 0-2 reception error */
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#define IRQ_INTSER_NUM 3
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#define IRQ_INTSR(n) (0x26 + (n)*4) /* UART 0-2 reception completion */
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#define IRQ_INTSR_NUM 3
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#define IRQ_INTST(n) (0x27 + (n)*4) /* UART 0-2 transmission completion */
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#define IRQ_INTST_NUM 3
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#define NUM_CPU_IRQS 0x30
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/* The MA1 has a UART with 3 channels. */
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#define V850E_UART_NUM_CHANNELS 3
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#endif /* __V850_MA1_H__ */
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