2014-08-22 18:36:26 +08:00
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drm/drm.h>
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#include <drm/drmP.h>
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2015-11-30 18:22:42 +08:00
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#include <drm/drm_atomic.h>
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2014-08-22 18:36:26 +08:00
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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2016-09-14 20:54:57 +08:00
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#include <drm/drm_flip_work.h>
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2014-08-22 18:36:26 +08:00
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#include <drm/drm_plane_helper.h>
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2017-03-07 04:02:26 +08:00
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#ifdef CONFIG_DRM_ANALOGIX_DP
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2017-03-03 21:39:36 +08:00
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#include <drm/bridge/analogix_dp.h>
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2017-03-07 04:02:26 +08:00
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#endif
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2014-08-22 18:36:26 +08:00
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#include <linux/kernel.h>
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2015-05-02 08:02:30 +08:00
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#include <linux/module.h>
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2014-08-22 18:36:26 +08:00
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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2016-09-14 20:54:56 +08:00
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#include <linux/iopoll.h>
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2014-08-22 18:36:26 +08:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/component.h>
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#include <linux/reset.h>
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#include <linux/delay.h>
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#include "rockchip_drm_drv.h"
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#include "rockchip_drm_gem.h"
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#include "rockchip_drm_fb.h"
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2016-07-24 14:57:44 +08:00
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#include "rockchip_drm_psr.h"
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2014-08-22 18:36:26 +08:00
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#include "rockchip_drm_vop.h"
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#define VOP_WIN_SET(x, win, name, v) \
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2017-07-28 14:06:25 +08:00
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vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
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2015-06-26 17:14:46 +08:00
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#define VOP_SCL_SET(x, win, name, v) \
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2017-07-28 14:06:25 +08:00
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vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
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2015-12-15 09:08:43 +08:00
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#define VOP_SCL_SET_EXT(x, win, name, v) \
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2017-07-28 14:06:25 +08:00
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vop_reg_set(vop, &win->phy->scl->ext->name, \
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win->base, ~0, v, #name)
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2017-07-26 14:19:19 +08:00
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#define VOP_INTR_SET_MASK(vop, name, mask, v) \
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2017-07-28 14:06:25 +08:00
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vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
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#define VOP_REG_SET(vop, group, name, v) \
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vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
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2017-07-26 14:19:19 +08:00
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2015-12-15 08:36:55 +08:00
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#define VOP_INTR_SET_TYPE(vop, name, type, v) \
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do { \
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2016-01-13 02:05:18 +08:00
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int i, reg = 0, mask = 0; \
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2015-12-15 08:36:55 +08:00
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for (i = 0; i < vop->data->intr->nintrs; i++) { \
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2016-01-13 02:05:18 +08:00
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if (vop->data->intr->intrs[i] & type) { \
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2015-12-15 08:36:55 +08:00
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reg |= (v) << i; \
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2016-01-13 02:05:18 +08:00
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mask |= 1 << i; \
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} \
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2015-12-15 08:36:55 +08:00
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} \
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2017-07-26 14:19:19 +08:00
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VOP_INTR_SET_MASK(vop, name, mask, reg); \
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2015-12-15 08:36:55 +08:00
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} while (0)
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#define VOP_INTR_GET_TYPE(vop, name, type) \
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vop_get_intr_type(vop, &vop->data->intr->name, type)
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2014-08-22 18:36:26 +08:00
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#define VOP_WIN_GET(x, win, name) \
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2017-07-28 14:06:25 +08:00
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vop_read_reg(x, win->offset, win->phy->name)
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2014-08-22 18:36:26 +08:00
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#define VOP_WIN_GET_YRGBADDR(vop, win) \
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vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
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#define to_vop(x) container_of(x, struct vop, crtc)
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#define to_vop_win(x) container_of(x, struct vop_win, base)
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2016-09-14 20:54:57 +08:00
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enum vop_pending {
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VOP_PENDING_FB_UNREF,
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};
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2014-08-22 18:36:26 +08:00
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struct vop_win {
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struct drm_plane base;
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const struct vop_win_data *data;
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struct vop *vop;
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};
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struct vop {
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struct drm_crtc crtc;
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struct device *dev;
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struct drm_device *drm_dev;
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2015-01-22 14:37:56 +08:00
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bool is_enabled;
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2014-08-22 18:36:26 +08:00
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/* mutex vsync_ work */
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struct mutex vsync_mutex;
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bool vsync_work_pending;
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2015-02-04 13:10:31 +08:00
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struct completion dsp_hold_completion;
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2016-06-08 20:19:11 +08:00
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/* protected by dev->event_lock */
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2015-11-30 18:22:42 +08:00
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struct drm_pending_vblank_event *event;
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2014-08-22 18:36:26 +08:00
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2016-09-14 20:54:57 +08:00
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struct drm_flip_work fb_unref_work;
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unsigned long pending;
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2016-07-24 14:57:40 +08:00
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struct completion line_flag_completion;
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2014-08-22 18:36:26 +08:00
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const struct vop_data *data;
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uint32_t *regsbak;
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void __iomem *regs;
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/* physical map length of vop register */
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uint32_t len;
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/* one time only one process allowed to config the register */
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spinlock_t reg_lock;
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/* lock vop irq reg */
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spinlock_t irq_lock;
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unsigned int irq;
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/* vop AHP clk */
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struct clk *hclk;
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/* vop dclk */
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struct clk *dclk;
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/* vop share memory frequency */
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struct clk *aclk;
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/* vop dclk reset */
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struct reset_control *dclk_rst;
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struct vop_win win[];
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};
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static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
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{
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writel(v, vop->regs + offset);
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vop->regsbak[offset >> 2] = v;
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}
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static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
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{
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return readl(vop->regs + offset);
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}
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static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
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const struct vop_reg *reg)
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{
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return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
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}
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2017-07-28 14:06:25 +08:00
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static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
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uint32_t _offset, uint32_t _mask, uint32_t v,
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const char *reg_name)
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2014-08-22 18:36:26 +08:00
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{
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2017-07-28 14:06:25 +08:00
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int offset, mask, shift;
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if (!reg || !reg->mask) {
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2017-09-15 16:36:03 +08:00
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DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
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2016-04-20 14:18:15 +08:00
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return;
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2017-07-28 14:06:25 +08:00
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}
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offset = reg->offset + _offset;
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mask = reg->mask & _mask;
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shift = reg->shift;
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2014-08-22 18:36:26 +08:00
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2017-07-28 14:06:25 +08:00
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if (reg->write_mask) {
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2016-04-20 14:18:15 +08:00
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v = ((v << shift) & 0xffff) | (mask << (shift + 16));
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} else {
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2014-08-22 18:36:26 +08:00
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uint32_t cached_val = vop->regsbak[offset >> 2];
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2016-04-20 14:18:15 +08:00
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v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
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vop->regsbak[offset >> 2] = v;
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2014-08-22 18:36:26 +08:00
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}
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2016-04-20 14:18:15 +08:00
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2017-07-28 14:06:25 +08:00
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if (reg->relaxed)
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2016-04-20 14:18:15 +08:00
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writel_relaxed(v, vop->regs + offset);
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else
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writel(v, vop->regs + offset);
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2014-08-22 18:36:26 +08:00
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}
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2015-12-15 08:36:55 +08:00
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static inline uint32_t vop_get_intr_type(struct vop *vop,
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const struct vop_reg *reg, int type)
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{
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uint32_t i, ret = 0;
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uint32_t regs = vop_read_reg(vop, 0, reg);
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for (i = 0; i < vop->data->intr->nintrs; i++) {
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if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
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ret |= vop->data->intr->intrs[i];
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}
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return ret;
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}
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2015-12-14 18:14:36 +08:00
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static inline void vop_cfg_done(struct vop *vop)
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{
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2017-07-28 14:06:25 +08:00
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VOP_REG_SET(vop, common, cfg_done, 1);
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2015-12-14 18:14:36 +08:00
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}
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2015-05-11 18:55:39 +08:00
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static bool has_rb_swapped(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_BGR888:
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case DRM_FORMAT_BGR565:
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return true;
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default:
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return false;
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}
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}
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2014-08-22 18:36:26 +08:00
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static enum vop_data_format vop_convert_format(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ARGB8888:
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2015-05-11 18:55:39 +08:00
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_ABGR8888:
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2014-08-22 18:36:26 +08:00
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return VOP_FMT_ARGB8888;
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case DRM_FORMAT_RGB888:
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2015-05-11 18:55:39 +08:00
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case DRM_FORMAT_BGR888:
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2014-08-22 18:36:26 +08:00
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return VOP_FMT_RGB888;
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case DRM_FORMAT_RGB565:
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2015-05-11 18:55:39 +08:00
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case DRM_FORMAT_BGR565:
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2014-08-22 18:36:26 +08:00
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return VOP_FMT_RGB565;
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case DRM_FORMAT_NV12:
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return VOP_FMT_YUV420SP;
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case DRM_FORMAT_NV16:
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return VOP_FMT_YUV422SP;
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case DRM_FORMAT_NV24:
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return VOP_FMT_YUV444SP;
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default:
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2016-08-13 01:00:54 +08:00
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DRM_ERROR("unsupported format[%08x]\n", format);
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2014-08-22 18:36:26 +08:00
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return -EINVAL;
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}
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}
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2015-07-20 16:16:49 +08:00
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static bool is_yuv_support(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_NV16:
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case DRM_FORMAT_NV24:
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return true;
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default:
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return false;
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}
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}
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2014-08-22 18:36:26 +08:00
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static bool is_alpha_support(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_ARGB8888:
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2015-05-11 18:55:39 +08:00
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case DRM_FORMAT_ABGR8888:
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2014-08-22 18:36:26 +08:00
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return true;
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default:
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return false;
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}
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}
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2015-06-26 17:14:46 +08:00
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static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
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uint32_t dst, bool is_horizontal,
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int vsu_mode, int *vskiplines)
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{
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uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
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if (is_horizontal) {
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if (mode == SCALE_UP)
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val = GET_SCL_FT_BIC(src, dst);
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else if (mode == SCALE_DOWN)
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val = GET_SCL_FT_BILI_DN(src, dst);
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} else {
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if (mode == SCALE_UP) {
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if (vsu_mode == SCALE_UP_BIL)
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val = GET_SCL_FT_BILI_UP(src, dst);
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else
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val = GET_SCL_FT_BIC(src, dst);
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} else if (mode == SCALE_DOWN) {
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if (vskiplines) {
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*vskiplines = scl_get_vskiplines(src, dst);
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val = scl_get_bili_dn_vskip(src, dst,
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*vskiplines);
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} else {
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val = GET_SCL_FT_BILI_DN(src, dst);
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}
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}
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}
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return val;
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}
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static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
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uint32_t src_w, uint32_t src_h, uint32_t dst_w,
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uint32_t dst_h, uint32_t pixel_format)
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{
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uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
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uint16_t cbcr_hor_scl_mode = SCALE_NONE;
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uint16_t cbcr_ver_scl_mode = SCALE_NONE;
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int hsub = drm_format_horz_chroma_subsampling(pixel_format);
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int vsub = drm_format_vert_chroma_subsampling(pixel_format);
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|
|
bool is_yuv = is_yuv_support(pixel_format);
|
|
|
|
uint16_t cbcr_src_w = src_w / hsub;
|
|
|
|
uint16_t cbcr_src_h = src_h / vsub;
|
|
|
|
uint16_t vsu_mode;
|
|
|
|
uint16_t lb_mode;
|
|
|
|
uint32_t val;
|
2016-04-29 15:39:53 +08:00
|
|
|
int vskiplines = 0;
|
2015-06-26 17:14:46 +08:00
|
|
|
|
|
|
|
if (dst_w > 3840) {
|
2016-08-13 01:00:54 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
|
2015-06-26 17:14:46 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-12-15 09:08:43 +08:00
|
|
|
if (!win->phy->scl->ext) {
|
|
|
|
VOP_SCL_SET(vop, win, scale_yrgb_x,
|
|
|
|
scl_cal_scale2(src_w, dst_w));
|
|
|
|
VOP_SCL_SET(vop, win, scale_yrgb_y,
|
|
|
|
scl_cal_scale2(src_h, dst_h));
|
|
|
|
if (is_yuv) {
|
|
|
|
VOP_SCL_SET(vop, win, scale_cbcr_x,
|
2016-06-06 15:58:46 +08:00
|
|
|
scl_cal_scale2(cbcr_src_w, dst_w));
|
2015-12-15 09:08:43 +08:00
|
|
|
VOP_SCL_SET(vop, win, scale_cbcr_y,
|
2016-06-06 15:58:46 +08:00
|
|
|
scl_cal_scale2(cbcr_src_h, dst_h));
|
2015-12-15 09:08:43 +08:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-06-26 17:14:46 +08:00
|
|
|
yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
|
|
|
|
yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
|
|
|
|
|
|
|
|
if (is_yuv) {
|
|
|
|
cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
|
|
|
|
cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
|
|
|
|
if (cbcr_hor_scl_mode == SCALE_DOWN)
|
|
|
|
lb_mode = scl_vop_cal_lb_mode(dst_w, true);
|
|
|
|
else
|
|
|
|
lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
|
|
|
|
} else {
|
|
|
|
if (yrgb_hor_scl_mode == SCALE_DOWN)
|
|
|
|
lb_mode = scl_vop_cal_lb_mode(dst_w, false);
|
|
|
|
else
|
|
|
|
lb_mode = scl_vop_cal_lb_mode(src_w, false);
|
|
|
|
}
|
|
|
|
|
2015-12-15 09:08:43 +08:00
|
|
|
VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
|
2015-06-26 17:14:46 +08:00
|
|
|
if (lb_mode == LB_RGB_3840X2) {
|
|
|
|
if (yrgb_ver_scl_mode != SCALE_NONE) {
|
2016-08-13 01:00:54 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
|
2015-06-26 17:14:46 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (cbcr_ver_scl_mode != SCALE_NONE) {
|
2016-08-13 01:00:54 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
|
2015-06-26 17:14:46 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
vsu_mode = SCALE_UP_BIL;
|
|
|
|
} else if (lb_mode == LB_RGB_2560X4) {
|
|
|
|
vsu_mode = SCALE_UP_BIL;
|
|
|
|
} else {
|
|
|
|
vsu_mode = SCALE_UP_BIC;
|
|
|
|
}
|
|
|
|
|
|
|
|
val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
|
|
|
|
true, 0, NULL);
|
|
|
|
VOP_SCL_SET(vop, win, scale_yrgb_x, val);
|
|
|
|
val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
|
|
|
|
false, vsu_mode, &vskiplines);
|
|
|
|
VOP_SCL_SET(vop, win, scale_yrgb_y, val);
|
|
|
|
|
2015-12-15 09:08:43 +08:00
|
|
|
VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
|
2015-06-26 17:14:46 +08:00
|
|
|
|
2015-12-15 09:08:43 +08:00
|
|
|
VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
|
2015-06-26 17:14:46 +08:00
|
|
|
if (is_yuv) {
|
|
|
|
val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
|
|
|
|
dst_w, true, 0, NULL);
|
|
|
|
VOP_SCL_SET(vop, win, scale_cbcr_x, val);
|
|
|
|
val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
|
|
|
|
dst_h, false, vsu_mode, &vskiplines);
|
|
|
|
VOP_SCL_SET(vop, win, scale_cbcr_y, val);
|
|
|
|
|
2015-12-15 09:08:43 +08:00
|
|
|
VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
|
|
|
|
VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
|
2015-06-26 17:14:46 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-02-04 13:10:31 +08:00
|
|
|
static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (WARN_ON(!vop->is_enabled))
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
|
|
|
|
2016-09-14 20:54:54 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
|
2015-12-15 08:36:55 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
|
2015-02-04 13:10:31 +08:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (WARN_ON(!vop->is_enabled))
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
|
|
|
|
2015-12-15 08:36:55 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
|
2015-02-04 13:10:31 +08:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
2016-07-24 14:57:40 +08:00
|
|
|
/*
|
|
|
|
* (1) each frame starts at the start of the Vsync pulse which is signaled by
|
|
|
|
* the "FRAME_SYNC" interrupt.
|
|
|
|
* (2) the active data region of each frame ends at dsp_vact_end
|
|
|
|
* (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
|
|
|
|
* to get "LINE_FLAG" interrupt at the end of the active on screen data.
|
|
|
|
*
|
|
|
|
* VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
|
|
|
|
* Interrupts
|
|
|
|
* LINE_FLAG -------------------------------+
|
|
|
|
* FRAME_SYNC ----+ |
|
|
|
|
* | |
|
|
|
|
* v v
|
|
|
|
* | Vsync | Vbp | Vactive | Vfp |
|
|
|
|
* ^ ^ ^ ^
|
|
|
|
* | | | |
|
|
|
|
* | | | |
|
|
|
|
* dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
|
|
|
|
* dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
|
|
|
|
* dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
|
|
|
|
* dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
|
|
|
|
*/
|
|
|
|
static bool vop_line_flag_irq_is_enabled(struct vop *vop)
|
|
|
|
{
|
|
|
|
uint32_t line_flag_irq;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
|
|
|
|
|
|
|
line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
|
|
|
|
return !!line_flag_irq;
|
|
|
|
}
|
|
|
|
|
2017-04-27 14:54:17 +08:00
|
|
|
static void vop_line_flag_irq_enable(struct vop *vop)
|
2016-07-24 14:57:40 +08:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (WARN_ON(!vop->is_enabled))
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
|
|
|
|
2016-09-14 20:54:54 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
|
2016-07-24 14:57:40 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vop_line_flag_irq_disable(struct vop *vop)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
if (WARN_ON(!vop->is_enabled))
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
|
|
|
|
|
|
|
VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
2016-08-16 07:12:29 +08:00
|
|
|
static int vop_enable(struct drm_crtc *crtc)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
|
|
|
struct vop *vop = to_vop(crtc);
|
drm/rockchip: vop: fix iommu page fault when resume
Iommu would get page fault with following path:
vop_disable:
1, disable all windows and set vop config done
2, vop enter to standy, all windows not works, but their registers
are not clean, when you read window's enable bit, may found the
window is enable.
vop_enable:
1, memcpy(vop->regsbak, vop->regs, len)
save current vop registers to vop->regsbak, then you can found
window is enable on regsbak.
2, VOP_WIN_SET(vop, win, gate, 1);
force enable window gate, but gate and enable are on same
hardware register, then window enable bit rewrite to vop hardware.
3, vop power on, and vop might try to scan destroyed buffer,
then iommu get page fault.
Move windows disable after vop regsbak restore, then vop regsbak mechanism
would keep tracing the modify, everything would be safe.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-by: Sandy huang <sandy.huang@rock-chips.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501494582-6934-1-git-send-email-mark.yao@rock-chips.com
2017-07-31 17:49:42 +08:00
|
|
|
int ret, i;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-04-01 13:48:53 +08:00
|
|
|
ret = pm_runtime_get_sync(vop->dev);
|
|
|
|
if (ret < 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
|
2017-04-06 20:31:20 +08:00
|
|
|
return ret;
|
2015-04-01 13:48:53 +08:00
|
|
|
}
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
ret = clk_enable(vop->hclk);
|
2016-08-16 07:12:29 +08:00
|
|
|
if (WARN_ON(ret < 0))
|
|
|
|
goto err_put_pm_runtime;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
ret = clk_enable(vop->dclk);
|
2016-08-16 07:12:29 +08:00
|
|
|
if (WARN_ON(ret < 0))
|
2014-08-22 18:36:26 +08:00
|
|
|
goto err_disable_hclk;
|
|
|
|
|
|
|
|
ret = clk_enable(vop->aclk);
|
2016-08-16 07:12:29 +08:00
|
|
|
if (WARN_ON(ret < 0))
|
2014-08-22 18:36:26 +08:00
|
|
|
goto err_disable_dclk;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Slave iommu shares power, irq and clock with vop. It was associated
|
|
|
|
* automatically with this master device via common driver code.
|
|
|
|
* Now that we have enabled the clock we attach it to the shared drm
|
|
|
|
* mapping.
|
|
|
|
*/
|
|
|
|
ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
|
|
|
|
if (ret) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev,
|
|
|
|
"failed to attach dma mapping, %d\n", ret);
|
2014-08-22 18:36:26 +08:00
|
|
|
goto err_disable_aclk;
|
|
|
|
}
|
|
|
|
|
2015-07-20 16:25:20 +08:00
|
|
|
memcpy(vop->regs, vop->regsbak, vop->len);
|
drm/rockchip: vop: fix iommu page fault when resume
Iommu would get page fault with following path:
vop_disable:
1, disable all windows and set vop config done
2, vop enter to standy, all windows not works, but their registers
are not clean, when you read window's enable bit, may found the
window is enable.
vop_enable:
1, memcpy(vop->regsbak, vop->regs, len)
save current vop registers to vop->regsbak, then you can found
window is enable on regsbak.
2, VOP_WIN_SET(vop, win, gate, 1);
force enable window gate, but gate and enable are on same
hardware register, then window enable bit rewrite to vop hardware.
3, vop power on, and vop might try to scan destroyed buffer,
then iommu get page fault.
Move windows disable after vop regsbak restore, then vop regsbak mechanism
would keep tracing the modify, everything would be safe.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-by: Sandy huang <sandy.huang@rock-chips.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501494582-6934-1-git-send-email-mark.yao@rock-chips.com
2017-07-31 17:49:42 +08:00
|
|
|
/*
|
|
|
|
* We need to make sure that all windows are disabled before we
|
|
|
|
* enable the crtc. Otherwise we might try to scan from a destroyed
|
|
|
|
* buffer later.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < vop->data->win_size; i++) {
|
|
|
|
struct vop_win *vop_win = &vop->win[i];
|
|
|
|
const struct vop_win_data *win = vop_win->data;
|
|
|
|
|
|
|
|
spin_lock(&vop->reg_lock);
|
|
|
|
VOP_WIN_SET(vop, win, enable, 0);
|
|
|
|
spin_unlock(&vop->reg_lock);
|
|
|
|
}
|
|
|
|
|
2016-08-27 11:39:38 +08:00
|
|
|
vop_cfg_done(vop);
|
|
|
|
|
2015-01-22 18:29:57 +08:00
|
|
|
/*
|
|
|
|
* At here, vop clock & iommu is enable, R/W vop regs would be safe.
|
|
|
|
*/
|
|
|
|
vop->is_enabled = true;
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
spin_lock(&vop->reg_lock);
|
|
|
|
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, common, standby, 1);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
spin_unlock(&vop->reg_lock);
|
|
|
|
|
|
|
|
enable_irq(vop->irq);
|
|
|
|
|
2015-11-23 15:21:08 +08:00
|
|
|
drm_crtc_vblank_on(crtc);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2016-08-16 07:12:29 +08:00
|
|
|
return 0;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
err_disable_aclk:
|
|
|
|
clk_disable(vop->aclk);
|
|
|
|
err_disable_dclk:
|
|
|
|
clk_disable(vop->dclk);
|
|
|
|
err_disable_hclk:
|
|
|
|
clk_disable(vop->hclk);
|
2016-08-16 07:12:29 +08:00
|
|
|
err_put_pm_runtime:
|
|
|
|
pm_runtime_put_sync(vop->dev);
|
|
|
|
return ret;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2017-06-30 17:36:45 +08:00
|
|
|
static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *old_state)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
|
|
|
struct vop *vop = to_vop(crtc);
|
|
|
|
|
2016-06-08 20:19:12 +08:00
|
|
|
WARN_ON(vop->event);
|
|
|
|
|
2016-08-19 03:01:46 +08:00
|
|
|
rockchip_drm_psr_deactivate(&vop->crtc);
|
|
|
|
|
2015-11-23 15:21:08 +08:00
|
|
|
drm_crtc_vblank_off(crtc);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
/*
|
2015-02-04 13:10:31 +08:00
|
|
|
* Vop standby will take effect at end of current frame,
|
|
|
|
* if dsp hold valid irq happen, it means standby complete.
|
|
|
|
*
|
|
|
|
* we must wait standby complete when we want to disable aclk,
|
|
|
|
* if not, memory bus maybe dead.
|
2014-08-22 18:36:26 +08:00
|
|
|
*/
|
2015-02-04 13:10:31 +08:00
|
|
|
reinit_completion(&vop->dsp_hold_completion);
|
|
|
|
vop_dsp_hold_valid_irq_enable(vop);
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
spin_lock(&vop->reg_lock);
|
|
|
|
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, common, standby, 1);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
spin_unlock(&vop->reg_lock);
|
2015-01-22 18:29:57 +08:00
|
|
|
|
2015-02-04 13:10:31 +08:00
|
|
|
wait_for_completion(&vop->dsp_hold_completion);
|
|
|
|
|
|
|
|
vop_dsp_hold_valid_irq_disable(vop);
|
|
|
|
|
|
|
|
disable_irq(vop->irq);
|
|
|
|
|
2015-01-22 18:29:57 +08:00
|
|
|
vop->is_enabled = false;
|
2015-02-04 13:10:31 +08:00
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
/*
|
2015-02-04 13:10:31 +08:00
|
|
|
* vop standby complete, so iommu detach is safe.
|
2014-08-22 18:36:26 +08:00
|
|
|
*/
|
|
|
|
rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
|
|
|
|
|
2015-02-04 13:10:31 +08:00
|
|
|
clk_disable(vop->dclk);
|
2014-08-22 18:36:26 +08:00
|
|
|
clk_disable(vop->aclk);
|
|
|
|
clk_disable(vop->hclk);
|
2015-04-01 13:48:53 +08:00
|
|
|
pm_runtime_put(vop->dev);
|
2016-06-08 20:19:12 +08:00
|
|
|
|
|
|
|
if (crtc->state->event && !crtc->state->active) {
|
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
|
|
drm_crtc_send_vblank_event(crtc, crtc->state->event);
|
|
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
|
|
|
|
|
|
crtc->state->event = NULL;
|
|
|
|
}
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static void vop_plane_destroy(struct drm_plane *plane)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
2015-11-30 18:22:42 +08:00
|
|
|
drm_plane_cleanup(plane);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static int vop_plane_atomic_check(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *state)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
2015-11-30 18:22:42 +08:00
|
|
|
struct drm_crtc *crtc = state->crtc;
|
2016-03-04 19:04:03 +08:00
|
|
|
struct drm_crtc_state *crtc_state;
|
2015-11-30 18:22:42 +08:00
|
|
|
struct drm_framebuffer *fb = state->fb;
|
2014-08-22 18:36:26 +08:00
|
|
|
struct vop_win *vop_win = to_vop_win(plane);
|
|
|
|
const struct vop_win_data *win = vop_win->data;
|
|
|
|
int ret;
|
2015-11-30 18:22:42 +08:00
|
|
|
struct drm_rect clip;
|
2015-06-26 17:14:46 +08:00
|
|
|
int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
|
|
|
|
DRM_PLANE_HELPER_NO_SCALING;
|
|
|
|
int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
|
|
|
|
DRM_PLANE_HELPER_NO_SCALING;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
if (!crtc || !fb)
|
2016-09-14 20:55:01 +08:00
|
|
|
return 0;
|
2016-03-04 19:04:03 +08:00
|
|
|
|
|
|
|
crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
|
|
|
|
if (WARN_ON(!crtc_state))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
clip.x1 = 0;
|
|
|
|
clip.y1 = 0;
|
2016-03-04 19:04:03 +08:00
|
|
|
clip.x2 = crtc_state->adjusted_mode.hdisplay;
|
|
|
|
clip.y2 = crtc_state->adjusted_mode.vdisplay;
|
2015-11-30 18:22:42 +08:00
|
|
|
|
2017-11-02 04:15:58 +08:00
|
|
|
ret = drm_plane_helper_check_state(state, crtc_state, &clip,
|
2016-07-27 00:07:02 +08:00
|
|
|
min_scale, max_scale,
|
|
|
|
true, true);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-07-27 00:07:02 +08:00
|
|
|
if (!state->visible)
|
2016-09-14 20:55:01 +08:00
|
|
|
return 0;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2016-12-15 05:32:55 +08:00
|
|
|
ret = vop_convert_format(fb->format->format);
|
2016-09-14 20:55:01 +08:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2015-07-20 16:16:49 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
/*
|
|
|
|
* Src.x1 can be odd when do clip, but yuv plane start point
|
|
|
|
* need align with 2 pixel.
|
|
|
|
*/
|
2017-07-31 17:49:55 +08:00
|
|
|
if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2)) {
|
|
|
|
DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
|
2014-08-22 18:36:26 +08:00
|
|
|
return -EINVAL;
|
2017-07-31 17:49:55 +08:00
|
|
|
}
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static void vop_plane_atomic_disable(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *old_state)
|
|
|
|
{
|
|
|
|
struct vop_win *vop_win = to_vop_win(plane);
|
|
|
|
const struct vop_win_data *win = vop_win->data;
|
|
|
|
struct vop *vop = to_vop(old_state->crtc);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
if (!old_state->crtc)
|
|
|
|
return;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
spin_lock(&vop->reg_lock);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
VOP_WIN_SET(vop, win, enable, 0);
|
2015-07-20 16:16:49 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
spin_unlock(&vop->reg_lock);
|
|
|
|
}
|
2015-07-20 16:16:49 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static void vop_plane_atomic_update(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *old_state)
|
|
|
|
{
|
|
|
|
struct drm_plane_state *state = plane->state;
|
|
|
|
struct drm_crtc *crtc = state->crtc;
|
|
|
|
struct vop_win *vop_win = to_vop_win(plane);
|
|
|
|
const struct vop_win_data *win = vop_win->data;
|
|
|
|
struct vop *vop = to_vop(state->crtc);
|
|
|
|
struct drm_framebuffer *fb = state->fb;
|
|
|
|
unsigned int actual_w, actual_h;
|
|
|
|
unsigned int dsp_stx, dsp_sty;
|
|
|
|
uint32_t act_info, dsp_info, dsp_st;
|
2016-07-27 00:07:01 +08:00
|
|
|
struct drm_rect *src = &state->src;
|
|
|
|
struct drm_rect *dest = &state->dst;
|
2015-11-30 18:22:42 +08:00
|
|
|
struct drm_gem_object *obj, *uv_obj;
|
|
|
|
struct rockchip_gem_object *rk_obj, *rk_uv_obj;
|
|
|
|
unsigned long offset;
|
|
|
|
dma_addr_t dma_addr;
|
|
|
|
uint32_t val;
|
|
|
|
bool rb_swap;
|
2016-09-14 20:55:01 +08:00
|
|
|
int format;
|
2015-07-20 16:16:49 +08:00
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
/*
|
2015-11-30 18:22:42 +08:00
|
|
|
* can't update plane when vop is disabled.
|
2014-08-22 18:36:26 +08:00
|
|
|
*/
|
2016-06-08 20:19:11 +08:00
|
|
|
if (WARN_ON(!crtc))
|
2015-11-30 18:22:42 +08:00
|
|
|
return;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
if (WARN_ON(!vop->is_enabled))
|
|
|
|
return;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2016-09-14 20:55:01 +08:00
|
|
|
if (!state->visible) {
|
2015-11-30 18:22:42 +08:00
|
|
|
vop_plane_atomic_disable(plane, old_state);
|
|
|
|
return;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
2015-11-30 18:22:42 +08:00
|
|
|
|
|
|
|
obj = rockchip_fb_get_gem_obj(fb, 0);
|
|
|
|
rk_obj = to_rockchip_obj(obj);
|
|
|
|
|
|
|
|
actual_w = drm_rect_width(src) >> 16;
|
|
|
|
actual_h = drm_rect_height(src) >> 16;
|
|
|
|
act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
|
|
|
|
|
|
|
|
dsp_info = (drm_rect_height(dest) - 1) << 16;
|
|
|
|
dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
|
|
|
|
|
|
|
|
dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
|
|
|
|
dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
|
|
|
|
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
|
|
|
|
|
2016-12-15 05:30:57 +08:00
|
|
|
offset = (src->x1 >> 16) * fb->format->cpp[0];
|
2015-11-30 18:22:42 +08:00
|
|
|
offset += (src->y1 >> 16) * fb->pitches[0];
|
2016-09-14 20:55:01 +08:00
|
|
|
dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
|
|
|
|
|
2016-12-15 05:32:55 +08:00
|
|
|
format = vop_convert_format(fb->format->format);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
spin_lock(&vop->reg_lock);
|
|
|
|
|
2016-09-14 20:55:01 +08:00
|
|
|
VOP_WIN_SET(vop, win, format, format);
|
2017-07-31 17:49:50 +08:00
|
|
|
VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
|
2016-09-14 20:55:01 +08:00
|
|
|
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
|
2016-12-15 05:32:55 +08:00
|
|
|
if (is_yuv_support(fb->format->format)) {
|
|
|
|
int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
|
|
|
|
int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
|
2016-12-15 05:30:57 +08:00
|
|
|
int bpp = fb->format->cpp[1];
|
2015-11-30 18:22:42 +08:00
|
|
|
|
|
|
|
uv_obj = rockchip_fb_get_gem_obj(fb, 1);
|
|
|
|
rk_uv_obj = to_rockchip_obj(uv_obj);
|
|
|
|
|
|
|
|
offset = (src->x1 >> 16) * bpp / hsub;
|
|
|
|
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
|
|
|
|
|
|
|
|
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
|
2017-07-31 17:49:50 +08:00
|
|
|
VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
|
2015-11-30 18:22:42 +08:00
|
|
|
VOP_WIN_SET(vop, win, uv_mst, dma_addr);
|
2015-07-20 16:16:49 +08:00
|
|
|
}
|
2015-06-26 17:14:46 +08:00
|
|
|
|
|
|
|
if (win->phy->scl)
|
|
|
|
scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
|
2015-11-30 18:22:42 +08:00
|
|
|
drm_rect_width(dest), drm_rect_height(dest),
|
2016-12-15 05:32:55 +08:00
|
|
|
fb->format->format);
|
2015-06-26 17:14:46 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
VOP_WIN_SET(vop, win, act_info, act_info);
|
|
|
|
VOP_WIN_SET(vop, win, dsp_info, dsp_info);
|
|
|
|
VOP_WIN_SET(vop, win, dsp_st, dsp_st);
|
2015-06-26 17:14:46 +08:00
|
|
|
|
2016-12-15 05:32:55 +08:00
|
|
|
rb_swap = has_rb_swapped(fb->format->format);
|
2015-05-11 18:55:39 +08:00
|
|
|
VOP_WIN_SET(vop, win, rb_swap, rb_swap);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2016-12-15 05:32:55 +08:00
|
|
|
if (is_alpha_support(fb->format->format)) {
|
2014-08-22 18:36:26 +08:00
|
|
|
VOP_WIN_SET(vop, win, dst_alpha_ctl,
|
|
|
|
DST_FACTOR_M0(ALPHA_SRC_INVERSE));
|
|
|
|
val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
|
|
|
|
SRC_ALPHA_M0(ALPHA_STRAIGHT) |
|
|
|
|
SRC_BLEND_M0(ALPHA_PER_PIX) |
|
|
|
|
SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
|
|
|
|
SRC_FACTOR_M0(ALPHA_ONE);
|
|
|
|
VOP_WIN_SET(vop, win, src_alpha_ctl, val);
|
|
|
|
} else {
|
|
|
|
VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
|
|
|
|
}
|
|
|
|
|
|
|
|
VOP_WIN_SET(vop, win, enable, 1);
|
|
|
|
spin_unlock(&vop->reg_lock);
|
|
|
|
}
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static const struct drm_plane_helper_funcs plane_helper_funcs = {
|
|
|
|
.atomic_check = vop_plane_atomic_check,
|
|
|
|
.atomic_update = vop_plane_atomic_update,
|
|
|
|
.atomic_disable = vop_plane_atomic_disable,
|
|
|
|
};
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
static const struct drm_plane_funcs vop_plane_funcs = {
|
2015-11-30 18:22:42 +08:00
|
|
|
.update_plane = drm_atomic_helper_update_plane,
|
|
|
|
.disable_plane = drm_atomic_helper_disable_plane,
|
2014-08-22 18:36:26 +08:00
|
|
|
.destroy = vop_plane_destroy,
|
2016-09-14 20:55:01 +08:00
|
|
|
.reset = drm_atomic_helper_plane_reset,
|
|
|
|
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
|
|
|
|
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
2014-08-22 18:36:26 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct vop *vop = to_vop(crtc);
|
|
|
|
unsigned long flags;
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
if (WARN_ON(!vop->is_enabled))
|
2014-08-22 18:36:26 +08:00
|
|
|
return -EPERM;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
|
|
|
|
2016-09-14 20:54:54 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
|
2015-12-15 08:36:55 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct vop *vop = to_vop(crtc);
|
|
|
|
unsigned long flags;
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
if (WARN_ON(!vop->is_enabled))
|
2014-08-22 18:36:26 +08:00
|
|
|
return;
|
2015-01-22 14:37:56 +08:00
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
2015-12-15 08:36:55 +08:00
|
|
|
|
|
|
|
VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
|
|
const struct drm_display_mode *mode,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
2016-01-06 12:03:53 +08:00
|
|
|
struct vop *vop = to_vop(crtc);
|
|
|
|
|
|
|
|
adjusted_mode->clock =
|
|
|
|
clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-06-30 17:36:44 +08:00
|
|
|
static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *old_state)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
|
|
|
struct vop *vop = to_vop(crtc);
|
2017-05-27 19:43:36 +08:00
|
|
|
const struct vop_data *vop_data = vop->data;
|
2016-04-20 10:41:42 +08:00
|
|
|
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
|
2015-11-30 18:22:42 +08:00
|
|
|
struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
|
2014-08-22 18:36:26 +08:00
|
|
|
u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
|
|
|
|
u16 hdisplay = adjusted_mode->hdisplay;
|
|
|
|
u16 htotal = adjusted_mode->htotal;
|
|
|
|
u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
|
|
|
|
u16 hact_end = hact_st + hdisplay;
|
|
|
|
u16 vdisplay = adjusted_mode->vdisplay;
|
|
|
|
u16 vtotal = adjusted_mode->vtotal;
|
|
|
|
u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
|
|
|
|
u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
|
|
|
|
u16 vact_end = vact_st + vdisplay;
|
2016-04-20 14:18:16 +08:00
|
|
|
uint32_t pin_pol, val;
|
2016-08-16 07:12:29 +08:00
|
|
|
int ret;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2016-06-08 20:19:12 +08:00
|
|
|
WARN_ON(vop->event);
|
|
|
|
|
2016-08-16 07:12:29 +08:00
|
|
|
ret = vop_enable(crtc);
|
|
|
|
if (ret) {
|
|
|
|
DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-02-05 15:54:56 +08:00
|
|
|
pin_pol = BIT(DCLK_INVERT);
|
2017-02-24 20:55:03 +08:00
|
|
|
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
|
|
|
|
BIT(HSYNC_POSITIVE) : 0;
|
|
|
|
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
|
|
|
|
BIT(VSYNC_POSITIVE) : 0;
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, output, pin_pol, pin_pol);
|
2016-04-20 14:18:16 +08:00
|
|
|
|
2016-04-20 10:41:42 +08:00
|
|
|
switch (s->output_type) {
|
|
|
|
case DRM_MODE_CONNECTOR_LVDS:
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, output, rgb_en, 1);
|
|
|
|
VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
|
2016-04-20 10:41:42 +08:00
|
|
|
break;
|
|
|
|
case DRM_MODE_CONNECTOR_eDP:
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
|
|
|
|
VOP_REG_SET(vop, output, edp_en, 1);
|
2016-04-20 10:41:42 +08:00
|
|
|
break;
|
|
|
|
case DRM_MODE_CONNECTOR_HDMIA:
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
|
|
|
|
VOP_REG_SET(vop, output, hdmi_en, 1);
|
2016-04-20 10:41:42 +08:00
|
|
|
break;
|
|
|
|
case DRM_MODE_CONNECTOR_DSI:
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
|
|
|
|
VOP_REG_SET(vop, output, mipi_en, 1);
|
2016-04-20 10:41:42 +08:00
|
|
|
break;
|
2017-02-05 15:54:56 +08:00
|
|
|
case DRM_MODE_CONNECTOR_DisplayPort:
|
|
|
|
pin_pol &= ~BIT(DCLK_INVERT);
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
|
|
|
|
VOP_REG_SET(vop, output, dp_en, 1);
|
2017-02-05 15:54:56 +08:00
|
|
|
break;
|
2016-04-20 10:41:42 +08:00
|
|
|
default:
|
2016-08-13 01:00:54 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
|
|
|
|
s->output_type);
|
2016-04-20 10:41:42 +08:00
|
|
|
}
|
2017-05-27 19:43:36 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* if vop is not support RGB10 output, need force RGB10 to RGB888.
|
|
|
|
*/
|
|
|
|
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
|
|
|
|
!(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
|
|
|
|
s->output_mode = ROCKCHIP_OUT_MODE_P888;
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, common, out_mode, s->output_mode);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
|
2014-08-22 18:36:26 +08:00
|
|
|
val = hact_st << 16;
|
|
|
|
val |= hact_end;
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, modeset, hact_st_end, val);
|
|
|
|
VOP_REG_SET(vop, modeset, hpost_st_end, val);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
|
2014-08-22 18:36:26 +08:00
|
|
|
val = vact_st << 16;
|
|
|
|
val |= vact_end;
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, modeset, vact_st_end, val);
|
|
|
|
VOP_REG_SET(vop, modeset, vpost_st_end, val);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
|
2017-04-27 14:54:17 +08:00
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
|
2015-12-16 18:08:17 +08:00
|
|
|
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, common, standby, 0);
|
2016-08-19 03:01:46 +08:00
|
|
|
|
|
|
|
rockchip_drm_psr_activate(&vop->crtc);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2016-09-14 20:54:56 +08:00
|
|
|
static bool vop_fs_irq_is_pending(struct vop *vop)
|
|
|
|
{
|
|
|
|
return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vop_wait_for_irq_handler(struct vop *vop)
|
|
|
|
{
|
|
|
|
bool pending;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Spin until frame start interrupt status bit goes low, which means
|
|
|
|
* that interrupt handler was invoked and cleared it. The timeout of
|
|
|
|
* 10 msecs is really too long, but it is just a safety measure if
|
|
|
|
* something goes really wrong. The wait will only happen in the very
|
|
|
|
* unlikely case of a vblank happening exactly at the same time and
|
|
|
|
* shouldn't exceed microseconds range.
|
|
|
|
*/
|
|
|
|
ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
|
|
|
|
!pending, 0, 10 * 1000);
|
|
|
|
if (ret)
|
|
|
|
DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
|
|
|
|
|
|
|
|
synchronize_irq(vop->irq);
|
|
|
|
}
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *old_crtc_state)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
2016-09-14 20:54:57 +08:00
|
|
|
struct drm_atomic_state *old_state = old_crtc_state->state;
|
2017-07-12 16:13:37 +08:00
|
|
|
struct drm_plane_state *old_plane_state, *new_plane_state;
|
2014-08-22 18:36:26 +08:00
|
|
|
struct vop *vop = to_vop(crtc);
|
2016-09-14 20:54:57 +08:00
|
|
|
struct drm_plane *plane;
|
|
|
|
int i;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
if (WARN_ON(!vop->is_enabled))
|
|
|
|
return;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
spin_lock(&vop->reg_lock);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
vop_cfg_done(vop);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
spin_unlock(&vop->reg_lock);
|
2016-09-14 20:54:56 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* There is a (rather unlikely) possiblity that a vblank interrupt
|
|
|
|
* fired before we set the cfg_done bit. To avoid spuriously
|
|
|
|
* signalling flip completion we need to wait for it to finish.
|
|
|
|
*/
|
|
|
|
vop_wait_for_irq_handler(vop);
|
2016-09-14 20:54:57 +08:00
|
|
|
|
2016-09-14 20:55:00 +08:00
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
|
|
if (crtc->state->event) {
|
|
|
|
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
|
|
|
|
WARN_ON(vop->event);
|
|
|
|
|
|
|
|
vop->event = crtc->state->event;
|
|
|
|
crtc->state->event = NULL;
|
|
|
|
}
|
|
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
|
|
|
2017-07-12 16:13:37 +08:00
|
|
|
for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
|
|
|
|
new_plane_state, i) {
|
2016-09-14 20:54:57 +08:00
|
|
|
if (!old_plane_state->fb)
|
|
|
|
continue;
|
|
|
|
|
2017-07-12 16:13:37 +08:00
|
|
|
if (old_plane_state->fb == new_plane_state->fb)
|
2016-09-14 20:54:57 +08:00
|
|
|
continue;
|
|
|
|
|
2017-08-11 20:33:06 +08:00
|
|
|
drm_framebuffer_get(old_plane_state->fb);
|
2016-09-14 20:54:57 +08:00
|
|
|
drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
|
|
|
|
set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
|
|
|
|
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
|
|
|
|
}
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *old_crtc_state)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
2016-08-19 03:01:46 +08:00
|
|
|
rockchip_drm_psr_flush(crtc);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
|
|
|
|
.mode_fixup = vop_crtc_mode_fixup,
|
|
|
|
.atomic_flush = vop_crtc_atomic_flush,
|
|
|
|
.atomic_begin = vop_crtc_atomic_begin,
|
2017-06-30 17:36:44 +08:00
|
|
|
.atomic_enable = vop_crtc_atomic_enable,
|
2017-06-30 17:36:45 +08:00
|
|
|
.atomic_disable = vop_crtc_atomic_disable,
|
2015-11-30 18:22:42 +08:00
|
|
|
};
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
static void vop_crtc_destroy(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
drm_crtc_cleanup(crtc);
|
|
|
|
}
|
|
|
|
|
2016-07-14 23:29:15 +08:00
|
|
|
static void vop_crtc_reset(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
if (crtc->state)
|
|
|
|
__drm_atomic_helper_crtc_destroy_state(crtc->state);
|
|
|
|
kfree(crtc->state);
|
|
|
|
|
|
|
|
crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
|
|
|
|
if (crtc->state)
|
|
|
|
crtc->state->crtc = crtc;
|
|
|
|
}
|
|
|
|
|
2016-04-20 10:41:42 +08:00
|
|
|
static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct rockchip_crtc_state *rockchip_state;
|
|
|
|
|
|
|
|
rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
|
|
|
|
if (!rockchip_state)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
__drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
|
|
|
|
return &rockchip_state->base;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vop_crtc_destroy_state(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *state)
|
|
|
|
{
|
|
|
|
struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
|
|
|
|
|
2016-05-09 22:34:09 +08:00
|
|
|
__drm_atomic_helper_crtc_destroy_state(&s->base);
|
2016-04-20 10:41:42 +08:00
|
|
|
kfree(s);
|
|
|
|
}
|
|
|
|
|
2017-03-07 04:02:26 +08:00
|
|
|
#ifdef CONFIG_DRM_ANALOGIX_DP
|
2017-03-03 21:39:36 +08:00
|
|
|
static struct drm_connector *vop_get_edp_connector(struct vop *vop)
|
|
|
|
{
|
|
|
|
struct drm_connector *connector;
|
2017-05-15 21:43:30 +08:00
|
|
|
struct drm_connector_list_iter conn_iter;
|
2017-03-03 21:39:36 +08:00
|
|
|
|
2017-05-15 21:43:30 +08:00
|
|
|
drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
|
|
|
|
drm_for_each_connector_iter(connector, &conn_iter) {
|
2017-03-03 21:39:36 +08:00
|
|
|
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
|
2017-05-15 21:43:30 +08:00
|
|
|
drm_connector_list_iter_end(&conn_iter);
|
2017-03-03 21:39:36 +08:00
|
|
|
return connector;
|
|
|
|
}
|
2017-05-15 21:43:30 +08:00
|
|
|
}
|
|
|
|
drm_connector_list_iter_end(&conn_iter);
|
2017-03-03 21:39:36 +08:00
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
|
|
|
|
const char *source_name, size_t *values_cnt)
|
|
|
|
{
|
|
|
|
struct vop *vop = to_vop(crtc);
|
|
|
|
struct drm_connector *connector;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
connector = vop_get_edp_connector(vop);
|
|
|
|
if (!connector)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
*values_cnt = 3;
|
|
|
|
|
|
|
|
if (source_name && strcmp(source_name, "auto") == 0)
|
|
|
|
ret = analogix_dp_start_crc(connector);
|
|
|
|
else if (!source_name)
|
|
|
|
ret = analogix_dp_stop_crc(connector);
|
|
|
|
else
|
|
|
|
ret = -EINVAL;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
2017-03-07 04:02:26 +08:00
|
|
|
#else
|
|
|
|
static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
|
|
|
|
const char *source_name, size_t *values_cnt)
|
|
|
|
{
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
#endif
|
2017-03-03 21:39:36 +08:00
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
static const struct drm_crtc_funcs vop_crtc_funcs = {
|
2015-11-30 18:22:42 +08:00
|
|
|
.set_config = drm_atomic_helper_set_config,
|
|
|
|
.page_flip = drm_atomic_helper_page_flip,
|
2014-08-22 18:36:26 +08:00
|
|
|
.destroy = vop_crtc_destroy,
|
2016-07-14 23:29:15 +08:00
|
|
|
.reset = vop_crtc_reset,
|
2016-04-20 10:41:42 +08:00
|
|
|
.atomic_duplicate_state = vop_crtc_duplicate_state,
|
|
|
|
.atomic_destroy_state = vop_crtc_destroy_state,
|
2017-02-07 17:16:29 +08:00
|
|
|
.enable_vblank = vop_crtc_enable_vblank,
|
|
|
|
.disable_vblank = vop_crtc_disable_vblank,
|
2017-03-03 21:39:36 +08:00
|
|
|
.set_crc_source = vop_crtc_set_crc_source,
|
2014-08-22 18:36:26 +08:00
|
|
|
};
|
|
|
|
|
2016-09-14 20:54:57 +08:00
|
|
|
static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
|
|
|
|
{
|
|
|
|
struct vop *vop = container_of(work, struct vop, fb_unref_work);
|
|
|
|
struct drm_framebuffer *fb = val;
|
|
|
|
|
|
|
|
drm_crtc_vblank_put(&vop->crtc);
|
2017-08-11 20:33:06 +08:00
|
|
|
drm_framebuffer_put(fb);
|
2016-09-14 20:54:57 +08:00
|
|
|
}
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
static void vop_handle_vblank(struct vop *vop)
|
2014-08-22 18:36:26 +08:00
|
|
|
{
|
2015-11-30 18:22:42 +08:00
|
|
|
struct drm_device *drm = vop->drm_dev;
|
|
|
|
struct drm_crtc *crtc = &vop->crtc;
|
|
|
|
unsigned long flags;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2016-06-08 20:19:12 +08:00
|
|
|
spin_lock_irqsave(&drm->event_lock, flags);
|
2015-11-30 18:22:42 +08:00
|
|
|
if (vop->event) {
|
|
|
|
drm_crtc_send_vblank_event(crtc, vop->event);
|
2016-08-11 04:24:39 +08:00
|
|
|
drm_crtc_vblank_put(crtc);
|
2016-09-14 20:54:59 +08:00
|
|
|
vop->event = NULL;
|
2016-08-11 04:24:39 +08:00
|
|
|
}
|
2016-06-08 20:19:12 +08:00
|
|
|
spin_unlock_irqrestore(&drm->event_lock, flags);
|
|
|
|
|
2016-09-14 20:54:57 +08:00
|
|
|
if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
|
|
|
|
drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t vop_isr(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct vop *vop = data;
|
2015-11-23 15:21:08 +08:00
|
|
|
struct drm_crtc *crtc = &vop->crtc;
|
2015-12-15 08:36:55 +08:00
|
|
|
uint32_t active_irqs;
|
2014-08-22 18:36:26 +08:00
|
|
|
unsigned long flags;
|
2015-02-04 13:10:31 +08:00
|
|
|
int ret = IRQ_NONE;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
/*
|
2015-12-15 08:36:55 +08:00
|
|
|
* interrupt register has interrupt status, enable and clear bits, we
|
2014-08-22 18:36:26 +08:00
|
|
|
* must hold irq_lock to avoid a race with enable/disable_vblank().
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&vop->irq_lock, flags);
|
2015-12-15 08:36:55 +08:00
|
|
|
|
|
|
|
active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
|
2014-08-22 18:36:26 +08:00
|
|
|
/* Clear all active interrupt sources */
|
|
|
|
if (active_irqs)
|
2015-12-15 08:36:55 +08:00
|
|
|
VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
spin_unlock_irqrestore(&vop->irq_lock, flags);
|
|
|
|
|
|
|
|
/* This is expected for vop iommu irqs, since the irq is shared */
|
|
|
|
if (!active_irqs)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2015-02-04 13:10:31 +08:00
|
|
|
if (active_irqs & DSP_HOLD_VALID_INTR) {
|
|
|
|
complete(&vop->dsp_hold_completion);
|
|
|
|
active_irqs &= ~DSP_HOLD_VALID_INTR;
|
|
|
|
ret = IRQ_HANDLED;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2016-07-24 14:57:40 +08:00
|
|
|
if (active_irqs & LINE_FLAG_INTR) {
|
|
|
|
complete(&vop->line_flag_completion);
|
|
|
|
active_irqs &= ~LINE_FLAG_INTR;
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2015-02-04 13:10:31 +08:00
|
|
|
if (active_irqs & FS_INTR) {
|
2015-11-23 15:21:08 +08:00
|
|
|
drm_crtc_handle_vblank(crtc);
|
2015-11-30 18:22:42 +08:00
|
|
|
vop_handle_vblank(vop);
|
2015-02-04 13:10:31 +08:00
|
|
|
active_irqs &= ~FS_INTR;
|
2015-11-30 18:22:42 +08:00
|
|
|
ret = IRQ_HANDLED;
|
2015-02-04 13:10:31 +08:00
|
|
|
}
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-02-04 13:10:31 +08:00
|
|
|
/* Unhandled irqs are spurious. */
|
|
|
|
if (active_irqs)
|
2016-08-13 01:00:54 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
|
|
|
|
active_irqs);
|
2015-02-04 13:10:31 +08:00
|
|
|
|
|
|
|
return ret;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int vop_create_crtc(struct vop *vop)
|
|
|
|
{
|
|
|
|
const struct vop_data *vop_data = vop->data;
|
|
|
|
struct device *dev = vop->dev;
|
|
|
|
struct drm_device *drm_dev = vop->drm_dev;
|
2016-03-08 06:00:52 +08:00
|
|
|
struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
|
2014-08-22 18:36:26 +08:00
|
|
|
struct drm_crtc *crtc = &vop->crtc;
|
|
|
|
struct device_node *port;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create drm_plane for primary and cursor planes first, since we need
|
|
|
|
* to pass them to drm_crtc_init_with_planes, which sets the
|
|
|
|
* "possible_crtcs" to the newly initialized crtc.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < vop_data->win_size; i++) {
|
|
|
|
struct vop_win *vop_win = &vop->win[i];
|
|
|
|
const struct vop_win_data *win_data = vop_win->data;
|
|
|
|
|
|
|
|
if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
|
|
|
|
win_data->type != DRM_PLANE_TYPE_CURSOR)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
|
|
|
|
0, &vop_plane_funcs,
|
|
|
|
win_data->phy->data_formats,
|
|
|
|
win_data->phy->nformats,
|
2017-07-24 11:46:38 +08:00
|
|
|
NULL, win_data->type, NULL);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (ret) {
|
2016-08-13 01:00:54 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
|
|
|
|
ret);
|
2014-08-22 18:36:26 +08:00
|
|
|
goto err_cleanup_planes;
|
|
|
|
}
|
|
|
|
|
|
|
|
plane = &vop_win->base;
|
2015-11-30 18:22:42 +08:00
|
|
|
drm_plane_helper_add(plane, &plane_helper_funcs);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
|
|
|
|
primary = plane;
|
|
|
|
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
|
|
|
|
cursor = plane;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
|
drm: Pass 'name' to drm_crtc_init_with_planes()
Done with coccinelle for the most part. However, it thinks '...' is
part of the semantic patch, so I put an 'int DOTDOTDOT' placeholder
in its place and got rid of it with sed afterwards.
I didn't convert drm_crtc_init() since passing the varargs through
would mean either cpp macros or va_list, and I figured we don't
care about these legacy functions enough to warrant the extra pain.
@@
identifier dev, crtc, primary, cursor, funcs;
@@
int drm_crtc_init_with_planes(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_plane *primary, struct drm_plane *cursor,
const struct drm_crtc_funcs *funcs
+ ,const char *name, int DOTDOTDOT
)
{ ... }
@@
identifier dev, crtc, primary, cursor, funcs;
@@
int drm_crtc_init_with_planes(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_plane *primary, struct drm_plane *cursor,
const struct drm_crtc_funcs *funcs
+ ,const char *name, int DOTDOTDOT
);
@@
expression E1, E2, E3, E4, E5;
@@
drm_crtc_init_with_planes(E1, E2, E3, E4, E5
+ ,NULL
)
v2: Split crtc and plane changes apart
Pass NULL for no-name instead of ""
Leave drm_crtc_init() alone
v3: Add ', or NULL...' to @name kernel doc (Jani)
Annotate the function with __printf() attribute (Jani)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449670771-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-12-09 22:19:31 +08:00
|
|
|
&vop_crtc_funcs, NULL);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (ret)
|
2016-03-08 06:00:52 +08:00
|
|
|
goto err_cleanup_planes;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create drm_planes for overlay windows with possible_crtcs restricted
|
|
|
|
* to the newly created crtc.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < vop_data->win_size; i++) {
|
|
|
|
struct vop_win *vop_win = &vop->win[i];
|
|
|
|
const struct vop_win_data *win_data = vop_win->data;
|
|
|
|
unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
|
|
|
|
|
|
|
|
if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
|
|
|
|
possible_crtcs,
|
|
|
|
&vop_plane_funcs,
|
|
|
|
win_data->phy->data_formats,
|
|
|
|
win_data->phy->nformats,
|
2017-07-24 11:46:38 +08:00
|
|
|
NULL, win_data->type, NULL);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (ret) {
|
2016-08-13 01:00:54 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
|
|
|
|
ret);
|
2014-08-22 18:36:26 +08:00
|
|
|
goto err_cleanup_crtc;
|
|
|
|
}
|
2015-11-30 18:22:42 +08:00
|
|
|
drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
port = of_get_child_by_name(dev->of_node, "port");
|
|
|
|
if (!port) {
|
2017-07-19 05:43:04 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
|
|
|
|
dev->of_node);
|
2016-03-08 06:00:52 +08:00
|
|
|
ret = -ENOENT;
|
2014-08-22 18:36:26 +08:00
|
|
|
goto err_cleanup_crtc;
|
|
|
|
}
|
|
|
|
|
2016-09-14 20:54:57 +08:00
|
|
|
drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
|
|
|
|
vop_fb_unref_worker);
|
|
|
|
|
2015-02-04 13:10:31 +08:00
|
|
|
init_completion(&vop->dsp_hold_completion);
|
2016-07-24 14:57:40 +08:00
|
|
|
init_completion(&vop->line_flag_completion);
|
2014-08-22 18:36:26 +08:00
|
|
|
crtc->port = port;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_cleanup_crtc:
|
|
|
|
drm_crtc_cleanup(crtc);
|
|
|
|
err_cleanup_planes:
|
2016-03-08 06:00:52 +08:00
|
|
|
list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
|
|
|
|
head)
|
2014-08-22 18:36:26 +08:00
|
|
|
drm_plane_cleanup(plane);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vop_destroy_crtc(struct vop *vop)
|
|
|
|
{
|
|
|
|
struct drm_crtc *crtc = &vop->crtc;
|
2016-03-08 06:00:52 +08:00
|
|
|
struct drm_device *drm_dev = vop->drm_dev;
|
|
|
|
struct drm_plane *plane, *tmp;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
of_node_put(crtc->port);
|
2016-03-08 06:00:52 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to cleanup the planes now. Why?
|
|
|
|
*
|
|
|
|
* The planes are "&vop->win[i].base". That means the memory is
|
|
|
|
* all part of the big "struct vop" chunk of memory. That memory
|
|
|
|
* was devm allocated and associated with this component. We need to
|
|
|
|
* free it ourselves before vop_unbind() finishes.
|
|
|
|
*/
|
|
|
|
list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
|
|
|
|
head)
|
|
|
|
vop_plane_destroy(plane);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
|
|
|
|
* references the CRTC.
|
|
|
|
*/
|
2014-08-22 18:36:26 +08:00
|
|
|
drm_crtc_cleanup(crtc);
|
2016-09-14 20:54:57 +08:00
|
|
|
drm_flip_work_cleanup(&vop->fb_unref_work);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int vop_initial(struct vop *vop)
|
|
|
|
{
|
|
|
|
const struct vop_data *vop_data = vop->data;
|
|
|
|
struct reset_control *ahb_rst;
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
|
|
|
|
if (IS_ERR(vop->hclk)) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
|
2014-08-22 18:36:26 +08:00
|
|
|
return PTR_ERR(vop->hclk);
|
|
|
|
}
|
|
|
|
vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
|
|
|
|
if (IS_ERR(vop->aclk)) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
|
2014-08-22 18:36:26 +08:00
|
|
|
return PTR_ERR(vop->aclk);
|
|
|
|
}
|
|
|
|
vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
|
|
|
|
if (IS_ERR(vop->dclk)) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
|
2014-08-22 18:36:26 +08:00
|
|
|
return PTR_ERR(vop->dclk);
|
|
|
|
}
|
|
|
|
|
2017-04-06 20:31:20 +08:00
|
|
|
ret = pm_runtime_get_sync(vop->dev);
|
|
|
|
if (ret < 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
|
2017-04-06 20:31:20 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
ret = clk_prepare(vop->dclk);
|
|
|
|
if (ret < 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
|
2017-04-06 20:31:20 +08:00
|
|
|
goto err_put_pm_runtime;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2015-11-06 20:22:24 +08:00
|
|
|
/* Enable both the hclk and aclk to setup the vop */
|
|
|
|
ret = clk_prepare_enable(vop->hclk);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (ret < 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
|
2014-08-22 18:36:26 +08:00
|
|
|
goto err_unprepare_dclk;
|
|
|
|
}
|
|
|
|
|
2015-11-06 20:22:24 +08:00
|
|
|
ret = clk_prepare_enable(vop->aclk);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (ret < 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
|
2015-11-06 20:22:24 +08:00
|
|
|
goto err_disable_hclk;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
2015-11-06 20:22:24 +08:00
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
/*
|
|
|
|
* do hclk_reset, reset all vop registers.
|
|
|
|
*/
|
|
|
|
ahb_rst = devm_reset_control_get(vop->dev, "ahb");
|
|
|
|
if (IS_ERR(ahb_rst)) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
|
2014-08-22 18:36:26 +08:00
|
|
|
ret = PTR_ERR(ahb_rst);
|
2015-11-06 20:22:24 +08:00
|
|
|
goto err_disable_aclk;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
reset_control_assert(ahb_rst);
|
|
|
|
usleep_range(10, 20);
|
|
|
|
reset_control_deassert(ahb_rst);
|
|
|
|
|
|
|
|
memcpy(vop->regsbak, vop->regs, vop->len);
|
|
|
|
|
2017-07-28 14:06:25 +08:00
|
|
|
VOP_REG_SET(vop, misc, global_regdone_en, 1);
|
|
|
|
VOP_REG_SET(vop, common, dsp_blank, 0);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
for (i = 0; i < vop_data->win_size; i++) {
|
|
|
|
const struct vop_win_data *win = &vop_data->win[i];
|
2017-07-26 14:19:39 +08:00
|
|
|
int channel = i * 2 + 1;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2017-07-26 14:19:39 +08:00
|
|
|
VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
|
2014-08-22 18:36:26 +08:00
|
|
|
VOP_WIN_SET(vop, win, enable, 0);
|
2017-07-26 14:19:05 +08:00
|
|
|
VOP_WIN_SET(vop, win, gate, 1);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
vop_cfg_done(vop);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* do dclk_reset, let all config take affect.
|
|
|
|
*/
|
|
|
|
vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
|
|
|
|
if (IS_ERR(vop->dclk_rst)) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
|
2014-08-22 18:36:26 +08:00
|
|
|
ret = PTR_ERR(vop->dclk_rst);
|
2015-11-06 20:22:24 +08:00
|
|
|
goto err_disable_aclk;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
reset_control_assert(vop->dclk_rst);
|
|
|
|
usleep_range(10, 20);
|
|
|
|
reset_control_deassert(vop->dclk_rst);
|
|
|
|
|
|
|
|
clk_disable(vop->hclk);
|
2015-11-06 20:22:24 +08:00
|
|
|
clk_disable(vop->aclk);
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-01-22 14:37:56 +08:00
|
|
|
vop->is_enabled = false;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2017-04-06 20:31:20 +08:00
|
|
|
pm_runtime_put_sync(vop->dev);
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
return 0;
|
|
|
|
|
2015-11-06 20:22:24 +08:00
|
|
|
err_disable_aclk:
|
|
|
|
clk_disable_unprepare(vop->aclk);
|
2014-08-22 18:36:26 +08:00
|
|
|
err_disable_hclk:
|
2015-11-06 20:22:24 +08:00
|
|
|
clk_disable_unprepare(vop->hclk);
|
2014-08-22 18:36:26 +08:00
|
|
|
err_unprepare_dclk:
|
|
|
|
clk_unprepare(vop->dclk);
|
2017-04-06 20:31:20 +08:00
|
|
|
err_put_pm_runtime:
|
|
|
|
pm_runtime_put_sync(vop->dev);
|
2014-08-22 18:36:26 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the vop->win array elements.
|
|
|
|
*/
|
|
|
|
static void vop_win_init(struct vop *vop)
|
|
|
|
{
|
|
|
|
const struct vop_data *vop_data = vop->data;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < vop_data->win_size; i++) {
|
|
|
|
struct vop_win *vop_win = &vop->win[i];
|
|
|
|
const struct vop_win_data *win_data = &vop_data->win[i];
|
|
|
|
|
|
|
|
vop_win->data = win_data;
|
|
|
|
vop_win->vop = vop;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-24 14:57:40 +08:00
|
|
|
/**
|
2017-04-27 14:54:17 +08:00
|
|
|
* rockchip_drm_wait_vact_end
|
2016-07-24 14:57:40 +08:00
|
|
|
* @crtc: CRTC to enable line flag
|
|
|
|
* @mstimeout: millisecond for timeout
|
|
|
|
*
|
2017-04-27 14:54:17 +08:00
|
|
|
* Wait for vact_end line flag irq or timeout.
|
2016-07-24 14:57:40 +08:00
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* Zero on success, negative errno on failure.
|
|
|
|
*/
|
2017-04-27 14:54:17 +08:00
|
|
|
int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
|
2016-07-24 14:57:40 +08:00
|
|
|
{
|
|
|
|
struct vop *vop = to_vop(crtc);
|
|
|
|
unsigned long jiffies_left;
|
|
|
|
|
|
|
|
if (!crtc || !vop->is_enabled)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2017-04-27 14:54:17 +08:00
|
|
|
if (mstimeout <= 0)
|
2016-07-24 14:57:40 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (vop_line_flag_irq_is_enabled(vop))
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
reinit_completion(&vop->line_flag_completion);
|
2017-04-27 14:54:17 +08:00
|
|
|
vop_line_flag_irq_enable(vop);
|
2016-07-24 14:57:40 +08:00
|
|
|
|
|
|
|
jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
|
|
|
|
msecs_to_jiffies(mstimeout));
|
|
|
|
vop_line_flag_irq_disable(vop);
|
|
|
|
|
|
|
|
if (jiffies_left == 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
|
2016-07-24 14:57:40 +08:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2017-04-27 14:54:17 +08:00
|
|
|
EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
|
2016-07-24 14:57:40 +08:00
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
static int vop_bind(struct device *dev, struct device *master, void *data)
|
|
|
|
{
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
const struct vop_data *vop_data;
|
|
|
|
struct drm_device *drm_dev = data;
|
|
|
|
struct vop *vop;
|
|
|
|
struct resource *res;
|
|
|
|
size_t alloc_size;
|
2015-04-20 07:00:53 +08:00
|
|
|
int ret, irq;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
2015-12-15 08:58:26 +08:00
|
|
|
vop_data = of_device_get_match_data(dev);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (!vop_data)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
/* Allocate vop struct and its vop_win array */
|
|
|
|
alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
|
|
|
|
vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
|
|
|
|
if (!vop)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
vop->dev = dev;
|
|
|
|
vop->data = vop_data;
|
|
|
|
vop->drm_dev = drm_dev;
|
|
|
|
dev_set_drvdata(dev, vop);
|
|
|
|
|
|
|
|
vop_win_init(vop);
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
vop->len = resource_size(res);
|
|
|
|
vop->regs = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(vop->regs))
|
|
|
|
return PTR_ERR(vop->regs);
|
|
|
|
|
|
|
|
vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
|
|
|
|
if (!vop->regsbak)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-04-20 07:00:53 +08:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
|
2015-04-20 07:00:53 +08:00
|
|
|
return irq;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
2015-04-20 07:00:53 +08:00
|
|
|
vop->irq = (unsigned int)irq;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
spin_lock_init(&vop->reg_lock);
|
|
|
|
spin_lock_init(&vop->irq_lock);
|
|
|
|
|
|
|
|
mutex_init(&vop->vsync_mutex);
|
|
|
|
|
2015-11-30 18:22:42 +08:00
|
|
|
ret = devm_request_irq(dev, vop->irq, vop_isr,
|
|
|
|
IRQF_SHARED, dev_name(dev), vop);
|
2014-08-22 18:36:26 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* IRQ is initially disabled; it gets enabled in power_on */
|
|
|
|
disable_irq(vop->irq);
|
|
|
|
|
|
|
|
ret = vop_create_crtc(vop);
|
|
|
|
if (ret)
|
2016-09-17 02:22:03 +08:00
|
|
|
goto err_enable_irq;
|
2014-08-22 18:36:26 +08:00
|
|
|
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
2016-07-24 14:57:44 +08:00
|
|
|
|
2017-04-06 20:31:20 +08:00
|
|
|
ret = vop_initial(vop);
|
|
|
|
if (ret < 0) {
|
2017-09-15 16:36:03 +08:00
|
|
|
DRM_DEV_ERROR(&pdev->dev,
|
|
|
|
"cannot initial vop dev - err %d\n", ret);
|
2017-04-06 20:31:20 +08:00
|
|
|
goto err_disable_pm_runtime;
|
|
|
|
}
|
|
|
|
|
2014-08-22 18:36:26 +08:00
|
|
|
return 0;
|
2016-09-17 02:22:03 +08:00
|
|
|
|
2017-04-06 20:31:20 +08:00
|
|
|
err_disable_pm_runtime:
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
vop_destroy_crtc(vop);
|
2016-09-17 02:22:03 +08:00
|
|
|
err_enable_irq:
|
|
|
|
enable_irq(vop->irq); /* To balance out the disable_irq above */
|
|
|
|
return ret;
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void vop_unbind(struct device *dev, struct device *master, void *data)
|
|
|
|
{
|
|
|
|
struct vop *vop = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
pm_runtime_disable(dev);
|
|
|
|
vop_destroy_crtc(vop);
|
2017-04-06 20:31:21 +08:00
|
|
|
|
|
|
|
clk_unprepare(vop->aclk);
|
|
|
|
clk_unprepare(vop->hclk);
|
|
|
|
clk_unprepare(vop->dclk);
|
2014-08-22 18:36:26 +08:00
|
|
|
}
|
|
|
|
|
2015-12-15 08:58:26 +08:00
|
|
|
const struct component_ops vop_component_ops = {
|
2014-08-22 18:36:26 +08:00
|
|
|
.bind = vop_bind,
|
|
|
|
.unbind = vop_unbind,
|
|
|
|
};
|
2015-12-31 10:40:11 +08:00
|
|
|
EXPORT_SYMBOL_GPL(vop_component_ops);
|