2018-03-15 05:15:19 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2014-11-12 18:39:03 +08:00
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/*
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* Copyright (C) 2014 Intel Corp.
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* Author: Jiang Liu <jiang.liu@linux.intel.com>
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*
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* This file is licensed under GPLv2.
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*
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2021-03-22 11:21:30 +08:00
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* This file contains common code to support Message Signaled Interrupts for
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2014-11-12 18:39:03 +08:00
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* PCI compatible and non PCI compatible devices.
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*/
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2014-11-15 22:24:05 +08:00
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#include <linux/types.h>
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#include <linux/device.h>
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2014-11-12 18:39:03 +08:00
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/msi.h>
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2016-11-22 17:21:16 +08:00
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#include <linux/slab.h>
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2021-12-07 06:27:31 +08:00
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#include <linux/sysfs.h>
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2021-08-13 11:56:27 +08:00
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#include <linux/pci.h>
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2014-11-15 22:24:04 +08:00
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2017-09-14 05:29:05 +08:00
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#include "internals.h"
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2016-09-14 22:18:47 +08:00
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/**
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2021-08-11 07:48:35 +08:00
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* alloc_msi_entry - Allocate an initialized msi_desc
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2016-09-14 22:18:47 +08:00
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* @dev: Pointer to the device for which this is allocated
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* @nvec: The number of vectors used in this entry
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* @affinity: Optional pointer to an affinity mask array size of @nvec
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*
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2021-08-11 07:48:35 +08:00
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* If @affinity is not %NULL then an affinity array[@nvec] is allocated
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2018-12-04 23:51:20 +08:00
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* and the affinity masks and flags from @affinity are copied.
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2021-08-11 07:48:35 +08:00
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*
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* Return: pointer to allocated &msi_desc on success or %NULL on failure
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2016-09-14 22:18:47 +08:00
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*/
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2018-12-04 23:51:20 +08:00
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struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
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const struct irq_affinity_desc *affinity)
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2015-07-09 16:00:47 +08:00
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{
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2016-09-14 22:18:47 +08:00
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struct msi_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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2015-07-09 16:00:47 +08:00
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if (!desc)
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return NULL;
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INIT_LIST_HEAD(&desc->list);
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desc->dev = dev;
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2016-09-14 22:18:47 +08:00
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desc->nvec_used = nvec;
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if (affinity) {
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desc->affinity = kmemdup(affinity,
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nvec * sizeof(*desc->affinity), GFP_KERNEL);
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if (!desc->affinity) {
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kfree(desc);
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return NULL;
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}
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}
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2015-07-09 16:00:47 +08:00
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return desc;
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}
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void free_msi_entry(struct msi_desc *entry)
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{
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2016-09-14 22:18:47 +08:00
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kfree(entry->affinity);
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2015-07-09 16:00:47 +08:00
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kfree(entry);
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}
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2014-11-12 19:11:25 +08:00
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void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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{
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*msg = entry->msg;
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}
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void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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struct msi_desc *entry = irq_get_msi_desc(irq);
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__get_cached_msi_msg(entry, msg);
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}
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EXPORT_SYMBOL_GPL(get_cached_msi_msg);
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2021-12-11 06:18:55 +08:00
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static void msi_device_data_release(struct device *dev, void *res)
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{
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2021-12-07 06:51:04 +08:00
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struct msi_device_data *md = res;
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WARN_ON_ONCE(!list_empty(&md->list));
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2021-12-11 06:18:55 +08:00
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dev->msi.data = NULL;
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}
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/**
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* msi_setup_device_data - Setup MSI device data
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* @dev: Device for which MSI device data should be set up
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*
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* Return: 0 on success, appropriate error code otherwise
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*
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* This can be called more than once for @dev. If the MSI device data is
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* already allocated the call succeeds. The allocated memory is
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* automatically released when the device is destroyed.
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*/
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int msi_setup_device_data(struct device *dev)
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{
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struct msi_device_data *md;
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if (dev->msi.data)
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return 0;
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md = devres_alloc(msi_device_data_release, sizeof(*md), GFP_KERNEL);
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if (!md)
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return -ENOMEM;
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2021-12-07 06:51:04 +08:00
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INIT_LIST_HEAD(&md->list);
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2021-12-07 06:51:05 +08:00
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mutex_init(&md->mutex);
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2021-12-11 06:18:55 +08:00
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dev->msi.data = md;
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devres_add(dev, md);
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return 0;
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}
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2021-12-07 06:51:05 +08:00
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/**
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* msi_lock_descs - Lock the MSI descriptor storage of a device
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* @dev: Device to operate on
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*/
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void msi_lock_descs(struct device *dev)
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{
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mutex_lock(&dev->msi.data->mutex);
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}
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EXPORT_SYMBOL_GPL(msi_lock_descs);
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/**
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* msi_unlock_descs - Unlock the MSI descriptor storage of a device
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* @dev: Device to operate on
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*/
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void msi_unlock_descs(struct device *dev)
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{
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mutex_unlock(&dev->msi.data->mutex);
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}
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EXPORT_SYMBOL_GPL(msi_unlock_descs);
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2021-12-11 06:19:23 +08:00
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/**
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* msi_get_virq - Return Linux interrupt number of a MSI interrupt
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* @dev: Device to operate on
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* @index: MSI interrupt index to look for (0-based)
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*
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* Return: The Linux interrupt number on success (> 0), 0 if not found
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*/
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unsigned int msi_get_virq(struct device *dev, unsigned int index)
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{
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struct msi_desc *desc;
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bool pcimsi;
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if (!dev->msi.data)
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return 0;
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pcimsi = dev_is_pci(dev) ? to_pci_dev(dev)->msi_enabled : false;
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for_each_msi_entry(desc, dev) {
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/* PCI-MSI has only one descriptor for multiple interrupts. */
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if (pcimsi) {
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if (desc->irq && index < desc->nvec_used)
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return desc->irq + index;
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break;
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}
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/*
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* PCI-MSIX and platform MSI use a descriptor per
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* interrupt.
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*/
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if (desc->msi_index == index)
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return desc->irq;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(msi_get_virq);
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2021-12-07 06:27:28 +08:00
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#ifdef CONFIG_SYSFS
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2021-08-13 11:56:27 +08:00
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static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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2021-12-11 06:18:49 +08:00
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/* MSI vs. MSIX is per device not per interrupt */
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bool is_msix = dev_is_pci(dev) ? to_pci_dev(dev)->msix_enabled : false;
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2021-08-13 11:56:27 +08:00
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return sysfs_emit(buf, "%s\n", is_msix ? "msix" : "msi");
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}
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/**
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* msi_populate_sysfs - Populate msi_irqs sysfs entries for devices
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* @dev: The device(PCI, platform etc) who will get sysfs entries
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*/
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2021-12-11 06:19:08 +08:00
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static const struct attribute_group **msi_populate_sysfs(struct device *dev)
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2021-08-13 11:56:27 +08:00
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{
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const struct attribute_group **msi_irq_groups;
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struct attribute **msi_attrs, *msi_attr;
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struct device_attribute *msi_dev_attr;
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struct attribute_group *msi_irq_group;
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struct msi_desc *entry;
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int ret = -ENOMEM;
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int num_msi = 0;
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int count = 0;
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int i;
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/* Determine how many msi entries we have */
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for_each_msi_entry(entry, dev)
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num_msi += entry->nvec_used;
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if (!num_msi)
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return NULL;
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/* Dynamically create the MSI attributes for the device */
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msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
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if (!msi_attrs)
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return ERR_PTR(-ENOMEM);
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for_each_msi_entry(entry, dev) {
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for (i = 0; i < entry->nvec_used; i++) {
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msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
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if (!msi_dev_attr)
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goto error_attrs;
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msi_attrs[count] = &msi_dev_attr->attr;
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sysfs_attr_init(&msi_dev_attr->attr);
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msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
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entry->irq + i);
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if (!msi_dev_attr->attr.name)
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goto error_attrs;
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msi_dev_attr->attr.mode = 0444;
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msi_dev_attr->show = msi_mode_show;
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++count;
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}
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}
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msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
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if (!msi_irq_group)
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goto error_attrs;
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msi_irq_group->name = "msi_irqs";
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msi_irq_group->attrs = msi_attrs;
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msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
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if (!msi_irq_groups)
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goto error_irq_group;
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msi_irq_groups[0] = msi_irq_group;
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ret = sysfs_create_groups(&dev->kobj, msi_irq_groups);
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if (ret)
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goto error_irq_groups;
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return msi_irq_groups;
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error_irq_groups:
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kfree(msi_irq_groups);
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error_irq_group:
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kfree(msi_irq_group);
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error_attrs:
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count = 0;
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msi_attr = msi_attrs[count];
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while (msi_attr) {
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msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
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kfree(msi_attr->name);
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kfree(msi_dev_attr);
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++count;
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msi_attr = msi_attrs[count];
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}
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kfree(msi_attrs);
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return ERR_PTR(ret);
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}
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2021-12-11 06:19:03 +08:00
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/**
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* msi_device_populate_sysfs - Populate msi_irqs sysfs entries for a device
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* @dev: The device (PCI, platform etc) which will get sysfs entries
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*/
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int msi_device_populate_sysfs(struct device *dev)
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{
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const struct attribute_group **group = msi_populate_sysfs(dev);
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if (IS_ERR(group))
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return PTR_ERR(group);
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dev->msi.data->attrs = group;
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return 0;
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}
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/**
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* msi_device_destroy_sysfs - Destroy msi_irqs sysfs entries for a device
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* @dev: The device (PCI, platform etc) for which to remove
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* sysfs entries
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*/
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void msi_device_destroy_sysfs(struct device *dev)
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{
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2021-12-11 06:19:08 +08:00
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const struct attribute_group **msi_irq_groups = dev->msi.data->attrs;
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struct device_attribute *dev_attr;
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struct attribute **msi_attrs;
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int count = 0;
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2021-12-11 06:19:03 +08:00
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dev->msi.data->attrs = NULL;
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2021-12-11 06:19:08 +08:00
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if (!msi_irq_groups)
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return;
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sysfs_remove_groups(&dev->kobj, msi_irq_groups);
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msi_attrs = msi_irq_groups[0]->attrs;
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while (msi_attrs[count]) {
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dev_attr = container_of(msi_attrs[count], struct device_attribute, attr);
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kfree(dev_attr->attr.name);
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kfree(dev_attr);
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++count;
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}
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kfree(msi_attrs);
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kfree(msi_irq_groups[0]);
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kfree(msi_irq_groups);
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2021-12-11 06:19:03 +08:00
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}
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2021-12-07 06:27:28 +08:00
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#endif
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2021-08-13 11:56:27 +08:00
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2014-11-12 18:39:03 +08:00
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#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
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2014-12-07 04:20:20 +08:00
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static inline void irq_chip_write_msi_msg(struct irq_data *data,
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struct msi_msg *msg)
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{
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data->chip->irq_write_msi_msg(data, msg);
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}
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genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
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static void msi_check_level(struct irq_domain *domain, struct msi_msg *msg)
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{
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struct msi_domain_info *info = domain->host_data;
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/*
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* If the MSI provider has messed with the second message and
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* not advertized that it is level-capable, signal the breakage.
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|
*/
|
|
|
|
WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
|
|
|
|
(info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
|
|
|
|
(msg[1].address_lo || msg[1].address_hi || msg[1].data));
|
|
|
|
}
|
|
|
|
|
2014-11-12 18:39:03 +08:00
|
|
|
/**
|
|
|
|
* msi_domain_set_affinity - Generic affinity setter function for MSI domains
|
|
|
|
* @irq_data: The irq data associated to the interrupt
|
|
|
|
* @mask: The affinity mask to set
|
|
|
|
* @force: Flag to enforce setting (disable online checks)
|
|
|
|
*
|
|
|
|
* Intended to be used by MSI interrupt controllers which are
|
|
|
|
* implemented with hierarchical domains.
|
2021-08-11 07:48:35 +08:00
|
|
|
*
|
|
|
|
* Return: IRQ_SET_MASK_* result code
|
2014-11-12 18:39:03 +08:00
|
|
|
*/
|
|
|
|
int msi_domain_set_affinity(struct irq_data *irq_data,
|
|
|
|
const struct cpumask *mask, bool force)
|
|
|
|
{
|
|
|
|
struct irq_data *parent = irq_data->parent_data;
|
genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
|
|
|
struct msi_msg msg[2] = { [1] = { }, };
|
2014-11-12 18:39:03 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = parent->chip->irq_set_affinity(parent, mask, force);
|
|
|
|
if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
|
genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
|
|
|
BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
|
|
|
|
msi_check_level(irq_data->domain, msg);
|
|
|
|
irq_chip_write_msi_msg(irq_data, msg);
|
2014-11-12 18:39:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-09-14 05:29:10 +08:00
|
|
|
static int msi_domain_activate(struct irq_domain *domain,
|
|
|
|
struct irq_data *irq_data, bool early)
|
2014-11-12 18:39:03 +08:00
|
|
|
{
|
genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
|
|
|
struct msi_msg msg[2] = { [1] = { }, };
|
2014-11-12 18:39:03 +08:00
|
|
|
|
genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
|
|
|
BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
|
|
|
|
msi_check_level(irq_data->domain, msg);
|
|
|
|
irq_chip_write_msi_msg(irq_data, msg);
|
2017-09-14 05:29:10 +08:00
|
|
|
return 0;
|
2014-11-12 18:39:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void msi_domain_deactivate(struct irq_domain *domain,
|
|
|
|
struct irq_data *irq_data)
|
|
|
|
{
|
genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
|
|
|
struct msi_msg msg[2];
|
2014-11-12 18:39:03 +08:00
|
|
|
|
genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers
So far, MSIs have been used to signal edge-triggered interrupts, as
a write is a good model for an edge (you can't "unwrite" something).
On the other hand, routing zillions of wires in an SoC because you
need level interrupts is a bit extreme.
People have come up with a variety of schemes to support this, which
involves sending two messages: one to signal the interrupt, and one
to clear it. Since the kernel cannot represent this, we've ended up
with side-band mechanisms that are pretty awful.
Instead, let's acknoledge the requirement, and ensure that, under the
right circumstances, the irq_compose_msg and irq_write_msg can take
as a parameter an array of two messages instead of a pointer to a
single one. We also add some checking that the compose method only
clobbers the second message if the MSI domain has been created with
the MSI_FLAG_LEVEL_CAPABLE flags.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
2018-05-08 20:14:30 +08:00
|
|
|
memset(msg, 0, sizeof(msg));
|
|
|
|
irq_chip_write_msi_msg(irq_data, msg);
|
2014-11-12 18:39:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
|
|
|
unsigned int nr_irqs, void *arg)
|
|
|
|
{
|
|
|
|
struct msi_domain_info *info = domain->host_data;
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
|
|
|
irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
if (irq_find_mapping(domain, hwirq) > 0)
|
|
|
|
return -EEXIST;
|
|
|
|
|
2016-01-13 04:18:06 +08:00
|
|
|
if (domain->parent) {
|
|
|
|
ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
2014-11-12 18:39:03 +08:00
|
|
|
|
|
|
|
for (i = 0; i < nr_irqs; i++) {
|
|
|
|
ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
|
|
|
|
if (ret < 0) {
|
|
|
|
if (ops->msi_free) {
|
|
|
|
for (i--; i > 0; i--)
|
|
|
|
ops->msi_free(domain, info, virq + i);
|
|
|
|
}
|
|
|
|
irq_domain_free_irqs_top(domain, virq, nr_irqs);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
|
|
|
|
unsigned int nr_irqs)
|
|
|
|
{
|
|
|
|
struct msi_domain_info *info = domain->host_data;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (info->ops->msi_free) {
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
|
|
info->ops->msi_free(domain, info, virq + i);
|
|
|
|
}
|
|
|
|
irq_domain_free_irqs_top(domain, virq, nr_irqs);
|
|
|
|
}
|
|
|
|
|
2015-04-27 20:54:23 +08:00
|
|
|
static const struct irq_domain_ops msi_domain_ops = {
|
2014-11-12 18:39:03 +08:00
|
|
|
.alloc = msi_domain_alloc,
|
|
|
|
.free = msi_domain_free,
|
|
|
|
.activate = msi_domain_activate,
|
|
|
|
.deactivate = msi_domain_deactivate,
|
|
|
|
};
|
|
|
|
|
2014-11-15 22:24:05 +08:00
|
|
|
static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
|
|
|
|
msi_alloc_info_t *arg)
|
|
|
|
{
|
|
|
|
return arg->hwirq;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
|
|
|
|
int nvec, msi_alloc_info_t *arg)
|
|
|
|
{
|
|
|
|
memset(arg, 0, sizeof(*arg));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
|
|
|
|
struct msi_desc *desc)
|
|
|
|
{
|
|
|
|
arg->desc = desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msi_domain_ops_init(struct irq_domain *domain,
|
|
|
|
struct msi_domain_info *info,
|
|
|
|
unsigned int virq, irq_hw_number_t hwirq,
|
|
|
|
msi_alloc_info_t *arg)
|
|
|
|
{
|
|
|
|
irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
|
|
|
|
info->chip_data);
|
|
|
|
if (info->handler && info->handler_name) {
|
|
|
|
__irq_set_handler(virq, info->handler, 0, info->handler_name);
|
|
|
|
if (info->handler_data)
|
|
|
|
irq_set_handler_data(virq, info->handler_data);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msi_domain_ops_check(struct irq_domain *domain,
|
|
|
|
struct msi_domain_info *info,
|
|
|
|
struct device *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct msi_domain_ops msi_domain_ops_default = {
|
2020-08-26 19:16:57 +08:00
|
|
|
.get_hwirq = msi_domain_ops_get_hwirq,
|
|
|
|
.msi_init = msi_domain_ops_init,
|
|
|
|
.msi_check = msi_domain_ops_check,
|
|
|
|
.msi_prepare = msi_domain_ops_prepare,
|
|
|
|
.set_desc = msi_domain_ops_set_desc,
|
|
|
|
.domain_alloc_irqs = __msi_domain_alloc_irqs,
|
|
|
|
.domain_free_irqs = __msi_domain_free_irqs,
|
2014-11-15 22:24:05 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static void msi_domain_update_dom_ops(struct msi_domain_info *info)
|
|
|
|
{
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
|
|
|
|
|
|
|
if (ops == NULL) {
|
|
|
|
info->ops = &msi_domain_ops_default;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-08-26 19:16:57 +08:00
|
|
|
if (ops->domain_alloc_irqs == NULL)
|
|
|
|
ops->domain_alloc_irqs = msi_domain_ops_default.domain_alloc_irqs;
|
|
|
|
if (ops->domain_free_irqs == NULL)
|
|
|
|
ops->domain_free_irqs = msi_domain_ops_default.domain_free_irqs;
|
|
|
|
|
|
|
|
if (!(info->flags & MSI_FLAG_USE_DEF_DOM_OPS))
|
|
|
|
return;
|
|
|
|
|
2014-11-15 22:24:05 +08:00
|
|
|
if (ops->get_hwirq == NULL)
|
|
|
|
ops->get_hwirq = msi_domain_ops_default.get_hwirq;
|
|
|
|
if (ops->msi_init == NULL)
|
|
|
|
ops->msi_init = msi_domain_ops_default.msi_init;
|
|
|
|
if (ops->msi_check == NULL)
|
|
|
|
ops->msi_check = msi_domain_ops_default.msi_check;
|
|
|
|
if (ops->msi_prepare == NULL)
|
|
|
|
ops->msi_prepare = msi_domain_ops_default.msi_prepare;
|
|
|
|
if (ops->set_desc == NULL)
|
|
|
|
ops->set_desc = msi_domain_ops_default.set_desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msi_domain_update_chip_ops(struct msi_domain_info *info)
|
|
|
|
{
|
|
|
|
struct irq_chip *chip = info->chip;
|
|
|
|
|
2015-10-14 02:14:45 +08:00
|
|
|
BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
|
2014-11-15 22:24:05 +08:00
|
|
|
if (!chip->irq_set_affinity)
|
|
|
|
chip->irq_set_affinity = msi_domain_set_affinity;
|
|
|
|
}
|
|
|
|
|
2014-11-12 18:39:03 +08:00
|
|
|
/**
|
2021-08-11 07:48:35 +08:00
|
|
|
* msi_create_irq_domain - Create an MSI interrupt domain
|
2015-10-13 19:51:44 +08:00
|
|
|
* @fwnode: Optional fwnode of the interrupt controller
|
2014-11-12 18:39:03 +08:00
|
|
|
* @info: MSI domain info
|
|
|
|
* @parent: Parent irq domain
|
2021-08-11 07:48:35 +08:00
|
|
|
*
|
|
|
|
* Return: pointer to the created &struct irq_domain or %NULL on failure
|
2014-11-12 18:39:03 +08:00
|
|
|
*/
|
2015-10-13 19:51:44 +08:00
|
|
|
struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
|
2014-11-12 18:39:03 +08:00
|
|
|
struct msi_domain_info *info,
|
|
|
|
struct irq_domain *parent)
|
|
|
|
{
|
2017-05-12 19:55:37 +08:00
|
|
|
struct irq_domain *domain;
|
|
|
|
|
2020-08-26 19:16:57 +08:00
|
|
|
msi_domain_update_dom_ops(info);
|
2014-11-15 22:24:05 +08:00
|
|
|
if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
|
|
|
|
msi_domain_update_chip_ops(info);
|
2014-11-12 18:39:03 +08:00
|
|
|
|
2017-05-12 19:55:37 +08:00
|
|
|
domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
|
|
|
|
fwnode, &msi_domain_ops, info);
|
2017-06-20 07:37:04 +08:00
|
|
|
|
|
|
|
if (domain && !domain->name && info->chip)
|
2017-05-12 19:55:37 +08:00
|
|
|
domain->name = info->chip->name;
|
|
|
|
|
|
|
|
return domain;
|
2014-11-12 18:39:03 +08:00
|
|
|
}
|
|
|
|
|
2015-11-23 16:26:05 +08:00
|
|
|
int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
|
|
|
|
int nvec, msi_alloc_info_t *arg)
|
|
|
|
{
|
|
|
|
struct msi_domain_info *info = domain->host_data;
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = ops->msi_check(domain, info, dev);
|
|
|
|
if (ret == 0)
|
|
|
|
ret = ops->msi_prepare(domain, dev, nvec, arg);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-11-23 16:26:06 +08:00
|
|
|
int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
|
|
|
|
int virq, int nvec, msi_alloc_info_t *arg)
|
|
|
|
{
|
|
|
|
struct msi_domain_info *info = domain->host_data;
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
|
|
|
struct msi_desc *desc;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
for_each_msi_entry(desc, dev) {
|
|
|
|
/* Don't even try the multi-MSI brain damage. */
|
|
|
|
if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ops->set_desc(arg, desc);
|
|
|
|
/* Assumes the domain mutex is held! */
|
2017-09-06 17:35:40 +08:00
|
|
|
ret = irq_domain_alloc_irqs_hierarchy(domain, desc->irq, 1,
|
|
|
|
arg);
|
2015-11-23 16:26:06 +08:00
|
|
|
if (ret)
|
|
|
|
break;
|
|
|
|
|
2017-09-06 17:35:40 +08:00
|
|
|
irq_set_msi_desc_off(desc->irq, 0, desc);
|
2015-11-23 16:26:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
/* Mop up the damage */
|
|
|
|
for_each_msi_entry(desc, dev) {
|
|
|
|
if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
irq_domain_free_irqs_common(domain, desc->irq, 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-12-29 17:47:22 +08:00
|
|
|
/*
|
|
|
|
* Carefully check whether the device can use reservation mode. If
|
|
|
|
* reservation mode is enabled then the early activation will assign a
|
|
|
|
* dummy vector to the device. If the PCI/MSI device does not support
|
|
|
|
* masking of the entry then this can result in spurious interrupts when
|
|
|
|
* the device driver is not absolutely careful. But even then a malfunction
|
|
|
|
* of the hardware could result in a spurious interrupt on the dummy vector
|
|
|
|
* and render the device unusable. If the entry can be masked then the core
|
|
|
|
* logic will prevent the spurious interrupt and reservation mode can be
|
|
|
|
* used. For now reservation mode is restricted to PCI/MSI.
|
|
|
|
*/
|
|
|
|
static bool msi_check_reservation_mode(struct irq_domain *domain,
|
|
|
|
struct msi_domain_info *info,
|
|
|
|
struct device *dev)
|
2017-12-29 17:42:10 +08:00
|
|
|
{
|
2017-12-29 17:47:22 +08:00
|
|
|
struct msi_desc *desc;
|
|
|
|
|
2020-08-26 19:16:51 +08:00
|
|
|
switch(domain->bus_token) {
|
|
|
|
case DOMAIN_BUS_PCI_MSI:
|
|
|
|
case DOMAIN_BUS_VMD_MSI:
|
|
|
|
break;
|
|
|
|
default:
|
2017-12-29 17:47:22 +08:00
|
|
|
return false;
|
2020-08-26 19:16:51 +08:00
|
|
|
}
|
2017-12-29 17:47:22 +08:00
|
|
|
|
2017-12-29 17:42:10 +08:00
|
|
|
if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
|
|
|
|
return false;
|
2017-12-29 17:47:22 +08:00
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Checking the first MSI descriptor is sufficient. MSIX supports
|
2021-11-04 07:27:29 +08:00
|
|
|
* masking and MSI does so when the can_mask attribute is set.
|
2017-12-29 17:47:22 +08:00
|
|
|
*/
|
|
|
|
desc = first_msi_entry(dev);
|
2021-12-07 06:27:39 +08:00
|
|
|
return desc->pci.msi_attrib.is_msix || desc->pci.msi_attrib.can_mask;
|
2017-12-29 17:42:10 +08:00
|
|
|
}
|
|
|
|
|
2021-12-07 06:27:59 +08:00
|
|
|
static int msi_handle_pci_fail(struct irq_domain *domain, struct msi_desc *desc,
|
|
|
|
int allocated)
|
|
|
|
{
|
|
|
|
switch(domain->bus_token) {
|
|
|
|
case DOMAIN_BUS_PCI_MSI:
|
|
|
|
case DOMAIN_BUS_VMD_MSI:
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI))
|
|
|
|
break;
|
|
|
|
fallthrough;
|
|
|
|
default:
|
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Let a failed PCI multi MSI allocation retry */
|
|
|
|
if (desc->nvec_used > 1)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
/* If there was a successful allocation let the caller know */
|
|
|
|
return allocated ? allocated : -ENOSPC;
|
|
|
|
}
|
|
|
|
|
2020-08-26 19:16:57 +08:00
|
|
|
int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
|
|
|
|
int nvec)
|
2014-11-15 22:24:04 +08:00
|
|
|
{
|
|
|
|
struct msi_domain_info *info = domain->host_data;
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
2017-12-29 17:42:10 +08:00
|
|
|
struct irq_data *irq_data;
|
2014-11-15 22:24:04 +08:00
|
|
|
struct msi_desc *desc;
|
2020-12-18 14:00:39 +08:00
|
|
|
msi_alloc_info_t arg = { };
|
2021-12-07 06:27:59 +08:00
|
|
|
int allocated = 0;
|
2016-07-04 16:39:22 +08:00
|
|
|
int i, ret, virq;
|
2017-12-29 17:42:10 +08:00
|
|
|
bool can_reserve;
|
2014-11-15 22:24:04 +08:00
|
|
|
|
2015-11-23 16:26:05 +08:00
|
|
|
ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
|
2014-11-15 22:24:04 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
for_each_msi_entry(desc, dev) {
|
|
|
|
ops->set_desc(&arg, desc);
|
|
|
|
|
2016-07-04 16:39:22 +08:00
|
|
|
virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
|
2016-07-04 16:39:24 +08:00
|
|
|
dev_to_node(dev), &arg, false,
|
2016-07-04 16:39:26 +08:00
|
|
|
desc->affinity);
|
2021-12-07 06:51:07 +08:00
|
|
|
if (virq < 0)
|
|
|
|
return msi_handle_pci_fail(domain, desc, allocated);
|
2014-11-15 22:24:04 +08:00
|
|
|
|
2017-09-14 05:29:05 +08:00
|
|
|
for (i = 0; i < desc->nvec_used; i++) {
|
2014-11-15 22:24:04 +08:00
|
|
|
irq_set_msi_desc_off(virq, i, desc);
|
2017-09-14 05:29:05 +08:00
|
|
|
irq_debugfs_copy_devname(virq + i, dev);
|
|
|
|
}
|
2021-12-07 06:27:59 +08:00
|
|
|
allocated++;
|
2014-11-15 22:24:04 +08:00
|
|
|
}
|
|
|
|
|
2017-12-29 17:47:22 +08:00
|
|
|
can_reserve = msi_check_reservation_mode(domain, info, dev);
|
2017-12-29 17:42:10 +08:00
|
|
|
|
2021-01-23 20:27:59 +08:00
|
|
|
/*
|
|
|
|
* This flag is set by the PCI layer as we need to activate
|
|
|
|
* the MSI entries before the PCI layer enables MSI in the
|
|
|
|
* card. Otherwise the card latches a random msi message.
|
|
|
|
*/
|
|
|
|
if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY))
|
|
|
|
goto skip_activate;
|
|
|
|
|
|
|
|
for_each_msi_vector(desc, i, dev) {
|
|
|
|
if (desc->irq == i) {
|
|
|
|
virq = desc->irq;
|
2014-11-15 22:24:04 +08:00
|
|
|
dev_dbg(dev, "irq [%d-%d] for MSI\n",
|
|
|
|
virq, virq + desc->nvec_used - 1);
|
2021-01-23 20:27:59 +08:00
|
|
|
}
|
2016-07-14 00:18:33 +08:00
|
|
|
|
2021-01-23 20:27:59 +08:00
|
|
|
irq_data = irq_domain_get_irq_data(domain, i);
|
2020-01-31 22:26:52 +08:00
|
|
|
if (!can_reserve) {
|
2017-12-29 17:47:22 +08:00
|
|
|
irqd_clr_can_reserve(irq_data);
|
2020-01-31 22:26:52 +08:00
|
|
|
if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK)
|
|
|
|
irqd_set_msi_nomask_quirk(irq_data);
|
|
|
|
}
|
2017-12-29 17:47:22 +08:00
|
|
|
ret = irq_domain_activate_irq(irq_data, can_reserve);
|
2017-12-29 17:42:10 +08:00
|
|
|
if (ret)
|
2021-12-07 06:51:07 +08:00
|
|
|
return ret;
|
2017-12-29 17:42:10 +08:00
|
|
|
}
|
|
|
|
|
2021-01-23 20:27:59 +08:00
|
|
|
skip_activate:
|
2017-12-29 17:42:10 +08:00
|
|
|
/*
|
|
|
|
* If these interrupts use reservation mode, clear the activated bit
|
|
|
|
* so request_irq() will assign the final vector.
|
|
|
|
*/
|
|
|
|
if (can_reserve) {
|
2021-01-23 20:27:59 +08:00
|
|
|
for_each_msi_vector(desc, i, dev) {
|
|
|
|
irq_data = irq_domain_get_irq_data(domain, i);
|
2017-12-29 17:42:10 +08:00
|
|
|
irqd_clr_activated(irq_data);
|
2016-07-14 00:18:33 +08:00
|
|
|
}
|
2014-11-15 22:24:04 +08:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-12-07 06:51:07 +08:00
|
|
|
* msi_domain_alloc_irqs_descs_locked - Allocate interrupts from a MSI interrupt domain
|
2020-08-26 19:16:57 +08:00
|
|
|
* @domain: The domain to allocate from
|
2014-11-15 22:24:04 +08:00
|
|
|
* @dev: Pointer to device struct of the device for which the interrupts
|
2020-08-26 19:16:57 +08:00
|
|
|
* are allocated
|
|
|
|
* @nvec: The number of interrupts to allocate
|
|
|
|
*
|
2021-12-07 06:51:07 +08:00
|
|
|
* Must be invoked from within a msi_lock_descs() / msi_unlock_descs()
|
|
|
|
* pair. Use this for MSI irqdomains which implement their own vector
|
|
|
|
* allocation/free.
|
|
|
|
*
|
2021-08-11 07:48:35 +08:00
|
|
|
* Return: %0 on success or an error code.
|
2014-11-15 22:24:04 +08:00
|
|
|
*/
|
2021-12-07 06:51:07 +08:00
|
|
|
int msi_domain_alloc_irqs_descs_locked(struct irq_domain *domain, struct device *dev,
|
|
|
|
int nvec)
|
2020-08-26 19:16:57 +08:00
|
|
|
{
|
|
|
|
struct msi_domain_info *info = domain->host_data;
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
2021-12-11 06:19:03 +08:00
|
|
|
int ret;
|
|
|
|
|
2021-12-07 06:51:07 +08:00
|
|
|
lockdep_assert_held(&dev->msi.data->mutex);
|
|
|
|
|
2021-12-11 06:19:03 +08:00
|
|
|
ret = ops->domain_alloc_irqs(domain, dev, nvec);
|
|
|
|
if (ret)
|
2021-12-07 06:51:07 +08:00
|
|
|
goto cleanup;
|
2021-12-11 06:19:03 +08:00
|
|
|
|
|
|
|
if (!(info->flags & MSI_FLAG_DEV_SYSFS))
|
|
|
|
return 0;
|
2020-08-26 19:16:57 +08:00
|
|
|
|
2021-12-11 06:19:03 +08:00
|
|
|
ret = msi_device_populate_sysfs(dev);
|
|
|
|
if (ret)
|
2021-12-07 06:51:07 +08:00
|
|
|
goto cleanup;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cleanup:
|
|
|
|
msi_domain_free_irqs_descs_locked(domain, dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
|
|
|
|
* @domain: The domain to allocate from
|
|
|
|
* @dev: Pointer to device struct of the device for which the interrupts
|
|
|
|
* are allocated
|
|
|
|
* @nvec: The number of interrupts to allocate
|
|
|
|
*
|
|
|
|
* Return: %0 on success or an error code.
|
|
|
|
*/
|
|
|
|
int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, int nvec)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
msi_lock_descs(dev);
|
|
|
|
ret = msi_domain_alloc_irqs_descs_locked(domain, dev, nvec);
|
|
|
|
msi_unlock_descs(dev);
|
2021-12-11 06:19:03 +08:00
|
|
|
return ret;
|
2020-08-26 19:16:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void __msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
|
2014-11-15 22:24:04 +08:00
|
|
|
{
|
2021-05-18 11:31:17 +08:00
|
|
|
struct irq_data *irq_data;
|
2014-11-15 22:24:04 +08:00
|
|
|
struct msi_desc *desc;
|
2021-05-18 11:31:17 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_msi_vector(desc, i, dev) {
|
|
|
|
irq_data = irq_domain_get_irq_data(domain, i);
|
|
|
|
if (irqd_is_activated(irq_data))
|
|
|
|
irq_domain_deactivate_irq(irq_data);
|
|
|
|
}
|
2014-11-15 22:24:04 +08:00
|
|
|
|
|
|
|
for_each_msi_entry(desc, dev) {
|
2015-01-27 03:10:19 +08:00
|
|
|
/*
|
|
|
|
* We might have failed to allocate an MSI early
|
|
|
|
* enough that there is no IRQ associated to this
|
|
|
|
* entry. If that's the case, don't do anything.
|
|
|
|
*/
|
|
|
|
if (desc->irq) {
|
|
|
|
irq_domain_free_irqs(desc->irq, desc->nvec_used);
|
|
|
|
desc->irq = 0;
|
|
|
|
}
|
2014-11-15 22:24:04 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-08-26 19:16:57 +08:00
|
|
|
/**
|
2021-12-07 06:51:07 +08:00
|
|
|
* msi_domain_free_irqs_descs_locked - Free interrupts from a MSI interrupt @domain associated to @dev
|
2020-08-26 19:16:57 +08:00
|
|
|
* @domain: The domain to managing the interrupts
|
|
|
|
* @dev: Pointer to device struct of the device for which the interrupts
|
|
|
|
* are free
|
2021-12-07 06:51:07 +08:00
|
|
|
*
|
|
|
|
* Must be invoked from within a msi_lock_descs() / msi_unlock_descs()
|
|
|
|
* pair. Use this for MSI irqdomains which implement their own vector
|
|
|
|
* allocation.
|
2020-08-26 19:16:57 +08:00
|
|
|
*/
|
2021-12-07 06:51:07 +08:00
|
|
|
void msi_domain_free_irqs_descs_locked(struct irq_domain *domain, struct device *dev)
|
2020-08-26 19:16:57 +08:00
|
|
|
{
|
|
|
|
struct msi_domain_info *info = domain->host_data;
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
|
|
|
|
2021-12-07 06:51:07 +08:00
|
|
|
lockdep_assert_held(&dev->msi.data->mutex);
|
|
|
|
|
2021-12-11 06:19:03 +08:00
|
|
|
if (info->flags & MSI_FLAG_DEV_SYSFS)
|
|
|
|
msi_device_destroy_sysfs(dev);
|
|
|
|
ops->domain_free_irqs(domain, dev);
|
2020-08-26 19:16:57 +08:00
|
|
|
}
|
|
|
|
|
2021-12-07 06:51:07 +08:00
|
|
|
/**
|
|
|
|
* msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated to @dev
|
|
|
|
* @domain: The domain to managing the interrupts
|
|
|
|
* @dev: Pointer to device struct of the device for which the interrupts
|
|
|
|
* are free
|
|
|
|
*/
|
|
|
|
void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
|
|
|
|
{
|
|
|
|
msi_lock_descs(dev);
|
|
|
|
msi_domain_free_irqs_descs_locked(domain, dev);
|
|
|
|
msi_unlock_descs(dev);
|
|
|
|
}
|
|
|
|
|
2014-11-12 18:39:03 +08:00
|
|
|
/**
|
|
|
|
* msi_get_domain_info - Get the MSI interrupt domain info for @domain
|
|
|
|
* @domain: The interrupt domain to retrieve data from
|
|
|
|
*
|
2021-08-11 07:48:35 +08:00
|
|
|
* Return: the pointer to the msi_domain_info stored in @domain->host_data.
|
2014-11-12 18:39:03 +08:00
|
|
|
*/
|
|
|
|
struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
|
|
|
|
{
|
|
|
|
return (struct msi_domain_info *)domain->host_data;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
|