2018-12-14 00:56:18 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Linux performance counter support for ARC CPUs.
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// This code is inspired by the perf support of various other architectures.
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//
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// Copyright (C) 2013-2018 Synopsys, Inc. (www.synopsys.com)
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2013-11-07 21:55:11 +08:00
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#include <linux/errno.h>
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2015-08-24 18:48:06 +08:00
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#include <linux/interrupt.h>
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2013-11-07 21:55:11 +08:00
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <asm/arcregs.h>
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2013-11-12 18:00:03 +08:00
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#include <asm/stacktrace.h>
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2013-11-07 21:55:11 +08:00
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2018-12-14 00:56:18 +08:00
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/* HW holds 8 symbols + one for null terminator */
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#define ARCPMU_EVENT_NAME_LEN 9
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2018-12-14 00:56:19 +08:00
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enum arc_pmu_attr_groups {
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ARCPMU_ATTR_GR_EVENTS,
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ARCPMU_ATTR_GR_FORMATS,
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ARCPMU_NR_ATTR_GR
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};
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struct arc_pmu_raw_event_entry {
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char name[ARCPMU_EVENT_NAME_LEN];
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};
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2013-11-07 21:55:11 +08:00
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struct arc_pmu {
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struct pmu pmu;
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2015-08-24 19:03:30 +08:00
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unsigned int irq;
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2013-11-07 21:55:11 +08:00
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int n_counters;
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2018-12-14 00:56:19 +08:00
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int n_events;
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2015-08-24 18:42:27 +08:00
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u64 max_period;
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2013-11-07 21:55:11 +08:00
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int ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
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2018-12-14 00:56:19 +08:00
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struct arc_pmu_raw_event_entry *raw_entry;
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struct attribute **attrs;
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struct perf_pmu_events_attr *attr;
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const struct attribute_group *attr_groups[ARCPMU_NR_ATTR_GR + 1];
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2015-08-24 19:03:30 +08:00
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};
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struct arc_pmu_cpu {
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/*
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* A 1 bit for an index indicates that the counter is being used for
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* an event. A 0 means that the counter can be used.
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*/
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unsigned long used_mask[BITS_TO_LONGS(ARC_PERF_MAX_COUNTERS)];
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/*
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* The events that are active on the PMU for the given index.
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*/
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2015-08-24 18:48:06 +08:00
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struct perf_event *act_counter[ARC_PERF_MAX_COUNTERS];
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2013-11-07 21:55:11 +08:00
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};
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2013-11-12 18:00:03 +08:00
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struct arc_callchain_trace {
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int depth;
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void *perf_stuff;
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};
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static int callchain_trace(unsigned int addr, void *data)
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{
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struct arc_callchain_trace *ctrl = data;
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2016-04-28 23:30:53 +08:00
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struct perf_callchain_entry_ctx *entry = ctrl->perf_stuff;
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2018-12-14 00:56:18 +08:00
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2013-11-12 18:00:03 +08:00
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perf_callchain_store(entry, addr);
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if (ctrl->depth++ < 3)
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return 0;
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return -1;
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}
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2018-12-14 00:56:18 +08:00
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void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
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struct pt_regs *regs)
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2013-11-12 18:00:03 +08:00
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{
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struct arc_callchain_trace ctrl = {
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.depth = 0,
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.perf_stuff = entry,
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};
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arc_unwind_core(NULL, regs, callchain_trace, &ctrl);
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}
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2018-12-14 00:56:18 +08:00
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void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
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struct pt_regs *regs)
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2013-07-12 21:55:54 +08:00
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{
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/*
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* User stack can't be unwound trivially with kernel dwarf unwinder
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* So for now just record the user PC
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*/
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perf_callchain_store(entry, instruction_pointer(regs));
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}
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2014-11-17 19:43:03 +08:00
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static struct arc_pmu *arc_pmu;
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2015-08-24 19:03:30 +08:00
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static DEFINE_PER_CPU(struct arc_pmu_cpu, arc_pmu_cpu);
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2014-11-17 19:43:03 +08:00
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2013-11-07 21:55:11 +08:00
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/* read counter #idx; note that counter# != event# on ARC! */
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2018-12-14 00:56:18 +08:00
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static u64 arc_pmu_read_counter(int idx)
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2013-11-07 21:55:11 +08:00
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{
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2018-12-14 00:56:18 +08:00
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u32 tmp;
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u64 result;
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2013-11-07 21:55:11 +08:00
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/*
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* ARC supports making 'snapshots' of the counters, so we don't
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* need to care about counters wrapping to 0 underneath our feet
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*/
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
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2018-12-14 00:56:18 +08:00
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result = (u64) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
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2013-11-07 21:55:11 +08:00
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result |= read_aux_reg(ARC_REG_PCT_SNAPL);
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return result;
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}
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static void arc_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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2018-12-14 00:56:18 +08:00
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u64 prev_raw_count = local64_read(&hwc->prev_count);
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u64 new_raw_count = arc_pmu_read_counter(idx);
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s64 delta = new_raw_count - prev_raw_count;
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2013-11-07 21:55:11 +08:00
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2015-08-24 18:42:27 +08:00
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/*
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2016-05-21 19:45:35 +08:00
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* We aren't afraid of hwc->prev_count changing beneath our feet
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2015-08-24 18:42:27 +08:00
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* because there's no way for us to re-enter this function anytime.
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*/
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local64_set(&hwc->prev_count, new_raw_count);
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2013-11-07 21:55:11 +08:00
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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}
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static void arc_pmu_read(struct perf_event *event)
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{
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arc_perf_event_update(event, &event->hw, event->hw.idx);
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}
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static int arc_pmu_cache_event(u64 config)
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{
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unsigned int cache_type, cache_op, cache_result;
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int ret;
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cache_type = (config >> 0) & 0xff;
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cache_op = (config >> 8) & 0xff;
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cache_result = (config >> 16) & 0xff;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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return -EINVAL;
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2013-11-28 18:19:59 +08:00
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if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
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2013-11-07 21:55:11 +08:00
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return -EINVAL;
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2013-11-28 18:19:59 +08:00
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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2013-11-07 21:55:11 +08:00
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return -EINVAL;
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ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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2015-04-15 22:14:07 +08:00
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pr_debug("init cache event: type/op/result %d/%d/%d with h/w %d \'%s\'\n",
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cache_type, cache_op, cache_result, ret,
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arc_pmu_ev_hw_map[ret]);
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2013-11-07 21:55:11 +08:00
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return ret;
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}
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/* initializes hw_perf_event structure if event is supported */
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static int arc_pmu_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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int ret;
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2015-08-24 18:48:06 +08:00
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if (!is_sampling_event(event)) {
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2018-12-14 00:56:18 +08:00
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hwc->sample_period = arc_pmu->max_period;
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2015-08-24 18:48:06 +08:00
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hwc->last_period = hwc->sample_period;
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local64_set(&hwc->period_left, hwc->sample_period);
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}
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2015-08-24 18:42:27 +08:00
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2015-08-24 18:53:36 +08:00
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hwc->config = 0;
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if (is_isa_arcv2()) {
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/* "exclude user" means "count only kernel" */
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if (event->attr.exclude_user)
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hwc->config |= ARC_REG_PCT_CONFIG_KERN;
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/* "exclude kernel" means "count only user" */
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if (event->attr.exclude_kernel)
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hwc->config |= ARC_REG_PCT_CONFIG_USER;
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}
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2013-11-07 21:55:11 +08:00
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switch (event->attr.type) {
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case PERF_TYPE_HARDWARE:
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if (event->attr.config >= PERF_COUNT_HW_MAX)
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return -ENOENT;
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if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
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return -ENOENT;
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2015-08-24 18:53:36 +08:00
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hwc->config |= arc_pmu->ev_hw_idx[event->attr.config];
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2016-08-25 19:47:27 +08:00
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pr_debug("init event %d with h/w %08x \'%s\'\n",
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(int)event->attr.config, (int)hwc->config,
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2015-04-15 22:14:07 +08:00
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arc_pmu_ev_hw_map[event->attr.config]);
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2013-11-07 21:55:11 +08:00
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return 0;
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2015-08-24 18:42:27 +08:00
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2013-11-07 21:55:11 +08:00
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case PERF_TYPE_HW_CACHE:
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ret = arc_pmu_cache_event(event->attr.config);
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if (ret < 0)
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return ret;
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2015-08-24 18:53:36 +08:00
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hwc->config |= arc_pmu->ev_hw_idx[ret];
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2016-08-25 19:47:27 +08:00
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pr_debug("init cache event with h/w %08x \'%s\'\n",
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(int)hwc->config, arc_pmu_ev_hw_map[ret]);
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2013-11-07 21:55:11 +08:00
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return 0;
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2018-12-14 00:56:18 +08:00
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2018-12-14 00:56:19 +08:00
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case PERF_TYPE_RAW:
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if (event->attr.config >= arc_pmu->n_events)
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return -ENOENT;
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hwc->config |= event->attr.config;
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pr_debug("init raw event with idx %lld \'%s\'\n",
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event->attr.config,
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arc_pmu->raw_entry[event->attr.config].name);
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return 0;
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2013-11-07 21:55:11 +08:00
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default:
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return -ENOENT;
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}
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}
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/* starts all counters */
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static void arc_pmu_enable(struct pmu *pmu)
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{
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2018-12-14 00:56:18 +08:00
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u32 tmp;
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2013-11-07 21:55:11 +08:00
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
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}
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/* stops all counters */
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static void arc_pmu_disable(struct pmu *pmu)
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{
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2018-12-14 00:56:18 +08:00
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u32 tmp;
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2013-11-07 21:55:11 +08:00
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
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}
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2015-08-24 18:42:27 +08:00
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static int arc_pmu_event_set_period(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int idx = hwc->idx;
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int overflow = 0;
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u64 value;
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if (unlikely(left <= -period)) {
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/* left underflowed by more than period. */
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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2018-12-14 00:56:18 +08:00
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} else if (unlikely(left <= 0)) {
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2015-08-24 18:42:27 +08:00
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/* left underflowed by less than period. */
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (left > arc_pmu->max_period)
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left = arc_pmu->max_period;
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value = arc_pmu->max_period - left;
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local64_set(&hwc->prev_count, value);
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/* Select counter */
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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/* Write value */
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2018-12-14 00:56:18 +08:00
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write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value));
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write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value));
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2015-08-24 18:42:27 +08:00
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perf_event_update_userpage(event);
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return overflow;
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}
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2013-11-07 21:55:11 +08:00
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/*
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* Assigns hardware counter to hardware condition.
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* Note that there is no separate start/stop mechanism;
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* stopping is achieved by assigning the 'never' condition
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*/
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static void arc_pmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (WARN_ON_ONCE(idx == -1))
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return;
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if (flags & PERF_EF_RELOAD)
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2015-08-24 18:42:27 +08:00
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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2013-11-07 21:55:11 +08:00
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2015-08-24 18:42:27 +08:00
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arc_pmu_event_set_period(event);
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2013-11-07 21:55:11 +08:00
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2015-08-24 18:48:06 +08:00
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/* Enable interrupt for this counter */
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if (is_sampling_event(event))
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write_aux_reg(ARC_REG_PCT_INT_CTRL,
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2018-12-14 00:56:18 +08:00
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read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
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2015-08-24 18:48:06 +08:00
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2013-11-07 21:55:11 +08:00
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/* enable ARC pmu here */
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2015-08-19 19:53:58 +08:00
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|
write_aux_reg(ARC_REG_PCT_INDEX, idx); /* counter # */
|
|
|
|
write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */
|
2013-11-07 21:55:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void arc_pmu_stop(struct perf_event *event, int flags)
|
|
|
|
{
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
int idx = hwc->idx;
|
|
|
|
|
2015-08-24 18:48:06 +08:00
|
|
|
/* Disable interrupt for this counter */
|
|
|
|
if (is_sampling_event(event)) {
|
|
|
|
/*
|
|
|
|
* Reset interrupt flag by writing of 1. This is required
|
|
|
|
* to make sure pending interrupt was not left.
|
|
|
|
*/
|
2018-12-14 00:56:18 +08:00
|
|
|
write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
|
2015-08-24 18:48:06 +08:00
|
|
|
write_aux_reg(ARC_REG_PCT_INT_CTRL,
|
2018-12-14 00:56:18 +08:00
|
|
|
read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~BIT(idx));
|
2015-08-24 18:48:06 +08:00
|
|
|
}
|
|
|
|
|
2013-11-07 21:55:11 +08:00
|
|
|
if (!(event->hw.state & PERF_HES_STOPPED)) {
|
|
|
|
/* stop ARC pmu here */
|
|
|
|
write_aux_reg(ARC_REG_PCT_INDEX, idx);
|
|
|
|
|
|
|
|
/* condition code #0 is always "never" */
|
|
|
|
write_aux_reg(ARC_REG_PCT_CONFIG, 0);
|
|
|
|
|
|
|
|
event->hw.state |= PERF_HES_STOPPED;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((flags & PERF_EF_UPDATE) &&
|
|
|
|
!(event->hw.state & PERF_HES_UPTODATE)) {
|
|
|
|
arc_perf_event_update(event, &event->hw, idx);
|
|
|
|
event->hw.state |= PERF_HES_UPTODATE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void arc_pmu_del(struct perf_event *event, int flags)
|
|
|
|
{
|
2015-08-24 19:03:30 +08:00
|
|
|
struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
|
|
|
|
|
2013-11-07 21:55:11 +08:00
|
|
|
arc_pmu_stop(event, PERF_EF_UPDATE);
|
2015-08-24 19:03:30 +08:00
|
|
|
__clear_bit(event->hw.idx, pmu_cpu->used_mask);
|
2013-11-07 21:55:11 +08:00
|
|
|
|
2015-08-24 19:03:30 +08:00
|
|
|
pmu_cpu->act_counter[event->hw.idx] = 0;
|
2015-08-24 18:48:06 +08:00
|
|
|
|
2013-11-07 21:55:11 +08:00
|
|
|
perf_event_update_userpage(event);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* allocate hardware counter and optionally start counting */
|
|
|
|
static int arc_pmu_add(struct perf_event *event, int flags)
|
|
|
|
{
|
2015-08-24 19:03:30 +08:00
|
|
|
struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
|
2013-11-07 21:55:11 +08:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
int idx = hwc->idx;
|
|
|
|
|
2015-10-09 00:47:48 +08:00
|
|
|
idx = ffz(pmu_cpu->used_mask[0]);
|
|
|
|
if (idx == arc_pmu->n_counters)
|
|
|
|
return -EAGAIN;
|
|
|
|
|
|
|
|
__set_bit(idx, pmu_cpu->used_mask);
|
|
|
|
hwc->idx = idx;
|
2013-11-07 21:55:11 +08:00
|
|
|
|
|
|
|
write_aux_reg(ARC_REG_PCT_INDEX, idx);
|
2015-08-24 18:48:06 +08:00
|
|
|
|
2015-08-24 19:03:30 +08:00
|
|
|
pmu_cpu->act_counter[idx] = event;
|
2015-08-24 18:48:06 +08:00
|
|
|
|
|
|
|
if (is_sampling_event(event)) {
|
|
|
|
/* Mimic full counter overflow as other arches do */
|
2018-12-14 00:56:18 +08:00
|
|
|
write_aux_reg(ARC_REG_PCT_INT_CNTL,
|
|
|
|
lower_32_bits(arc_pmu->max_period));
|
2015-08-24 18:48:06 +08:00
|
|
|
write_aux_reg(ARC_REG_PCT_INT_CNTH,
|
2018-12-14 00:56:18 +08:00
|
|
|
upper_32_bits(arc_pmu->max_period));
|
2015-08-24 18:48:06 +08:00
|
|
|
}
|
|
|
|
|
2013-11-07 21:55:11 +08:00
|
|
|
write_aux_reg(ARC_REG_PCT_CONFIG, 0);
|
|
|
|
write_aux_reg(ARC_REG_PCT_COUNTL, 0);
|
|
|
|
write_aux_reg(ARC_REG_PCT_COUNTH, 0);
|
|
|
|
local64_set(&hwc->prev_count, 0);
|
|
|
|
|
|
|
|
hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
|
|
|
|
if (flags & PERF_EF_START)
|
|
|
|
arc_pmu_start(event, PERF_EF_RELOAD);
|
|
|
|
|
|
|
|
perf_event_update_userpage(event);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-08-24 18:48:06 +08:00
|
|
|
#ifdef CONFIG_ISA_ARCV2
|
|
|
|
static irqreturn_t arc_pmu_intr(int irq, void *dev)
|
|
|
|
{
|
|
|
|
struct perf_sample_data data;
|
2015-08-24 19:03:30 +08:00
|
|
|
struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
|
2015-08-24 18:48:06 +08:00
|
|
|
struct pt_regs *regs;
|
2015-05-09 20:57:30 +08:00
|
|
|
unsigned int active_ints;
|
2015-08-24 18:48:06 +08:00
|
|
|
int idx;
|
|
|
|
|
|
|
|
arc_pmu_disable(&arc_pmu->pmu);
|
|
|
|
|
|
|
|
active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT);
|
2015-05-09 20:57:30 +08:00
|
|
|
if (!active_ints)
|
|
|
|
goto done;
|
2015-08-24 18:48:06 +08:00
|
|
|
|
|
|
|
regs = get_irq_regs();
|
|
|
|
|
2015-05-09 20:57:30 +08:00
|
|
|
do {
|
|
|
|
struct perf_event *event;
|
2015-08-24 18:48:06 +08:00
|
|
|
struct hw_perf_event *hwc;
|
|
|
|
|
2015-05-09 20:57:30 +08:00
|
|
|
idx = __ffs(active_ints);
|
2015-08-24 18:48:06 +08:00
|
|
|
|
|
|
|
/* Reset interrupt flag by writing of 1 */
|
2018-12-14 00:56:18 +08:00
|
|
|
write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));
|
2015-08-24 18:48:06 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* On reset of "interrupt active" bit corresponding
|
|
|
|
* "interrupt enable" bit gets automatically reset as well.
|
|
|
|
* Now we need to re-enable interrupt for the counter.
|
|
|
|
*/
|
|
|
|
write_aux_reg(ARC_REG_PCT_INT_CTRL,
|
2018-12-14 00:56:18 +08:00
|
|
|
read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
|
2015-08-24 18:48:06 +08:00
|
|
|
|
2015-05-09 20:57:30 +08:00
|
|
|
event = pmu_cpu->act_counter[idx];
|
2015-08-24 18:48:06 +08:00
|
|
|
hwc = &event->hw;
|
|
|
|
|
|
|
|
WARN_ON_ONCE(hwc->idx != idx);
|
|
|
|
|
|
|
|
arc_perf_event_update(event, &event->hw, event->hw.idx);
|
|
|
|
perf_sample_data_init(&data, 0, hwc->last_period);
|
2015-05-09 20:57:30 +08:00
|
|
|
if (arc_pmu_event_set_period(event)) {
|
|
|
|
if (perf_event_overflow(event, &data, regs))
|
|
|
|
arc_pmu_stop(event, 0);
|
|
|
|
}
|
2015-08-24 18:48:06 +08:00
|
|
|
|
2018-12-14 00:56:18 +08:00
|
|
|
active_ints &= ~BIT(idx);
|
2015-05-09 20:57:30 +08:00
|
|
|
} while (active_ints);
|
2015-08-24 18:48:06 +08:00
|
|
|
|
2015-05-09 20:57:30 +08:00
|
|
|
done:
|
2015-08-24 18:48:06 +08:00
|
|
|
arc_pmu_enable(&arc_pmu->pmu);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
|
|
|
|
static irqreturn_t arc_pmu_intr(int irq, void *dev)
|
|
|
|
{
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_ISA_ARCV2 */
|
|
|
|
|
2015-12-11 15:43:12 +08:00
|
|
|
static void arc_cpu_pmu_irq_init(void *data)
|
2015-08-24 19:03:30 +08:00
|
|
|
{
|
2015-12-11 15:43:12 +08:00
|
|
|
int irq = *(int *)data;
|
2015-08-24 19:03:30 +08:00
|
|
|
|
2015-12-11 15:43:12 +08:00
|
|
|
enable_percpu_irq(irq, IRQ_TYPE_NONE);
|
2015-08-24 19:03:30 +08:00
|
|
|
|
|
|
|
/* Clear all pending interrupt flags */
|
|
|
|
write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);
|
|
|
|
}
|
|
|
|
|
2018-12-14 00:56:19 +08:00
|
|
|
/* Event field occupies the bottom 15 bits of our config field */
|
|
|
|
PMU_FORMAT_ATTR(event, "config:0-14");
|
|
|
|
static struct attribute *arc_pmu_format_attrs[] = {
|
|
|
|
&format_attr_event.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group arc_pmu_format_attr_gr = {
|
|
|
|
.name = "format",
|
|
|
|
.attrs = arc_pmu_format_attrs,
|
|
|
|
};
|
|
|
|
|
|
|
|
static ssize_t arc_pmu_events_sysfs_show(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
char *page)
|
|
|
|
{
|
|
|
|
struct perf_pmu_events_attr *pmu_attr;
|
|
|
|
|
|
|
|
pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
|
|
|
|
return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We don't add attrs here as we don't have pre-defined list of perf events.
|
|
|
|
* We will generate and add attrs dynamically in probe() after we read HW
|
|
|
|
* configuration.
|
|
|
|
*/
|
|
|
|
static struct attribute_group arc_pmu_events_attr_gr = {
|
|
|
|
.name = "events",
|
|
|
|
};
|
|
|
|
|
|
|
|
static void arc_pmu_add_raw_event_attr(int j, char *str)
|
|
|
|
{
|
|
|
|
memmove(arc_pmu->raw_entry[j].name, str, ARCPMU_EVENT_NAME_LEN - 1);
|
|
|
|
arc_pmu->attr[j].attr.attr.name = arc_pmu->raw_entry[j].name;
|
|
|
|
arc_pmu->attr[j].attr.attr.mode = VERIFY_OCTAL_PERMISSIONS(0444);
|
|
|
|
arc_pmu->attr[j].attr.show = arc_pmu_events_sysfs_show;
|
|
|
|
arc_pmu->attr[j].id = j;
|
|
|
|
arc_pmu->attrs[j] = &(arc_pmu->attr[j].attr.attr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int arc_pmu_raw_alloc(struct device *dev)
|
|
|
|
{
|
|
|
|
arc_pmu->attr = devm_kmalloc_array(dev, arc_pmu->n_events + 1,
|
|
|
|
sizeof(*arc_pmu->attr), GFP_KERNEL | __GFP_ZERO);
|
|
|
|
if (!arc_pmu->attr)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
arc_pmu->attrs = devm_kmalloc_array(dev, arc_pmu->n_events + 1,
|
|
|
|
sizeof(*arc_pmu->attrs), GFP_KERNEL | __GFP_ZERO);
|
|
|
|
if (!arc_pmu->attrs)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
arc_pmu->raw_entry = devm_kmalloc_array(dev, arc_pmu->n_events,
|
|
|
|
sizeof(*arc_pmu->raw_entry), GFP_KERNEL | __GFP_ZERO);
|
|
|
|
if (!arc_pmu->raw_entry)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-07 21:55:11 +08:00
|
|
|
static int arc_pmu_device_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct arc_reg_pct_build pct_bcr;
|
|
|
|
struct arc_reg_cc_build cc_bcr;
|
2015-08-24 18:48:06 +08:00
|
|
|
int i, j, has_interrupts;
|
2015-08-24 18:42:27 +08:00
|
|
|
int counter_size; /* in bits */
|
2013-11-07 21:55:11 +08:00
|
|
|
|
|
|
|
union cc_name {
|
|
|
|
struct {
|
2018-12-14 00:56:18 +08:00
|
|
|
u32 word0, word1;
|
2013-11-07 21:55:11 +08:00
|
|
|
char sentinel;
|
|
|
|
} indiv;
|
2018-12-14 00:56:18 +08:00
|
|
|
char str[ARCPMU_EVENT_NAME_LEN];
|
2013-11-07 21:55:11 +08:00
|
|
|
} cc_name;
|
|
|
|
|
|
|
|
|
|
|
|
READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
|
|
|
|
if (!pct_bcr.v) {
|
|
|
|
pr_err("This core does not have performance counters!\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2015-10-09 00:47:48 +08:00
|
|
|
BUILD_BUG_ON(ARC_PERF_MAX_COUNTERS > 32);
|
2015-08-24 18:37:01 +08:00
|
|
|
BUG_ON(pct_bcr.c > ARC_PERF_MAX_COUNTERS);
|
2013-11-07 21:55:11 +08:00
|
|
|
|
2014-09-25 19:24:43 +08:00
|
|
|
READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
|
2015-04-20 19:19:30 +08:00
|
|
|
BUG_ON(!cc_bcr.v); /* Counters exist but No countable conditions ? */
|
2014-09-25 19:24:43 +08:00
|
|
|
|
|
|
|
arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL);
|
2013-11-07 21:55:11 +08:00
|
|
|
if (!arc_pmu)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2018-12-14 00:56:19 +08:00
|
|
|
arc_pmu->n_events = cc_bcr.c;
|
|
|
|
|
|
|
|
if (arc_pmu_raw_alloc(&pdev->dev))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-08-24 18:48:06 +08:00
|
|
|
has_interrupts = is_isa_arcv2() ? pct_bcr.i : 0;
|
|
|
|
|
2013-11-07 21:55:11 +08:00
|
|
|
arc_pmu->n_counters = pct_bcr.c;
|
2015-08-24 18:42:27 +08:00
|
|
|
counter_size = 32 + (pct_bcr.s << 4);
|
2015-08-24 18:48:06 +08:00
|
|
|
|
2015-08-24 18:42:27 +08:00
|
|
|
arc_pmu->max_period = (1ULL << counter_size) / 2 - 1ULL;
|
2013-11-07 21:55:11 +08:00
|
|
|
|
2015-08-24 18:48:06 +08:00
|
|
|
pr_info("ARC perf\t: %d counters (%d bits), %d conditions%s\n",
|
|
|
|
arc_pmu->n_counters, counter_size, cc_bcr.c,
|
2018-12-14 00:56:18 +08:00
|
|
|
has_interrupts ? ", [overflow IRQ support]" : "");
|
2013-11-07 21:55:11 +08:00
|
|
|
|
2018-12-14 00:56:18 +08:00
|
|
|
cc_name.str[ARCPMU_EVENT_NAME_LEN - 1] = 0;
|
2015-04-15 22:14:07 +08:00
|
|
|
for (i = 0; i < PERF_COUNT_ARC_HW_MAX; i++)
|
2013-11-07 21:55:11 +08:00
|
|
|
arc_pmu->ev_hw_idx[i] = -1;
|
|
|
|
|
2015-04-15 22:14:07 +08:00
|
|
|
/* loop thru all available h/w condition indexes */
|
2013-11-07 21:55:11 +08:00
|
|
|
for (j = 0; j < cc_bcr.c; j++) {
|
|
|
|
write_aux_reg(ARC_REG_CC_INDEX, j);
|
|
|
|
cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
|
|
|
|
cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
|
2015-04-15 22:14:07 +08:00
|
|
|
|
|
|
|
/* See if it has been mapped to a perf event_id */
|
2013-11-07 21:55:11 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
|
|
|
|
if (arc_pmu_ev_hw_map[i] &&
|
|
|
|
!strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
|
|
|
|
strlen(arc_pmu_ev_hw_map[i])) {
|
2015-04-15 22:14:07 +08:00
|
|
|
pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n",
|
|
|
|
i, cc_name.str, j);
|
2013-11-07 21:55:11 +08:00
|
|
|
arc_pmu->ev_hw_idx[i] = j;
|
|
|
|
}
|
|
|
|
}
|
2018-12-14 00:56:19 +08:00
|
|
|
|
|
|
|
arc_pmu_add_raw_event_attr(j, cc_name.str);
|
2013-11-07 21:55:11 +08:00
|
|
|
}
|
|
|
|
|
2018-12-14 00:56:19 +08:00
|
|
|
arc_pmu_events_attr_gr.attrs = arc_pmu->attrs;
|
|
|
|
arc_pmu->attr_groups[ARCPMU_ATTR_GR_EVENTS] = &arc_pmu_events_attr_gr;
|
|
|
|
arc_pmu->attr_groups[ARCPMU_ATTR_GR_FORMATS] = &arc_pmu_format_attr_gr;
|
|
|
|
|
2013-11-07 21:55:11 +08:00
|
|
|
arc_pmu->pmu = (struct pmu) {
|
|
|
|
.pmu_enable = arc_pmu_enable,
|
|
|
|
.pmu_disable = arc_pmu_disable,
|
|
|
|
.event_init = arc_pmu_event_init,
|
|
|
|
.add = arc_pmu_add,
|
|
|
|
.del = arc_pmu_del,
|
|
|
|
.start = arc_pmu_start,
|
|
|
|
.stop = arc_pmu_stop,
|
|
|
|
.read = arc_pmu_read,
|
2018-12-14 00:56:19 +08:00
|
|
|
.attr_groups = arc_pmu->attr_groups,
|
2013-11-07 21:55:11 +08:00
|
|
|
};
|
|
|
|
|
2015-08-24 18:48:06 +08:00
|
|
|
if (has_interrupts) {
|
|
|
|
int irq = platform_get_irq(pdev, 0);
|
|
|
|
|
|
|
|
if (irq < 0) {
|
|
|
|
pr_err("Cannot get IRQ number for the platform\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2015-08-24 19:03:30 +08:00
|
|
|
arc_pmu->irq = irq;
|
|
|
|
|
2015-12-11 15:43:12 +08:00
|
|
|
/* intc map function ensures irq_set_percpu_devid() called */
|
|
|
|
request_percpu_irq(irq, arc_pmu_intr, "ARC perf counters",
|
|
|
|
this_cpu_ptr(&arc_pmu_cpu));
|
|
|
|
|
|
|
|
on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);
|
|
|
|
|
2015-08-24 18:48:06 +08:00
|
|
|
} else
|
|
|
|
arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
|
2014-06-15 14:00:18 +08:00
|
|
|
|
2018-12-14 00:56:19 +08:00
|
|
|
/*
|
|
|
|
* perf parser doesn't really like '-' symbol in events name, so let's
|
|
|
|
* use '_' in arc pct name as it goes to kernel PMU event prefix.
|
|
|
|
*/
|
|
|
|
return perf_pmu_register(&arc_pmu->pmu, "arc_pct", PERF_TYPE_RAW);
|
2013-11-07 21:55:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id arc_pmu_match[] = {
|
2015-04-15 19:05:38 +08:00
|
|
|
{ .compatible = "snps,arc700-pct" },
|
2014-11-18 20:06:11 +08:00
|
|
|
{ .compatible = "snps,archs-pct" },
|
2013-11-07 21:55:11 +08:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, arc_pmu_match);
|
|
|
|
|
|
|
|
static struct platform_driver arc_pmu_driver = {
|
|
|
|
.driver = {
|
2014-11-18 20:06:11 +08:00
|
|
|
.name = "arc-pct",
|
2013-11-07 21:55:11 +08:00
|
|
|
.of_match_table = of_match_ptr(arc_pmu_match),
|
|
|
|
},
|
|
|
|
.probe = arc_pmu_device_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(arc_pmu_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
|
|
|
|
MODULE_DESCRIPTION("ARC PMU driver");
|