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OpenCloudOS-Kernel/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi

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ARM: dts: imx: sabrelite: add Dual Lite/Solo support This makes the structure of Sabre Lite board files the same as Sabre SD board files so that they are easier to compare. By this, I mean that the majority of the file imx6q-sabrelite.dts is moved to imx6qdl-sabrelite.dtsi so that both imx6q-sabrelite.dts and imx6dl-sabrelite.dts can include it. Now Sabre Lite has support for Dual Lite/Solo processors. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-13 09:49:05 +08:00
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/ {
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 201>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-sabrelite {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
ARM: dts: imx6qdl-sabrelite: Add uart1 support Uart1 is available on Sabre Lite. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-13 09:49:06 +08:00
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
ARM: dts: imx: sabrelite: add Dual Lite/Solo support This makes the structure of Sabre Lite board files the same as Sabre SD board files so that they are easier to compare. By this, I mean that the majority of the file imx6q-sabrelite.dts is moved to imx6qdl-sabrelite.dtsi so that both imx6q-sabrelite.dts and imx6dl-sabrelite.dts can include it. Now Sabre Lite has support for Dual Lite/Solo processors. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-13 09:49:05 +08:00
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
ARM: dts: imx6qdl-sabrelite: move USDHC4 CD to pinctrl_usdhc4 This patch moves pin NANDF_D6 (CD) from pinctrl_hog to pinctrl_usdhc4. It also explicitly sets the pad to 0x1b0b0, which is also the value that it has before this patch if using mainline u-boot. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-17 09:12:52 +08:00
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
ARM: dts: imx: sabrelite: add Dual Lite/Solo support This makes the structure of Sabre Lite board files the same as Sabre SD board files so that they are easier to compare. By this, I mean that the majority of the file imx6q-sabrelite.dts is moved to imx6qdl-sabrelite.dtsi so that both imx6q-sabrelite.dts and imx6dl-sabrelite.dts can include it. Now Sabre Lite has support for Dual Lite/Solo processors. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-13 09:49:05 +08:00
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pcie {
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
ARM: dts: imx6qdl-sabrelite: Add uart1 support Uart1 is available on Sabre Lite. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-13 09:49:06 +08:00
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
ARM: dts: imx: sabrelite: add Dual Lite/Solo support This makes the structure of Sabre Lite board files the same as Sabre SD board files so that they are easier to compare. By this, I mean that the majority of the file imx6q-sabrelite.dts is moved to imx6qdl-sabrelite.dtsi so that both imx6q-sabrelite.dts and imx6dl-sabrelite.dts can include it. Now Sabre Lite has support for Dual Lite/Solo processors. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-13 09:49:05 +08:00
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio2 6 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};