OpenCloudOS-Kernel/arch/arm/boot/dts/mt8135.dtsi

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Joe.C <yingjoe.chen@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"

/ {
	compatible = "mediatek,mt8135";
	interrupt-parent = <&sysirq>;

	cpu-map {
		cluster0 {
			core0 {
				cpu = <&cpu0>;
			};
			core1 {
				cpu = <&cpu1>;
			};
		};

		cluster1 {
			core0 {
				cpu = <&cpu2>;
			};
			core1 {
				cpu = <&cpu3>;
			};
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x001>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x100>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x101>;
		};
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		system_clk: dummy13m {
			compatible = "fixed-clock";
			clock-frequency = <13000000>;
			#clock-cells = <0>;
		};

		rtc_clk: dummy32k {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		uart_clk: dummy26m {
			compatible = "fixed-clock";
			clock-frequency = <26000000>;
			#clock-cells = <0>;
		};

	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		timer: timer@10008000 {
			compatible = "mediatek,mt8135-timer",
					"mediatek,mt6577-timer";
			reg = <0 0x10008000 0 0x80>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&rtc_clk>;
			clock-names = "system-clk", "rtc-clk";
		};

		sysirq: interrupt-controller@10200030 {
			compatible = "mediatek,mt8135-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200030 0 0x1c>;
		};

		gic: interrupt-controller@10211000 {
			compatible = "arm,cortex-a15-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10211000 0 0x1000>,
			      <0 0x10212000 0 0x1000>,
			      <0 0x10214000 0 0x2000>,
			      <0 0x10216000 0 0x2000>;
		};

		uart0: serial@11006000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11006000 0 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@11007000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11007000 0 0x400>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@11008000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11008000 0 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart3: serial@11009000 {
			compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
			reg = <0 0x11009000 0 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

	};
};