2012-05-19 01:47:40 +08:00
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/*
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* Realtek RTL2832 DVB-T demodulator driver
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*
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* Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
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2014-12-17 00:54:23 +08:00
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* Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
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2012-05-19 01:47:40 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef RTL2832_PRIV_H
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#define RTL2832_PRIV_H
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2014-12-14 15:45:57 +08:00
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#include <linux/regmap.h>
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2014-12-14 21:05:49 +08:00
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#include <linux/math64.h>
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2014-12-17 00:37:18 +08:00
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#include <linux/bitops.h>
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2017-12-29 02:03:51 +08:00
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#include <media/dvb_frontend.h>
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#include <media/dvb_math.h>
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2014-12-17 00:37:18 +08:00
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#include "rtl2832.h"
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2012-05-19 01:47:40 +08:00
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2014-12-13 11:37:43 +08:00
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struct rtl2832_dev {
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2014-12-13 16:26:27 +08:00
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struct rtl2832_platform_data *pdata;
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2014-12-02 21:55:17 +08:00
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struct i2c_client *client;
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2014-12-18 18:22:46 +08:00
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struct regmap_config regmap_config;
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2014-12-14 15:45:57 +08:00
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struct regmap *regmap;
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2016-04-20 14:41:25 +08:00
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struct i2c_mux_core *muxc;
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2012-05-19 01:47:40 +08:00
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struct dvb_frontend fe;
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2015-06-08 01:53:52 +08:00
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enum fe_status fe_status;
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2014-12-14 21:10:22 +08:00
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u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
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2014-12-14 20:59:20 +08:00
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u64 post_bit_error;
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u64 post_bit_count;
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2012-05-19 01:47:40 +08:00
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bool sleeping;
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2014-02-08 14:50:04 +08:00
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struct delayed_work i2c_gate_work;
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2014-12-15 01:07:35 +08:00
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unsigned long filters; /* PID filter */
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2016-06-08 05:31:47 +08:00
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bool slave_ts;
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2012-05-19 01:47:40 +08:00
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};
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struct rtl2832_reg_entry {
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2014-12-15 12:17:25 +08:00
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u16 start_address;
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2012-05-19 01:47:40 +08:00
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u8 msb;
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u8 lsb;
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};
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struct rtl2832_reg_value {
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int reg;
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u32 value;
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};
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/* Demod register bit names */
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enum DVBT_REG_BIT_NAME {
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DVBT_SOFT_RST,
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DVBT_IIC_REPEAT,
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DVBT_TR_WAIT_MIN_8K,
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DVBT_RSD_BER_FAIL_VAL,
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DVBT_EN_BK_TRK,
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DVBT_REG_PI,
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DVBT_REG_PFREQ_1_0,
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DVBT_PD_DA8,
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DVBT_LOCK_TH,
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DVBT_BER_PASS_SCAL,
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DVBT_CE_FFSM_BYPASS,
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DVBT_ALPHAIIR_N,
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DVBT_ALPHAIIR_DIF,
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DVBT_EN_TRK_SPAN,
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DVBT_LOCK_TH_LEN,
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DVBT_CCI_THRE,
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DVBT_CCI_MON_SCAL,
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DVBT_CCI_M0,
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DVBT_CCI_M1,
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DVBT_CCI_M2,
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DVBT_CCI_M3,
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DVBT_SPEC_INIT_0,
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DVBT_SPEC_INIT_1,
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DVBT_SPEC_INIT_2,
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DVBT_AD_EN_REG,
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DVBT_AD_EN_REG1,
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DVBT_EN_BBIN,
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DVBT_MGD_THD0,
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DVBT_MGD_THD1,
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DVBT_MGD_THD2,
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DVBT_MGD_THD3,
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DVBT_MGD_THD4,
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DVBT_MGD_THD5,
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DVBT_MGD_THD6,
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DVBT_MGD_THD7,
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DVBT_EN_CACQ_NOTCH,
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DVBT_AD_AV_REF,
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DVBT_PIP_ON,
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DVBT_SCALE1_B92,
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DVBT_SCALE1_B93,
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DVBT_SCALE1_BA7,
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DVBT_SCALE1_BA9,
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DVBT_SCALE1_BAA,
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DVBT_SCALE1_BAB,
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DVBT_SCALE1_BAC,
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DVBT_SCALE1_BB0,
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DVBT_SCALE1_BB1,
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DVBT_KB_P1,
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DVBT_KB_P2,
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DVBT_KB_P3,
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DVBT_OPT_ADC_IQ,
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DVBT_AD_AVI,
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DVBT_AD_AVQ,
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DVBT_K1_CR_STEP12,
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DVBT_TRK_KS_P2,
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DVBT_TRK_KS_I2,
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DVBT_TR_THD_SET2,
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DVBT_TRK_KC_P2,
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DVBT_TRK_KC_I2,
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DVBT_CR_THD_SET2,
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DVBT_PSET_IFFREQ,
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DVBT_SPEC_INV,
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DVBT_BW_INDEX,
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DVBT_RSAMP_RATIO,
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DVBT_CFREQ_OFF_RATIO,
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DVBT_FSM_STAGE,
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DVBT_RX_CONSTEL,
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DVBT_RX_HIER,
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DVBT_RX_C_RATE_LP,
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DVBT_RX_C_RATE_HP,
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DVBT_GI_IDX,
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DVBT_FFT_MODE_IDX,
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DVBT_RSD_BER_EST,
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DVBT_CE_EST_EVM,
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DVBT_RF_AGC_VAL,
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DVBT_IF_AGC_VAL,
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DVBT_DAGC_VAL,
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DVBT_SFREQ_OFF,
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DVBT_CFREQ_OFF,
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DVBT_POLAR_RF_AGC,
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DVBT_POLAR_IF_AGC,
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DVBT_AAGC_HOLD,
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DVBT_EN_RF_AGC,
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DVBT_EN_IF_AGC,
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DVBT_IF_AGC_MIN,
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DVBT_IF_AGC_MAX,
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DVBT_RF_AGC_MIN,
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DVBT_RF_AGC_MAX,
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DVBT_IF_AGC_MAN,
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DVBT_IF_AGC_MAN_VAL,
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DVBT_RF_AGC_MAN,
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DVBT_RF_AGC_MAN_VAL,
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DVBT_DAGC_TRG_VAL,
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DVBT_AGC_TARG_VAL,
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DVBT_LOOP_GAIN_3_0,
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DVBT_LOOP_GAIN_4,
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DVBT_VTOP,
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DVBT_KRF,
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DVBT_AGC_TARG_VAL_0,
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DVBT_AGC_TARG_VAL_8_1,
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DVBT_AAGC_LOOP_GAIN,
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DVBT_LOOP_GAIN2_3_0,
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DVBT_LOOP_GAIN2_4,
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DVBT_LOOP_GAIN3,
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DVBT_VTOP1,
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DVBT_VTOP2,
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DVBT_VTOP3,
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DVBT_KRF1,
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DVBT_KRF2,
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DVBT_KRF3,
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DVBT_KRF4,
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DVBT_EN_GI_PGA,
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DVBT_THD_LOCK_UP,
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DVBT_THD_LOCK_DW,
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DVBT_THD_UP1,
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DVBT_THD_DW1,
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DVBT_INTER_CNT_LEN,
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DVBT_GI_PGA_STATE,
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DVBT_EN_AGC_PGA,
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DVBT_CKOUTPAR,
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DVBT_CKOUT_PWR,
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DVBT_SYNC_DUR,
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DVBT_ERR_DUR,
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DVBT_SYNC_LVL,
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DVBT_ERR_LVL,
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DVBT_VAL_LVL,
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DVBT_SERIAL,
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DVBT_SER_LSB,
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DVBT_CDIV_PH0,
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DVBT_CDIV_PH1,
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DVBT_MPEG_IO_OPT_2_2,
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DVBT_MPEG_IO_OPT_1_0,
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DVBT_CKOUTPAR_PIP,
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DVBT_CKOUT_PWR_PIP,
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DVBT_SYNC_LVL_PIP,
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DVBT_ERR_LVL_PIP,
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DVBT_VAL_LVL_PIP,
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DVBT_CKOUTPAR_PID,
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DVBT_CKOUT_PWR_PID,
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DVBT_SYNC_LVL_PID,
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DVBT_ERR_LVL_PID,
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DVBT_VAL_LVL_PID,
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DVBT_SM_PASS,
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DVBT_UPDATE_REG_2,
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DVBT_BTHD_P3,
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DVBT_BTHD_D3,
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DVBT_FUNC4_REG0,
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DVBT_FUNC4_REG1,
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DVBT_FUNC4_REG2,
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DVBT_FUNC4_REG3,
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DVBT_FUNC4_REG4,
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DVBT_FUNC4_REG5,
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DVBT_FUNC4_REG6,
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DVBT_FUNC4_REG7,
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DVBT_FUNC4_REG8,
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DVBT_FUNC4_REG9,
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DVBT_FUNC4_REG10,
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DVBT_FUNC5_REG0,
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DVBT_FUNC5_REG1,
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DVBT_FUNC5_REG2,
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DVBT_FUNC5_REG3,
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DVBT_FUNC5_REG4,
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DVBT_FUNC5_REG5,
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DVBT_FUNC5_REG6,
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DVBT_FUNC5_REG7,
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DVBT_FUNC5_REG8,
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DVBT_FUNC5_REG9,
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DVBT_FUNC5_REG10,
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DVBT_FUNC5_REG11,
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DVBT_FUNC5_REG12,
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DVBT_FUNC5_REG13,
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DVBT_FUNC5_REG14,
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DVBT_FUNC5_REG15,
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DVBT_FUNC5_REG16,
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DVBT_FUNC5_REG17,
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DVBT_FUNC5_REG18,
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DVBT_AD7_SETTING,
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DVBT_RSSI_R,
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DVBT_ACI_DET_IND,
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DVBT_REG_MON,
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DVBT_REG_MONSEL,
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DVBT_REG_GPE,
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DVBT_REG_GPO,
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DVBT_REG_4MSEL,
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DVBT_TEST_REG_1,
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DVBT_TEST_REG_2,
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DVBT_TEST_REG_3,
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DVBT_TEST_REG_4,
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DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
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};
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2015-04-24 09:52:07 +08:00
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static const struct rtl2832_reg_value rtl2832_tuner_init_fc2580[] = {
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{DVBT_DAGC_TRG_VAL, 0x39},
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{DVBT_AGC_TARG_VAL_0, 0x0},
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{DVBT_AGC_TARG_VAL_8_1, 0x5a},
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{DVBT_AAGC_LOOP_GAIN, 0x16},
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{DVBT_LOOP_GAIN2_3_0, 0x6},
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{DVBT_LOOP_GAIN2_4, 0x1},
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{DVBT_LOOP_GAIN3, 0x16},
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{DVBT_VTOP1, 0x35},
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{DVBT_VTOP2, 0x21},
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{DVBT_VTOP3, 0x21},
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{DVBT_KRF1, 0x0},
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{DVBT_KRF2, 0x40},
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{DVBT_KRF3, 0x10},
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{DVBT_KRF4, 0x10},
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{DVBT_IF_AGC_MIN, 0x80},
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{DVBT_IF_AGC_MAX, 0x7f},
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{DVBT_RF_AGC_MIN, 0x9c},
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{DVBT_RF_AGC_MAX, 0x7f},
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{DVBT_POLAR_RF_AGC, 0x0},
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{DVBT_POLAR_IF_AGC, 0x0},
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{DVBT_AD7_SETTING, 0xe9f4},
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};
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2012-09-12 09:27:08 +08:00
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static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
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{DVBT_DAGC_TRG_VAL, 0x39},
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{DVBT_AGC_TARG_VAL_0, 0x0},
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{DVBT_AGC_TARG_VAL_8_1, 0x5a},
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{DVBT_AAGC_LOOP_GAIN, 0x16},
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{DVBT_LOOP_GAIN2_3_0, 0x6},
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{DVBT_LOOP_GAIN2_4, 0x1},
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{DVBT_LOOP_GAIN3, 0x16},
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{DVBT_VTOP1, 0x35},
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{DVBT_VTOP2, 0x21},
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{DVBT_VTOP3, 0x21},
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{DVBT_KRF1, 0x0},
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{DVBT_KRF2, 0x40},
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{DVBT_KRF3, 0x10},
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{DVBT_KRF4, 0x10},
|
|
|
|
|
{DVBT_IF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_IF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_RF_AGC_MIN, 0x9c},
|
|
|
|
|
{DVBT_RF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_POLAR_RF_AGC, 0x0},
|
|
|
|
|
{DVBT_POLAR_IF_AGC, 0x0},
|
|
|
|
|
{DVBT_AD7_SETTING, 0xe9f4},
|
|
|
|
|
{DVBT_OPT_ADC_IQ, 0x1},
|
|
|
|
|
{DVBT_AD_AVI, 0x0},
|
|
|
|
|
{DVBT_AD_AVQ, 0x0},
|
2013-10-13 11:06:44 +08:00
|
|
|
{DVBT_SPEC_INV, 0x0},
|
2012-09-12 09:27:08 +08:00
|
|
|
};
|
|
|
|
|
|
2012-09-12 09:27:04 +08:00
|
|
|
static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
|
|
|
|
|
{DVBT_DAGC_TRG_VAL, 0x5a},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_0, 0x0},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_8_1, 0x5a},
|
|
|
|
|
{DVBT_AAGC_LOOP_GAIN, 0x16},
|
|
|
|
|
{DVBT_LOOP_GAIN2_3_0, 0x6},
|
|
|
|
|
{DVBT_LOOP_GAIN2_4, 0x1},
|
|
|
|
|
{DVBT_LOOP_GAIN3, 0x16},
|
|
|
|
|
{DVBT_VTOP1, 0x35},
|
|
|
|
|
{DVBT_VTOP2, 0x21},
|
|
|
|
|
{DVBT_VTOP3, 0x21},
|
|
|
|
|
{DVBT_KRF1, 0x0},
|
|
|
|
|
{DVBT_KRF2, 0x40},
|
|
|
|
|
{DVBT_KRF3, 0x10},
|
|
|
|
|
{DVBT_KRF4, 0x10},
|
|
|
|
|
{DVBT_IF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_IF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_RF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_RF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_POLAR_RF_AGC, 0x0},
|
|
|
|
|
{DVBT_POLAR_IF_AGC, 0x0},
|
|
|
|
|
{DVBT_AD7_SETTING, 0xe9bf},
|
|
|
|
|
{DVBT_EN_GI_PGA, 0x0},
|
|
|
|
|
{DVBT_THD_LOCK_UP, 0x0},
|
|
|
|
|
{DVBT_THD_LOCK_DW, 0x0},
|
|
|
|
|
{DVBT_THD_UP1, 0x11},
|
|
|
|
|
{DVBT_THD_DW1, 0xef},
|
|
|
|
|
{DVBT_INTER_CNT_LEN, 0xc},
|
|
|
|
|
{DVBT_GI_PGA_STATE, 0x0},
|
|
|
|
|
{DVBT_EN_AGC_PGA, 0x1},
|
|
|
|
|
{DVBT_IF_AGC_MAN, 0x0},
|
2013-10-13 11:06:44 +08:00
|
|
|
{DVBT_SPEC_INV, 0x0},
|
2012-09-12 09:27:04 +08:00
|
|
|
};
|
|
|
|
|
|
2012-09-18 04:53:04 +08:00
|
|
|
static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
|
|
|
|
|
{DVBT_DAGC_TRG_VAL, 0x5a},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_0, 0x0},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_8_1, 0x5a},
|
|
|
|
|
{DVBT_AAGC_LOOP_GAIN, 0x18},
|
|
|
|
|
{DVBT_LOOP_GAIN2_3_0, 0x8},
|
|
|
|
|
{DVBT_LOOP_GAIN2_4, 0x1},
|
|
|
|
|
{DVBT_LOOP_GAIN3, 0x18},
|
|
|
|
|
{DVBT_VTOP1, 0x35},
|
|
|
|
|
{DVBT_VTOP2, 0x21},
|
|
|
|
|
{DVBT_VTOP3, 0x21},
|
|
|
|
|
{DVBT_KRF1, 0x0},
|
|
|
|
|
{DVBT_KRF2, 0x40},
|
|
|
|
|
{DVBT_KRF3, 0x10},
|
|
|
|
|
{DVBT_KRF4, 0x10},
|
|
|
|
|
{DVBT_IF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_IF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_RF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_RF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_POLAR_RF_AGC, 0x0},
|
|
|
|
|
{DVBT_POLAR_IF_AGC, 0x0},
|
|
|
|
|
{DVBT_AD7_SETTING, 0xe9d4},
|
|
|
|
|
{DVBT_EN_GI_PGA, 0x0},
|
|
|
|
|
{DVBT_THD_LOCK_UP, 0x0},
|
|
|
|
|
{DVBT_THD_LOCK_DW, 0x0},
|
|
|
|
|
{DVBT_THD_UP1, 0x14},
|
|
|
|
|
{DVBT_THD_DW1, 0xec},
|
|
|
|
|
{DVBT_INTER_CNT_LEN, 0xc},
|
|
|
|
|
{DVBT_GI_PGA_STATE, 0x0},
|
|
|
|
|
{DVBT_EN_AGC_PGA, 0x1},
|
|
|
|
|
{DVBT_REG_GPE, 0x1},
|
|
|
|
|
{DVBT_REG_GPO, 0x1},
|
|
|
|
|
{DVBT_REG_MONSEL, 0x1},
|
|
|
|
|
{DVBT_REG_MON, 0x1},
|
|
|
|
|
{DVBT_REG_4MSEL, 0x0},
|
2013-10-13 11:06:44 +08:00
|
|
|
{DVBT_SPEC_INV, 0x0},
|
2013-04-10 05:19:50 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
|
2013-10-13 11:06:44 +08:00
|
|
|
{DVBT_DAGC_TRG_VAL, 0x39},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_0, 0x0},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_8_1, 0x40},
|
|
|
|
|
{DVBT_AAGC_LOOP_GAIN, 0x16},
|
|
|
|
|
{DVBT_LOOP_GAIN2_3_0, 0x8},
|
|
|
|
|
{DVBT_LOOP_GAIN2_4, 0x1},
|
|
|
|
|
{DVBT_LOOP_GAIN3, 0x18},
|
|
|
|
|
{DVBT_VTOP1, 0x35},
|
|
|
|
|
{DVBT_VTOP2, 0x21},
|
|
|
|
|
{DVBT_VTOP3, 0x21},
|
|
|
|
|
{DVBT_KRF1, 0x0},
|
|
|
|
|
{DVBT_KRF2, 0x40},
|
|
|
|
|
{DVBT_KRF3, 0x10},
|
|
|
|
|
{DVBT_KRF4, 0x10},
|
|
|
|
|
{DVBT_IF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_IF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_RF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_RF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_POLAR_RF_AGC, 0x0},
|
|
|
|
|
{DVBT_POLAR_IF_AGC, 0x0},
|
|
|
|
|
{DVBT_AD7_SETTING, 0xe9f4},
|
|
|
|
|
{DVBT_SPEC_INV, 0x1},
|
2012-09-18 04:53:04 +08:00
|
|
|
};
|
|
|
|
|
|
2015-05-06 00:54:19 +08:00
|
|
|
static const struct rtl2832_reg_value rtl2832_tuner_init_si2157[] = {
|
|
|
|
|
{DVBT_DAGC_TRG_VAL, 0x39},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_0, 0x0},
|
|
|
|
|
{DVBT_AGC_TARG_VAL_8_1, 0x40},
|
|
|
|
|
{DVBT_AAGC_LOOP_GAIN, 0x16},
|
|
|
|
|
{DVBT_LOOP_GAIN2_3_0, 0x8},
|
|
|
|
|
{DVBT_LOOP_GAIN2_4, 0x1},
|
|
|
|
|
{DVBT_LOOP_GAIN3, 0x18},
|
|
|
|
|
{DVBT_VTOP1, 0x35},
|
|
|
|
|
{DVBT_VTOP2, 0x21},
|
|
|
|
|
{DVBT_VTOP3, 0x21},
|
|
|
|
|
{DVBT_KRF1, 0x0},
|
|
|
|
|
{DVBT_KRF2, 0x40},
|
|
|
|
|
{DVBT_KRF3, 0x10},
|
|
|
|
|
{DVBT_KRF4, 0x10},
|
|
|
|
|
{DVBT_IF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_IF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_RF_AGC_MIN, 0x80},
|
|
|
|
|
{DVBT_RF_AGC_MAX, 0x7f},
|
|
|
|
|
{DVBT_POLAR_RF_AGC, 0x0},
|
|
|
|
|
{DVBT_POLAR_IF_AGC, 0x0},
|
|
|
|
|
{DVBT_AD7_SETTING, 0xe9f4},
|
|
|
|
|
{DVBT_SPEC_INV, 0x0},
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-19 01:47:40 +08:00
|
|
|
#endif /* RTL2832_PRIV_H */
|
