2019-05-29 22:18:05 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-08-19 16:54:33 +08:00
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/*******************************************************************************
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EZNPS CPU startup Code
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Copyright(c) 2012 EZchip Technologies.
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*******************************************************************************/
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#include <linux/linkage.h>
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#include <asm/entry.h>
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#include <asm/cache.h>
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#include <plat/ctop.h>
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.cpu A7
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.section .init.text, "ax",@progbits
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.align 1024 ; HW requierment for restart first PC
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ENTRY(res_service)
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2017-06-15 16:43:58 +08:00
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#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS)
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2012-08-19 16:54:33 +08:00
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; There is no work for HW thread id != 0
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lr r3, [CTOP_AUX_THREAD_ID]
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cmp r3, 0
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jne stext
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#endif
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#ifdef CONFIG_ARC_HAS_DCACHE
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; With no cache coherency mechanism D$ need to be used very carefully.
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; Address space:
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; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES.
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; 2G-3G: We disable D$ by setting this bit.
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; 3G-4G: D$ is disabled by architecture.
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; FMT are huge pages for user application reside at 0-2G.
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; Only FMT left as one who can use D$ where each such page got
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; disable/enable bit for cachability.
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; Programmer will use FMT pages for private data so cache coherency
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; would not be a problem.
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; First thing we invalidate D$
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sr 1, [ARC_REG_DC_IVDC]
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sr HW_COMPLY_KRN_NOT_D_CACHED, [CTOP_AUX_HW_COMPLY]
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#endif
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#ifdef CONFIG_SMP
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; We set logical cpuid to be used by GET_CPUID
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; We do not use physical cpuid since we want ids to be continious when
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; it comes to cpus on the same quad cluster.
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; This is useful for applications that used shared resources of a quad
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; cluster such SRAMS.
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lr r3, [CTOP_AUX_CORE_ID]
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sr r3, [CTOP_AUX_LOGIC_CORE_ID]
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lr r3, [CTOP_AUX_CLUSTER_ID]
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; Set logical is acheived by swap of 2 middle bits of cluster id (4 bit)
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; r3 is used since we use short instruction and we need q-class reg
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.short CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST
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.word CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM
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sr r3, [CTOP_AUX_LOGIC_CLUSTER_ID]
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#endif
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j stext
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END(res_service)
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