2005-04-17 06:20:36 +08:00
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
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*/
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2006-01-02 17:14:23 +08:00
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/*
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2005-06-23 20:46:46 +08:00
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*
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2005-04-17 06:20:36 +08:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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2005-06-23 20:46:46 +08:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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2006-01-02 17:14:23 +08:00
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*/
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2005-04-17 06:20:36 +08:00
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#ifndef _I915_DRV_H_
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#define _I915_DRV_H_
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2012-12-04 05:03:14 +08:00
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#include <uapi/drm/i915_drm.h>
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2015-02-11 01:16:05 +08:00
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#include <uapi/drm/drm_fourcc.h>
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2012-12-04 05:03:14 +08:00
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2008-10-31 10:38:48 +08:00
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#include <linux/io-mapping.h>
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2010-07-21 06:44:45 +08:00
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#include <linux/i2c.h>
|
2012-02-28 07:43:09 +08:00
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#include <linux/i2c-algo-bit.h>
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2011-08-12 18:11:33 +08:00
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#include <linux/backlight.h>
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2017-06-16 22:05:16 +08:00
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#include <linux/hash.h>
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2012-04-06 05:47:36 +08:00
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#include <linux/intel-iommu.h>
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2012-04-27 21:17:39 +08:00
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#include <linux/kref.h>
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2018-06-07 05:45:20 +08:00
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#include <linux/mm_types.h>
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drm/i915/pmu: Expose a PMU interface for perf queries
From: Chris Wilson <chris@chris-wilson.co.uk>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
From: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system, but also
runs the risk of hanging the machine.) As an alternative we can use the
perf event counter interface to sample the ring registers periodically
and send those results to userspace.
Functionality we are exporting to userspace is via the existing perf PMU
API and can be exercised via the existing tools. For example:
perf stat -a -e i915/rcs0-busy/ -I 1000
Will print the render engine busynnes once per second. All the performance
counters can be enumerated (perf list) and have their unit of measure
correctly reported in sysfs.
v1-v2 (Chris Wilson):
v2: Use a common timer for the ring sampling.
v3: (Tvrtko Ursulin)
* Decouple uAPI from i915 engine ids.
* Complete uAPI defines.
* Refactor some code to helpers for clarity.
* Skip sampling disabled engines.
* Expose counters in sysfs.
* Pass in fake regs to avoid null ptr deref in perf core.
* Convert to class/instance uAPI.
* Use shared driver code for rc6 residency, power and frequency.
v4: (Dmitry Rogozhkin)
* Register PMU with .task_ctx_nr=perf_invalid_context
* Expose cpumask for the PMU with the single CPU in the mask
* Properly support pmu->stop(): it should call pmu->read()
* Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE)
* Introduce refcounting of event subscriptions.
* Make pmu.busy_stats a refcounter to avoid busy stats going away
with some deleted event.
* Expose cpumask for i915 PMU to avoid multiple events creation of
the same type followed by counter aggregation by perf-stat.
* Track CPUs getting online/offline to migrate perf context. If (likely)
cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be
needed to see effect of CPU status tracking.
* End result is that only global events are supported and perf stat
works correctly.
* Deny perf driver level sampling - it is prohibited for uncore PMU.
v5: (Tvrtko Ursulin)
* Don't hardcode number of engine samplers.
* Rewrite event ref-counting for correctness and simplicity.
* Store initial counter value when starting already enabled events
to correctly report values to all listeners.
* Fix RC6 residency readout.
* Comments, GPL header.
v6:
* Add missing entry to v4 changelog.
* Fix accounting in CPU hotplug case by copying the approach from
arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin)
v7:
* Log failure message only on failure.
* Remove CPU hotplug notification state on unregister.
v8:
* Fix error unwind on failed registration.
* Checkpatch cleanup.
v9:
* Drop the energy metric, it is available via intel_rapl_perf.
(Ville Syrjälä)
* Use HAS_RC6(p). (Chris Wilson)
* Handle unsupported non-engine events. (Dmitry Rogozhkin)
* Rebase for intel_rc6_residency_ns needing caller managed
runtime pm.
* Drop HAS_RC6 checks from the read callback since creating those
events will be rejected at init time already.
* Add counter units to sysfs so perf stat output is nicer.
* Cleanup the attribute tables for brevity and readability.
v10:
* Fixed queued accounting.
v11:
* Move intel_engine_lookup_user to intel_engine_cs.c
* Commit update. (Joonas Lahtinen)
v12:
* More accurate sampling. (Chris Wilson)
* Store and report frequency in MHz for better usability from
perf stat.
* Removed metrics: queued, interrupts, rc6 counters.
* Sample engine busyness based on seqno difference only
for less MMIO (and forcewake) on all platforms. (Chris Wilson)
v13:
* Comment spelling, use mul_u32_u32 to work around potential GCC
issue and somne code alignment changes. (Chris Wilson)
v14:
* Rebase.
v15:
* Rebase for RPS refactoring.
v16:
* Use the dynamic slot in the CPU hotplug state machine so that we are
free to setup our state as multi-instance. Previously we were re-using
the CPUHP_AP_PERF_X86_UNCORE_ONLINE slot which is neither used as
multi-instance, nor owned by our driver to start with.
* Register the CPU hotplug handlers after the PMU, otherwise the callback
will get called before the PMU is initialized which can end up in
perf_pmu_migrate_context with an un-initialized base.
* Added workaround for a probable bug in cpuhp core.
v17:
* Remove workaround for the cpuhp bug.
v18:
* Rebase for drm_i915_gem_engine_class getting upstream before us.
v19:
* Rebase. (trivial)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-2-tvrtko.ursulin@linux.intel.com
2017-11-22 02:18:45 +08:00
|
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#include <linux/perf_event.h>
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
#include <linux/pm_qos.h>
|
drm/i915: Move GEM activity tracking into a common struct reservation_object
In preparation to support many distinct timelines, we need to expand the
activity tracking on the GEM object to handle more than just a request
per engine. We already use the struct reservation_object on the dma-buf
to handle many fence contexts, so integrating that into the GEM object
itself is the preferred solution. (For example, we can now share the same
reservation_object between every consumer/producer using this buffer and
skip the manual import/export via dma-buf.)
v2: Reimplement busy-ioctl (by walking the reservation object), postpone
the ABI change for another day. Similarly use the reservation object to
find the last_write request (if active and from i915) for choosing
display CS flips.
Caveats:
* busy-ioctl: busy-ioctl only reports on the native fences, it will not
warn of stalls (in set-domain-ioctl, pread/pwrite etc) if the object is
being rendered to by external fences. It also will not report the same
busy state as wait-ioctl (or polling on the dma-buf) in the same
circumstances. On the plus side, it does retain reporting of which
*i915* engines are engaged with this object.
* non-blocking atomic modesets take a step backwards as the wait for
render completion blocks the ioctl. This is fixed in a subsequent
patch to use a fence instead for awaiting on the rendering, see
"drm/i915: Restore nonblocking awaits for modesetting"
* dynamic array manipulation for shared-fences in reservation is slower
than the previous lockless static assignment (e.g. gem_exec_lut_handle
runtime on ivb goes from 42s to 66s), mainly due to atomic operations
(maintaining the fence refcounts).
* loss of object-level retirement callbacks, emulated by VMA retirement
tracking.
* minor loss of object-level last activity information from debugfs,
could be replaced with per-vma information if desired
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-21-chris@chris-wilson.co.uk
2016-10-28 20:58:44 +08:00
|
|
|
#include <linux/reservation.h>
|
2016-04-14 00:35:01 +08:00
|
|
|
#include <linux/shmem_fs.h>
|
2019-01-14 22:21:09 +08:00
|
|
|
#include <linux/stackdepot.h>
|
2016-04-14 00:35:01 +08:00
|
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|
|
#include <drm/intel-gtt.h>
|
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|
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
|
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|
|
#include <drm/drm_gem.h>
|
2016-06-21 16:54:22 +08:00
|
|
|
#include <drm/drm_auth.h>
|
2017-01-10 05:56:49 +08:00
|
|
|
#include <drm/drm_cache.h>
|
2018-09-05 21:57:05 +08:00
|
|
|
#include <drm/drm_util.h>
|
2018-11-29 04:26:12 +08:00
|
|
|
#include <drm/drm_dsc.h>
|
2019-05-24 23:36:14 +08:00
|
|
|
#include <drm/drm_atomic.h>
|
2019-01-08 16:27:09 +08:00
|
|
|
#include <drm/drm_connector.h>
|
2019-02-17 01:36:51 +08:00
|
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|
#include <drm/i915_mei_hdcp_interface.h>
|
2016-04-14 00:35:01 +08:00
|
|
|
|
2018-11-16 20:07:25 +08:00
|
|
|
#include "i915_fixed.h"
|
2016-04-14 00:35:01 +08:00
|
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|
#include "i915_params.h"
|
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|
|
#include "i915_reg.h"
|
2017-01-05 23:30:22 +08:00
|
|
|
#include "i915_utils.h"
|
2016-04-14 00:35:01 +08:00
|
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|
|
2019-06-13 16:44:16 +08:00
|
|
|
#include "display/intel_bios.h"
|
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|
|
#include "display/intel_display.h"
|
|
|
|
#include "display/intel_display_power.h"
|
|
|
|
#include "display/intel_dpll_mgr.h"
|
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|
|
#include "display/intel_frontbuffer.h"
|
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|
|
#include "display/intel_opregion.h"
|
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|
|
|
2019-08-08 21:42:48 +08:00
|
|
|
#include "gem/i915_gem_context_types.h"
|
2019-08-08 21:42:49 +08:00
|
|
|
#include "gem/i915_gem_shrinker.h"
|
2019-08-08 21:42:48 +08:00
|
|
|
#include "gem/i915_gem_stolen.h"
|
|
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|
|
2019-04-25 01:48:39 +08:00
|
|
|
#include "gt/intel_lrc.h"
|
|
|
|
#include "gt/intel_engine.h"
|
2019-06-21 15:07:40 +08:00
|
|
|
#include "gt/intel_gt_types.h"
|
2019-04-25 01:48:39 +08:00
|
|
|
#include "gt/intel_workarounds.h"
|
2019-07-13 18:00:11 +08:00
|
|
|
#include "gt/uc/intel_uc.h"
|
2019-04-25 01:48:39 +08:00
|
|
|
|
2017-12-22 05:57:32 +08:00
|
|
|
#include "intel_device_info.h"
|
2019-08-07 20:04:15 +08:00
|
|
|
#include "intel_pch.h"
|
2019-04-29 20:29:36 +08:00
|
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|
#include "intel_runtime_pm.h"
|
2017-12-22 05:57:31 +08:00
|
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|
#include "intel_uncore.h"
|
2019-04-25 04:07:13 +08:00
|
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|
#include "intel_wakeref.h"
|
2018-03-14 08:32:50 +08:00
|
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|
#include "intel_wopcm.h"
|
2016-04-14 00:35:01 +08:00
|
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|
|
2016-04-14 00:35:02 +08:00
|
|
|
#include "i915_gem.h"
|
2016-11-11 18:43:54 +08:00
|
|
|
#include "i915_gem_fence_reg.h"
|
2016-04-14 00:35:01 +08:00
|
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|
#include "i915_gem_gtt.h"
|
2018-03-08 17:50:37 +08:00
|
|
|
#include "i915_gpu_error.h"
|
2018-02-21 17:56:36 +08:00
|
|
|
#include "i915_request.h"
|
2018-04-19 02:40:52 +08:00
|
|
|
#include "i915_scheduler.h"
|
2019-06-21 15:08:10 +08:00
|
|
|
#include "gt/intel_timeline.h"
|
2016-11-11 18:43:54 +08:00
|
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#include "i915_vma.h"
|
2019-08-06 18:07:28 +08:00
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#include "i915_irq.h"
|
2016-11-11 18:43:54 +08:00
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|
drm/i915: gvt: Introduce the basic architecture of GVT-g
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v12:
- Call intel_gvt_init() in driver early initialization stage. (Chris)
v8:
- Remove the GVT idr and mutex in intel_gvt_host. (Joonas)
v7:
- Refine the URL link in Kconfig. (Joonas)
- Refine the introduction of GVT-g host support in Kconfig. (Joonas)
- Remove the macro GVT_ALIGN(), use round_down() instead. (Joonas)
- Make "struct intel_gvt" a data member in struct drm_i915_private.(Joonas)
- Remove {alloc, free}_gvt_device()
- Rename intel_gvt_{create, destroy}_gvt_device()
- Expost intel_gvt_init_host()
- Remove the dummy "struct intel_gvt" declaration in intel_gvt.h (Joonas)
v6:
- Refine introduction in Kconfig. (Chris)
- The exposed API functions will take struct intel_gvt * instead of
void *. (Chris/Tvrtko)
- Remove most memebers of strct intel_gvt_device_info. Will add them
in the device model patches.(Chris)
- Remove gvt_info() and gvt_err() in debug.h. (Chris)
- Move GVT kernel parameter into i915_params. (Chris)
- Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
- Remove the redundant struct i915_gvt *, as the functions in i915
will directly take struct intel_gvt *.
- Add more comments for reviewer.
v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfig
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization
v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.
Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.
Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-5-git-send-email-zhi.a.wang@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-16 20:07:00 +08:00
|
|
|
#include "intel_gvt.h"
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* General customization:
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define DRIVER_NAME "i915"
|
|
|
|
#define DRIVER_DESC "Intel Graphics"
|
2019-08-14 14:59:53 +08:00
|
|
|
#define DRIVER_DATE "20190813"
|
|
|
|
#define DRIVER_TIMESTAMP 1565765993
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2019-05-28 17:29:42 +08:00
|
|
|
struct drm_i915_gem_object;
|
|
|
|
|
2013-02-26 01:06:49 +08:00
|
|
|
enum hpd_pin {
|
|
|
|
HPD_NONE = 0,
|
|
|
|
HPD_TV = HPD_NONE, /* TV is known to be unreliable */
|
|
|
|
HPD_CRT,
|
|
|
|
HPD_SDVO_B,
|
|
|
|
HPD_SDVO_C,
|
2015-07-22 06:32:45 +08:00
|
|
|
HPD_PORT_A,
|
2013-02-26 01:06:49 +08:00
|
|
|
HPD_PORT_B,
|
|
|
|
HPD_PORT_C,
|
|
|
|
HPD_PORT_D,
|
2015-08-17 15:55:50 +08:00
|
|
|
HPD_PORT_E,
|
2018-03-24 01:24:17 +08:00
|
|
|
HPD_PORT_F,
|
2019-07-26 07:48:11 +08:00
|
|
|
HPD_PORT_G,
|
|
|
|
HPD_PORT_H,
|
|
|
|
HPD_PORT_I,
|
|
|
|
|
2013-02-26 01:06:49 +08:00
|
|
|
HPD_NUM_PINS
|
|
|
|
};
|
|
|
|
|
2015-05-28 20:43:48 +08:00
|
|
|
#define for_each_hpd_pin(__pin) \
|
|
|
|
for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
|
|
|
|
|
drm/i915: Add short HPD IRQ storm detection for non-MST systems
Unfortunately, it seems that the HPD IRQ storm problem from the early
days of Intel GPUs was never entirely solved, only mostly. Within the
last couple of days, I got a bug report from one of our customers who
had been having issues with their machine suddenly booting up very
slowly after having updated. The amount of time it took to boot went
from around 30 seconds, to over 6 minutes consistently.
After some investigation, I discovered that i915 was reporting massive
amounts of short HPD IRQ spam on this system from the DisplayPort port,
despite there not being anything actually connected. The symptoms would
start with one "long" HPD IRQ being detected at boot:
[ 1.891398] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00440000, dig 0x00440000, pins 0x000000a0
[ 1.891436] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long
[ 1.891472] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 5 - cnt: 0
[ 1.891508] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - long
[ 1.891544] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 7 - cnt: 0
[ 1.891592] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long
[ 1.891628] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port D - long
…
followed by constant short IRQs afterwards:
[ 1.895091] [drm:intel_encoder_hotplug [i915]] [CONNECTOR:66:DP-1] status updated from unknown to disconnected
[ 1.895129] [drm:i915_hotplug_work_func [i915]] Connector DP-3 (pin 7) received hotplug event.
[ 1.895165] [drm:intel_dp_detect [i915]] [CONNECTOR:72:DP-3]
[ 1.895275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.895312] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.895762] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.895799] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.896239] [drm:intel_dp_aux_xfer [i915]] dp_aux_ch timeout status 0x71450085
[ 1.896293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.896330] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.896781] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.896817] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.897275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
The customer's system in question has a GM45 GPU, which is apparently
well known for hotplugging storms.
So, workaround this impressively broken hardware by changing the default
HPD storm threshold from 5 to 50. Then, make long IRQs count for 10, and
short IRQs count for 1. This makes it so that 5 long IRQs will trigger
an HPD storm, and on systems with short HPD storm detection 50 short
IRQs will trigger an HPD storm. 50 short IRQs amounts to 100ms of
constant pulsing, which seems like a good middleground between being too
sensitive and not being sensitive enough (which would cause visible
stutters in userspace every time a storm occurs).
And just to be extra safe: we don't enable this by default on systems
with MST support. There's too high of a chance of MST support triggering
storm detection, and systems that are new enough to support MST are a
lot less likely to have issues with IRQ storms anyway.
As a note: this patch was tested using a ThinkPad T450s and a Chamelium
to simulate the short IRQ storms.
Changes since v1:
- Don't use two separate thresholds, just make long IRQs count for 10
each and short IRQs count for 1. This simplifies the code a bit
- Ville Syrjälä
Changes since v2:
- Document @long_hpd in intel_hpd_irq_storm_detect, no functional
changes
Changes since v4:
- Remove !! in long_hpd assignment - Ville Syrjälä
- queue_hp = true - Ville Syrjälä
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181106213017.14563-6-lyude@redhat.com
2018-11-07 05:30:16 +08:00
|
|
|
/* Threshold == 5 for long IRQs, 50 for short */
|
|
|
|
#define HPD_STORM_DEFAULT_THRESHOLD 50
|
2017-02-04 10:18:25 +08:00
|
|
|
|
2015-05-27 20:03:42 +08:00
|
|
|
struct i915_hotplug {
|
2019-07-12 08:53:42 +08:00
|
|
|
struct delayed_work hotplug_work;
|
2015-05-27 20:03:42 +08:00
|
|
|
|
|
|
|
struct {
|
|
|
|
unsigned long last_jiffies;
|
|
|
|
int count;
|
|
|
|
enum {
|
|
|
|
HPD_ENABLED = 0,
|
|
|
|
HPD_DISABLED = 1,
|
|
|
|
HPD_MARK_DISABLED = 2
|
|
|
|
} state;
|
|
|
|
} stats[HPD_NUM_PINS];
|
|
|
|
u32 event_bits;
|
2019-07-12 08:53:42 +08:00
|
|
|
u32 retry_bits;
|
2015-05-27 20:03:42 +08:00
|
|
|
struct delayed_work reenable_work;
|
|
|
|
|
|
|
|
u32 long_port_mask;
|
|
|
|
u32 short_port_mask;
|
|
|
|
struct work_struct dig_port_work;
|
|
|
|
|
2016-06-22 05:03:44 +08:00
|
|
|
struct work_struct poll_init_work;
|
|
|
|
bool poll_enabled;
|
|
|
|
|
2017-02-04 10:18:25 +08:00
|
|
|
unsigned int hpd_storm_threshold;
|
drm/i915: Add short HPD IRQ storm detection for non-MST systems
Unfortunately, it seems that the HPD IRQ storm problem from the early
days of Intel GPUs was never entirely solved, only mostly. Within the
last couple of days, I got a bug report from one of our customers who
had been having issues with their machine suddenly booting up very
slowly after having updated. The amount of time it took to boot went
from around 30 seconds, to over 6 minutes consistently.
After some investigation, I discovered that i915 was reporting massive
amounts of short HPD IRQ spam on this system from the DisplayPort port,
despite there not being anything actually connected. The symptoms would
start with one "long" HPD IRQ being detected at boot:
[ 1.891398] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00440000, dig 0x00440000, pins 0x000000a0
[ 1.891436] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long
[ 1.891472] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 5 - cnt: 0
[ 1.891508] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - long
[ 1.891544] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 7 - cnt: 0
[ 1.891592] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long
[ 1.891628] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port D - long
…
followed by constant short IRQs afterwards:
[ 1.895091] [drm:intel_encoder_hotplug [i915]] [CONNECTOR:66:DP-1] status updated from unknown to disconnected
[ 1.895129] [drm:i915_hotplug_work_func [i915]] Connector DP-3 (pin 7) received hotplug event.
[ 1.895165] [drm:intel_dp_detect [i915]] [CONNECTOR:72:DP-3]
[ 1.895275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.895312] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.895762] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.895799] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.896239] [drm:intel_dp_aux_xfer [i915]] dp_aux_ch timeout status 0x71450085
[ 1.896293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.896330] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.896781] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
[ 1.896817] [drm:intel_hpd_irq_handler [i915]] digital hpd port D - short
[ 1.897275] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x00200000, pins 0x00000080
The customer's system in question has a GM45 GPU, which is apparently
well known for hotplugging storms.
So, workaround this impressively broken hardware by changing the default
HPD storm threshold from 5 to 50. Then, make long IRQs count for 10, and
short IRQs count for 1. This makes it so that 5 long IRQs will trigger
an HPD storm, and on systems with short HPD storm detection 50 short
IRQs will trigger an HPD storm. 50 short IRQs amounts to 100ms of
constant pulsing, which seems like a good middleground between being too
sensitive and not being sensitive enough (which would cause visible
stutters in userspace every time a storm occurs).
And just to be extra safe: we don't enable this by default on systems
with MST support. There's too high of a chance of MST support triggering
storm detection, and systems that are new enough to support MST are a
lot less likely to have issues with IRQ storms anyway.
As a note: this patch was tested using a ThinkPad T450s and a Chamelium
to simulate the short IRQ storms.
Changes since v1:
- Don't use two separate thresholds, just make long IRQs count for 10
each and short IRQs count for 1. This simplifies the code a bit
- Ville Syrjälä
Changes since v2:
- Document @long_hpd in intel_hpd_irq_storm_detect, no functional
changes
Changes since v4:
- Remove !! in long_hpd assignment - Ville Syrjälä
- queue_hp = true - Ville Syrjälä
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181106213017.14563-6-lyude@redhat.com
2018-11-07 05:30:16 +08:00
|
|
|
/* Whether or not to count short HPD IRQs in HPD storms */
|
|
|
|
u8 hpd_short_storm_enabled;
|
2017-02-04 10:18:25 +08:00
|
|
|
|
2015-05-27 20:03:42 +08:00
|
|
|
/*
|
|
|
|
* if we get a HPD irq from DP and a HPD irq from non-DP
|
|
|
|
* the non-DP HPD could block the workqueue on a mode config
|
|
|
|
* mutex getting, that userspace may have taken. However
|
|
|
|
* userspace is waiting on the DP workqueue to run which is
|
|
|
|
* blocked behind the non-DP one.
|
|
|
|
*/
|
|
|
|
struct workqueue_struct *dp_wq;
|
|
|
|
};
|
|
|
|
|
2012-12-03 19:49:06 +08:00
|
|
|
#define I915_GEM_GPU_DOMAINS \
|
|
|
|
(I915_GEM_DOMAIN_RENDER | \
|
|
|
|
I915_GEM_DOMAIN_SAMPLER | \
|
|
|
|
I915_GEM_DOMAIN_COMMAND | \
|
|
|
|
I915_GEM_DOMAIN_INSTRUCTION | \
|
|
|
|
I915_GEM_DOMAIN_VERTEX)
|
2010-05-22 04:26:39 +08:00
|
|
|
|
2013-06-05 19:34:14 +08:00
|
|
|
struct drm_i915_private;
|
2014-08-07 21:20:40 +08:00
|
|
|
struct i915_mm_struct;
|
drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This has
a number of uses, with zero-copy downloads to the GPU and efficient
readback making the intermixed streaming of CPU and GPU operations
fairly efficient. This ability has many widespread implications from
faster rendering of client-side software rasterisers (chromium),
mitigation of stalls due to read back (firefox) and to faster pipelining
of texture data (such as pixel buffer objects in GL or data blobs in CL).
v2: Compile with CONFIG_MMU_NOTIFIER
v3: We can sleep while performing invalidate-range, which we can utilise
to drop our page references prior to the kernel manipulating the vma
(for either discard or cloning) and so protect normal users.
v4: Only run the invalidate notifier if the range intercepts the bo.
v5: Prevent userspace from attempting to GTT mmap non-page aligned buffers
v6: Recheck after reacquire mutex for lost mmu.
v7: Fix implicit padding of ioctl struct by rounding to next 64bit boundary.
v8: Fix rebasing error after forwarding porting the back port.
v9: Limit the userptr to page aligned entries. We now expect userspace
to handle all the offset-in-page adjustments itself.
v10: Prevent vma from being copied across fork to avoid issues with cow.
v11: Drop vma behaviour changes -- locking is nigh on impossible.
Use a worker to load user pages to avoid lock inversions.
v12: Use get_task_mm()/mmput() for correct refcounting of mm.
v13: Use a worker to release the mmu_notifier to avoid lock inversion
v14: Decouple mmu_notifier from struct_mutex using a custom mmu_notifer
with its own locking and tree of objects for each mm/mmu_notifier.
v15: Prevent overlapping userptr objects, and invalidate all objects
within the mmu_notifier range
v16: Fix a typo for iterating over multiple objects in the range and
rearrange error path to destroy the mmu_notifier locklessly.
Also close a race between invalidate_range and the get_pages_worker.
v17: Close a race between get_pages_worker/invalidate_range and fresh
allocations of the same userptr range - and notice that
struct_mutex was presumed to be held when during creation it wasn't.
v18: Sigh. Fix the refactor of st_set_pages() to allocate enough memory
for the struct sg_table and to clear it before reporting an error.
v19: Always error out on read-only userptr requests as we don't have the
hardware infrastructure to support them at the moment.
v20: Refuse to implement read-only support until we have the required
infrastructure - but reserve the bit in flags for future use.
v21: use_mm() is not required for get_user_pages(). It is only meant to
be used to fix up the kernel thread's current->mm for use with
copy_user().
v22: Use sg_alloc_table_from_pages for that chunky feeling
v23: Export a function for sanity checking dma-buf rather than encode
userptr details elsewhere, and clean up comments based on
suggestions by Bradley.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: "Gong, Zhipeng" <zhipeng.gong@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Cc: "Volkin, Bradley D" <bradley.d.volkin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com>
[danvet: Frob ioctl allocation to pick the next one - will cause a bit
of fuss with create2 apparently, but such are the rules.]
[danvet2: oops, forgot to git add after manual patch application]
[danvet3: Appease sparse.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-05-16 21:22:37 +08:00
|
|
|
struct i915_mmu_object;
|
2013-06-05 19:34:14 +08:00
|
|
|
|
2015-04-27 20:41:20 +08:00
|
|
|
struct drm_i915_file_private {
|
|
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
struct drm_file *file;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
spinlock_t lock;
|
|
|
|
struct list_head request_list;
|
|
|
|
} mm;
|
2019-03-21 22:07:09 +08:00
|
|
|
|
2015-04-27 20:41:20 +08:00
|
|
|
struct idr context_idr;
|
2019-03-21 22:07:09 +08:00
|
|
|
struct mutex context_idr_lock; /* guards context_idr */
|
2015-04-27 20:41:20 +08:00
|
|
|
|
2019-03-22 17:23:23 +08:00
|
|
|
struct idr vm_idr;
|
|
|
|
struct mutex vm_idr_lock; /* guards vm_idr */
|
|
|
|
|
2016-07-27 16:07:27 +08:00
|
|
|
unsigned int bsd_engine;
|
2016-11-18 21:10:47 +08:00
|
|
|
|
2018-06-15 18:44:29 +08:00
|
|
|
/*
|
|
|
|
* Every context ban increments per client ban score. Also
|
|
|
|
* hangs in short succession increments ban score. If ban threshold
|
|
|
|
* is reached, client is considered banned and submitting more work
|
|
|
|
* will fail. This is a stop gap measure to limit the badly behaving
|
|
|
|
* clients access to gpu. Note that unbannable contexts never increment
|
|
|
|
* the client ban score.
|
2016-11-18 21:10:47 +08:00
|
|
|
*/
|
2018-06-15 18:44:29 +08:00
|
|
|
#define I915_CLIENT_SCORE_HANG_FAST 1
|
|
|
|
#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
|
|
|
|
#define I915_CLIENT_SCORE_CONTEXT_BAN 3
|
|
|
|
#define I915_CLIENT_SCORE_BANNED 9
|
|
|
|
/** ban_score: Accumulated score of all ctx bans and fast hangs. */
|
|
|
|
atomic_t ban_score;
|
|
|
|
unsigned long hang_timestamp;
|
2015-04-27 20:41:20 +08:00
|
|
|
};
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* Interface history:
|
|
|
|
*
|
|
|
|
* 1.1: Original.
|
2006-01-02 17:14:23 +08:00
|
|
|
* 1.2: Add Power Management
|
|
|
|
* 1.3: Add vblank support
|
2006-01-25 12:31:43 +08:00
|
|
|
* 1.4: Fix cmdbuffer path, add heap destroy
|
2006-06-24 15:07:34 +08:00
|
|
|
* 1.5: Add vblank pipe configuration
|
2006-10-24 23:05:09 +08:00
|
|
|
* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
|
|
|
|
* - Support vertical blank on secondary display pipe
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
#define DRIVER_MAJOR 1
|
2006-10-24 23:05:09 +08:00
|
|
|
#define DRIVER_MINOR 6
|
2005-04-17 06:20:36 +08:00
|
|
|
#define DRIVER_PATCHLEVEL 0
|
|
|
|
|
2010-08-05 03:26:07 +08:00
|
|
|
struct intel_overlay;
|
|
|
|
struct intel_overlay_error_state;
|
|
|
|
|
2009-05-31 17:17:17 +08:00
|
|
|
struct sdvo_device_mapping {
|
2010-09-24 19:52:03 +08:00
|
|
|
u8 initialized;
|
2009-05-31 17:17:17 +08:00
|
|
|
u8 dvo_port;
|
|
|
|
u8 slave_addr;
|
|
|
|
u8 dvo_wiring;
|
2010-09-24 19:52:03 +08:00
|
|
|
u8 i2c_pin;
|
2010-04-24 04:07:40 +08:00
|
|
|
u8 ddc_pin;
|
2009-05-31 17:17:17 +08:00
|
|
|
};
|
|
|
|
|
2013-11-08 22:48:56 +08:00
|
|
|
struct intel_connector;
|
2014-10-27 22:26:47 +08:00
|
|
|
struct intel_encoder;
|
2016-11-08 20:55:32 +08:00
|
|
|
struct intel_atomic_state;
|
2015-01-15 20:55:21 +08:00
|
|
|
struct intel_crtc_state;
|
2015-01-20 20:51:52 +08:00
|
|
|
struct intel_initial_plane_config;
|
2013-03-28 17:42:00 +08:00
|
|
|
struct intel_crtc;
|
2013-06-04 04:40:22 +08:00
|
|
|
struct intel_limit;
|
|
|
|
struct dpll;
|
2017-02-08 02:33:45 +08:00
|
|
|
struct intel_cdclk_state;
|
2013-03-27 07:44:50 +08:00
|
|
|
|
2009-09-22 01:42:27 +08:00
|
|
|
struct drm_i915_display_funcs {
|
2017-02-08 02:33:45 +08:00
|
|
|
void (*get_cdclk)(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_cdclk_state *cdclk_state);
|
2017-01-27 03:52:01 +08:00
|
|
|
void (*set_cdclk)(struct drm_i915_private *dev_priv,
|
2019-03-27 18:13:21 +08:00
|
|
|
const struct intel_cdclk_state *cdclk_state,
|
|
|
|
enum pipe pipe);
|
2017-11-18 03:19:11 +08:00
|
|
|
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
|
|
|
|
enum i9xx_plane_id i9xx_plane);
|
2019-06-28 16:55:17 +08:00
|
|
|
int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
|
|
|
|
int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
|
2016-11-08 20:55:32 +08:00
|
|
|
void (*initial_watermarks)(struct intel_atomic_state *state,
|
2019-06-28 16:55:17 +08:00
|
|
|
struct intel_crtc_state *crtc_state);
|
2016-11-08 20:55:32 +08:00
|
|
|
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
|
2019-06-28 16:55:17 +08:00
|
|
|
struct intel_crtc_state *crtc_state);
|
2016-11-08 20:55:32 +08:00
|
|
|
void (*optimize_watermarks)(struct intel_atomic_state *state,
|
2019-06-28 16:55:17 +08:00
|
|
|
struct intel_crtc_state *crtc_state);
|
2018-12-11 05:54:14 +08:00
|
|
|
int (*compute_global_watermarks)(struct intel_atomic_state *state);
|
2016-11-01 04:37:03 +08:00
|
|
|
void (*update_wm)(struct intel_crtc *crtc);
|
2019-05-18 03:31:19 +08:00
|
|
|
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
|
2013-03-28 17:42:00 +08:00
|
|
|
/* Returns the active state of the crtc, and if the crtc is active,
|
|
|
|
* fills out the pipe-config with the hw state. */
|
|
|
|
bool (*get_pipe_config)(struct intel_crtc *,
|
2015-01-15 20:55:21 +08:00
|
|
|
struct intel_crtc_state *);
|
2015-01-20 20:51:52 +08:00
|
|
|
void (*get_initial_plane_config)(struct intel_crtc *,
|
|
|
|
struct intel_initial_plane_config *);
|
2015-01-15 20:55:23 +08:00
|
|
|
int (*crtc_compute_clock)(struct intel_crtc *crtc,
|
|
|
|
struct intel_crtc_state *crtc_state);
|
2016-08-09 23:04:01 +08:00
|
|
|
void (*crtc_enable)(struct intel_crtc_state *pipe_config,
|
2019-06-28 16:55:13 +08:00
|
|
|
struct intel_atomic_state *old_state);
|
2016-08-09 23:04:01 +08:00
|
|
|
void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
|
2019-06-28 16:55:13 +08:00
|
|
|
struct intel_atomic_state *old_state);
|
|
|
|
void (*update_crtcs)(struct intel_atomic_state *state);
|
2017-10-31 02:46:53 +08:00
|
|
|
void (*audio_codec_enable)(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state);
|
|
|
|
void (*audio_codec_disable)(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state);
|
2017-03-02 20:58:54 +08:00
|
|
|
void (*fdi_link_train)(struct intel_crtc *crtc,
|
|
|
|
const struct intel_crtc_state *crtc_state);
|
2016-11-01 04:37:22 +08:00
|
|
|
void (*init_clock_gating)(struct drm_i915_private *dev_priv);
|
2016-05-06 21:48:28 +08:00
|
|
|
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
|
2009-09-22 01:42:27 +08:00
|
|
|
/* clock updates for mode set */
|
|
|
|
/* cursor updates */
|
|
|
|
/* render clock increase/decrease */
|
|
|
|
/* display clock increase/decrease */
|
|
|
|
/* pll clock increase/decrease */
|
2016-03-16 18:57:14 +08:00
|
|
|
|
2019-03-27 23:50:37 +08:00
|
|
|
int (*color_check)(struct intel_crtc_state *crtc_state);
|
2019-02-06 00:08:40 +08:00
|
|
|
/*
|
|
|
|
* Program double buffered color management registers during
|
|
|
|
* vblank evasion. The registers should then latch during the
|
|
|
|
* next vblank start, alongside any other double buffered registers
|
|
|
|
* involved with the same commit.
|
|
|
|
*/
|
|
|
|
void (*color_commit)(const struct intel_crtc_state *crtc_state);
|
|
|
|
/*
|
|
|
|
* Load LUTs (and other single buffered color management
|
|
|
|
* registers). Will (hopefully) be called during the vblank
|
|
|
|
* following the latching of any double buffered registers
|
|
|
|
* involved with the same commit.
|
|
|
|
*/
|
2019-02-06 00:08:38 +08:00
|
|
|
void (*load_luts)(const struct intel_crtc_state *crtc_state);
|
2019-05-29 17:50:51 +08:00
|
|
|
void (*read_luts)(struct intel_crtc_state *crtc_state);
|
2009-09-22 01:42:27 +08:00
|
|
|
};
|
|
|
|
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 20:58:44 +08:00
|
|
|
struct intel_csr {
|
2015-10-29 05:59:04 +08:00
|
|
|
struct work_struct work;
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 20:58:44 +08:00
|
|
|
const char *fw_path;
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 required_version;
|
|
|
|
u32 max_fw_size; /* bytes */
|
|
|
|
u32 *dmc_payload;
|
|
|
|
u32 dmc_fw_size; /* dwords */
|
|
|
|
u32 version;
|
|
|
|
u32 mmio_count;
|
2019-06-07 17:12:28 +08:00
|
|
|
i915_reg_t mmioaddr[20];
|
|
|
|
u32 mmiodata[20];
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 dc_state;
|
|
|
|
u32 allowed_dc_mask;
|
2019-01-14 22:21:24 +08:00
|
|
|
intel_wakeref_t wakeref;
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 20:58:44 +08:00
|
|
|
};
|
|
|
|
|
2013-01-25 06:44:55 +08:00
|
|
|
enum i915_cache_level {
|
|
|
|
I915_CACHE_NONE = 0,
|
2013-08-06 20:17:02 +08:00
|
|
|
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
|
|
|
|
I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
|
|
|
|
caches, eg sampler/render caches, and the
|
|
|
|
large Last-Level-Cache. LLC is coherent with
|
|
|
|
the CPU, but L3 is only visible to the GPU. */
|
2013-08-08 21:41:10 +08:00
|
|
|
I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
|
2013-01-25 06:44:55 +08:00
|
|
|
};
|
|
|
|
|
2016-12-05 22:29:36 +08:00
|
|
|
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
|
|
|
|
|
2016-01-12 03:44:36 +08:00
|
|
|
struct intel_fbc {
|
2015-07-03 06:25:10 +08:00
|
|
|
/* This is always the inner lock when overlapping with struct_mutex and
|
|
|
|
* it's the outer lock when overlapping with stolen_lock. */
|
|
|
|
struct mutex lock;
|
2014-07-01 01:41:24 +08:00
|
|
|
unsigned threshold;
|
2015-02-14 03:23:46 +08:00
|
|
|
unsigned int possible_framebuffer_bits;
|
|
|
|
unsigned int busy_bits;
|
2016-01-19 21:35:48 +08:00
|
|
|
unsigned int visible_pipes_mask;
|
2015-02-10 00:46:29 +08:00
|
|
|
struct intel_crtc *crtc;
|
2013-06-28 07:30:21 +08:00
|
|
|
|
2014-06-20 03:06:10 +08:00
|
|
|
struct drm_mm_node compressed_fb;
|
2013-06-28 07:30:21 +08:00
|
|
|
struct drm_mm_node *compressed_llb;
|
|
|
|
|
2014-08-01 17:04:45 +08:00
|
|
|
bool false_color;
|
|
|
|
|
2015-10-15 21:44:46 +08:00
|
|
|
bool enabled;
|
2015-10-15 04:45:36 +08:00
|
|
|
bool active;
|
2018-06-26 00:37:57 +08:00
|
|
|
bool flip_pending;
|
2014-09-20 03:04:55 +08:00
|
|
|
|
2016-09-13 21:38:57 +08:00
|
|
|
bool underrun_detected;
|
|
|
|
struct work_struct underrun_work;
|
|
|
|
|
2017-07-15 03:38:22 +08:00
|
|
|
/*
|
|
|
|
* Due to the atomic rules we can't access some structures without the
|
|
|
|
* appropriate locking, so we cache information here in order to avoid
|
|
|
|
* these problems.
|
|
|
|
*/
|
2016-01-19 21:35:42 +08:00
|
|
|
struct intel_fbc_state_cache {
|
2017-01-16 23:21:27 +08:00
|
|
|
struct i915_vma *vma;
|
2018-02-20 21:42:08 +08:00
|
|
|
unsigned long flags;
|
2017-01-16 23:21:27 +08:00
|
|
|
|
2016-01-19 21:35:42 +08:00
|
|
|
struct {
|
|
|
|
unsigned int mode_flags;
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 hsw_bdw_pixel_rate;
|
2016-01-19 21:35:42 +08:00
|
|
|
} crtc;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
unsigned int rotation;
|
|
|
|
int src_w;
|
|
|
|
int src_h;
|
|
|
|
bool visible;
|
2017-10-18 04:08:07 +08:00
|
|
|
/*
|
|
|
|
* Display surface base address adjustement for
|
|
|
|
* pageflips. Note that on gen4+ this only adjusts up
|
|
|
|
* to a tile, offsets within a tile are handled in
|
|
|
|
* the hw itself (with the TILEOFF register).
|
|
|
|
*/
|
|
|
|
int adjusted_x;
|
|
|
|
int adjusted_y;
|
2017-10-18 04:08:11 +08:00
|
|
|
|
|
|
|
int y;
|
2018-08-15 18:34:05 +08:00
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 pixel_blend_mode;
|
2016-01-19 21:35:42 +08:00
|
|
|
} plane;
|
|
|
|
|
|
|
|
struct {
|
2016-11-19 03:53:04 +08:00
|
|
|
const struct drm_format_info *format;
|
2016-01-19 21:35:42 +08:00
|
|
|
unsigned int stride;
|
|
|
|
} fb;
|
|
|
|
} state_cache;
|
|
|
|
|
2017-07-15 03:38:22 +08:00
|
|
|
/*
|
|
|
|
* This structure contains everything that's relevant to program the
|
|
|
|
* hardware registers. When we want to figure out if we need to disable
|
|
|
|
* and re-enable FBC for a new configuration we just check if there's
|
|
|
|
* something different in the struct. The genx_fbc_activate functions
|
|
|
|
* are supposed to read from it in order to program the registers.
|
|
|
|
*/
|
2015-12-24 04:28:11 +08:00
|
|
|
struct intel_fbc_reg_params {
|
2017-01-16 23:21:27 +08:00
|
|
|
struct i915_vma *vma;
|
2018-02-20 21:42:08 +08:00
|
|
|
unsigned long flags;
|
2017-01-16 23:21:27 +08:00
|
|
|
|
2015-12-24 04:28:11 +08:00
|
|
|
struct {
|
|
|
|
enum pipe pipe;
|
2017-11-18 03:19:10 +08:00
|
|
|
enum i9xx_plane_id i9xx_plane;
|
2015-12-24 04:28:11 +08:00
|
|
|
unsigned int fence_y_offset;
|
|
|
|
} crtc;
|
|
|
|
|
|
|
|
struct {
|
2016-11-19 03:53:04 +08:00
|
|
|
const struct drm_format_info *format;
|
2015-12-24 04:28:11 +08:00
|
|
|
unsigned int stride;
|
|
|
|
} fb;
|
|
|
|
|
|
|
|
int cfb_size;
|
2017-08-11 02:30:33 +08:00
|
|
|
unsigned int gen9_wa_cfb_stride;
|
2015-12-24 04:28:11 +08:00
|
|
|
} params;
|
|
|
|
|
2015-10-28 00:50:03 +08:00
|
|
|
const char *no_fbc_reason;
|
2010-02-06 04:42:41 +08:00
|
|
|
};
|
|
|
|
|
2016-12-31 19:20:12 +08:00
|
|
|
/*
|
2015-01-10 04:55:56 +08:00
|
|
|
* HIGH_RR is the highest eDP panel refresh rate read from EDID
|
|
|
|
* LOW_RR is the lowest eDP panel refresh rate found from EDID
|
|
|
|
* parsing for same resolution.
|
|
|
|
*/
|
|
|
|
enum drrs_refresh_rate_type {
|
|
|
|
DRRS_HIGH_RR,
|
|
|
|
DRRS_LOW_RR,
|
|
|
|
DRRS_MAX_RR, /* RR count */
|
|
|
|
};
|
|
|
|
|
|
|
|
enum drrs_support_type {
|
|
|
|
DRRS_NOT_SUPPORTED = 0,
|
|
|
|
STATIC_DRRS_SUPPORT = 1,
|
|
|
|
SEAMLESS_DRRS_SUPPORT = 2
|
2014-04-05 14:43:28 +08:00
|
|
|
};
|
|
|
|
|
2014-07-12 01:30:11 +08:00
|
|
|
struct intel_dp;
|
2015-01-10 04:55:56 +08:00
|
|
|
struct i915_drrs {
|
|
|
|
struct mutex mutex;
|
|
|
|
struct delayed_work work;
|
|
|
|
struct intel_dp *dp;
|
|
|
|
unsigned busy_frontbuffer_bits;
|
|
|
|
enum drrs_refresh_rate_type refresh_rate_type;
|
|
|
|
enum drrs_support_type type;
|
|
|
|
};
|
|
|
|
|
2013-10-04 03:15:06 +08:00
|
|
|
struct i915_psr {
|
2014-07-12 01:30:15 +08:00
|
|
|
struct mutex lock;
|
2018-08-09 22:21:01 +08:00
|
|
|
|
|
|
|
#define I915_PSR_DEBUG_MODE_MASK 0x0f
|
|
|
|
#define I915_PSR_DEBUG_DEFAULT 0x00
|
|
|
|
#define I915_PSR_DEBUG_DISABLE 0x01
|
|
|
|
#define I915_PSR_DEBUG_ENABLE 0x02
|
2018-08-08 22:19:11 +08:00
|
|
|
#define I915_PSR_DEBUG_FORCE_PSR1 0x03
|
2018-08-09 22:21:01 +08:00
|
|
|
#define I915_PSR_DEBUG_IRQ 0x10
|
|
|
|
|
|
|
|
u32 debug;
|
2013-10-04 03:15:06 +08:00
|
|
|
bool sink_support;
|
2019-02-07 05:18:45 +08:00
|
|
|
bool enabled;
|
2018-08-09 22:21:01 +08:00
|
|
|
struct intel_dp *dp;
|
2018-11-28 15:28:38 +08:00
|
|
|
enum pipe pipe;
|
2014-06-13 20:10:03 +08:00
|
|
|
bool active;
|
2018-06-14 03:26:00 +08:00
|
|
|
struct work_struct work;
|
2014-07-12 01:30:16 +08:00
|
|
|
unsigned busy_frontbuffer_bits;
|
2018-03-29 06:30:42 +08:00
|
|
|
bool sink_psr2_support;
|
2016-02-02 04:02:07 +08:00
|
|
|
bool link_standby;
|
2017-01-02 19:30:55 +08:00
|
|
|
bool colorimetry_support;
|
2018-03-29 06:30:42 +08:00
|
|
|
bool psr2_enabled;
|
2018-03-29 06:30:44 +08:00
|
|
|
u8 sink_sync_latency;
|
2018-04-04 05:24:20 +08:00
|
|
|
ktime_t last_entry_attempt;
|
|
|
|
ktime_t last_exit;
|
2018-11-22 06:54:38 +08:00
|
|
|
bool sink_not_reliable;
|
2018-11-22 06:54:39 +08:00
|
|
|
bool irq_aux_error;
|
2018-12-04 08:34:03 +08:00
|
|
|
u16 su_x_granularity;
|
2013-07-12 05:45:00 +08:00
|
|
|
};
|
2013-06-28 07:30:21 +08:00
|
|
|
|
2011-07-13 05:56:22 +08:00
|
|
|
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
|
2012-03-15 22:56:26 +08:00
|
|
|
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
|
2014-07-04 07:27:50 +08:00
|
|
|
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
|
2014-11-20 16:26:30 +08:00
|
|
|
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
|
2017-07-01 00:33:48 +08:00
|
|
|
#define QUIRK_INCREASE_T12_DELAY (1<<6)
|
2018-07-11 04:02:05 +08:00
|
|
|
#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
|
2010-07-20 04:53:12 +08:00
|
|
|
|
2010-03-30 13:34:14 +08:00
|
|
|
struct intel_fbdev;
|
2011-07-08 19:22:42 +08:00
|
|
|
struct intel_fbc_work;
|
2010-03-30 13:34:13 +08:00
|
|
|
|
2012-02-15 05:37:19 +08:00
|
|
|
struct intel_gmbus {
|
|
|
|
struct i2c_adapter adapter;
|
2016-03-07 23:56:59 +08:00
|
|
|
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
|
2012-11-10 23:58:21 +08:00
|
|
|
u32 force_bit;
|
2012-02-15 05:37:19 +08:00
|
|
|
u32 reg0;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 21:33:26 +08:00
|
|
|
i915_reg_t gpio_reg;
|
2012-02-28 07:43:09 +08:00
|
|
|
struct i2c_algo_bit_data bit_algo;
|
2012-02-15 05:37:19 +08:00
|
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
};
|
|
|
|
|
2012-11-03 02:55:02 +08:00
|
|
|
struct i915_suspend_saved_registers {
|
2008-05-07 10:27:53 +08:00
|
|
|
u32 saveDSPARB;
|
2007-11-22 12:14:14 +08:00
|
|
|
u32 saveFBC_CONTROL;
|
2008-02-17 11:19:29 +08:00
|
|
|
u32 saveCACHE_MODE_0;
|
|
|
|
u32 saveMI_ARB_STATE;
|
2007-11-22 12:14:14 +08:00
|
|
|
u32 saveSWF0[16];
|
|
|
|
u32 saveSWF1[16];
|
2015-09-19 01:03:43 +08:00
|
|
|
u32 saveSWF3[3];
|
2019-01-18 20:01:24 +08:00
|
|
|
u64 saveFENCE[I915_MAX_NUM_FENCES];
|
2011-07-27 04:53:06 +08:00
|
|
|
u32 savePCH_PORT_HOTPLUG;
|
2014-12-11 04:16:05 +08:00
|
|
|
u16 saveGCDGMBUS;
|
2012-11-03 02:55:02 +08:00
|
|
|
};
|
2012-11-03 02:55:03 +08:00
|
|
|
|
2014-05-05 20:19:56 +08:00
|
|
|
struct vlv_s0ix_state {
|
|
|
|
/* GAM */
|
|
|
|
u32 wr_watermark;
|
|
|
|
u32 gfx_prio_ctrl;
|
|
|
|
u32 arb_mode;
|
|
|
|
u32 gfx_pend_tlb0;
|
|
|
|
u32 gfx_pend_tlb1;
|
|
|
|
u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
|
|
|
|
u32 media_max_req_count;
|
|
|
|
u32 gfx_max_req_count;
|
|
|
|
u32 render_hwsp;
|
|
|
|
u32 ecochk;
|
|
|
|
u32 bsd_hwsp;
|
|
|
|
u32 blt_hwsp;
|
|
|
|
u32 tlb_rd_addr;
|
|
|
|
|
|
|
|
/* MBC */
|
|
|
|
u32 g3dctl;
|
|
|
|
u32 gsckgctl;
|
|
|
|
u32 mbctl;
|
|
|
|
|
|
|
|
/* GCP */
|
|
|
|
u32 ucgctl1;
|
|
|
|
u32 ucgctl3;
|
|
|
|
u32 rcgctl1;
|
|
|
|
u32 rcgctl2;
|
|
|
|
u32 rstctl;
|
|
|
|
u32 misccpctl;
|
|
|
|
|
|
|
|
/* GPM */
|
|
|
|
u32 gfxpause;
|
|
|
|
u32 rpdeuhwtc;
|
|
|
|
u32 rpdeuc;
|
|
|
|
u32 ecobus;
|
|
|
|
u32 pwrdwnupctl;
|
|
|
|
u32 rp_down_timeout;
|
|
|
|
u32 rp_deucsw;
|
|
|
|
u32 rcubmabdtmr;
|
|
|
|
u32 rcedata;
|
|
|
|
u32 spare2gh;
|
|
|
|
|
|
|
|
/* Display 1 CZ domain */
|
|
|
|
u32 gt_imr;
|
|
|
|
u32 gt_ier;
|
|
|
|
u32 pm_imr;
|
|
|
|
u32 pm_ier;
|
|
|
|
u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
|
|
|
|
|
|
|
|
/* GT SA CZ domain */
|
|
|
|
u32 tilectl;
|
|
|
|
u32 gt_fifoctl;
|
|
|
|
u32 gtlc_wake_ctrl;
|
|
|
|
u32 gtlc_survive;
|
|
|
|
u32 pmwgicz;
|
|
|
|
|
|
|
|
/* Display 2 CZ domain */
|
|
|
|
u32 gu_ctl0;
|
|
|
|
u32 gu_ctl1;
|
2015-04-02 05:22:57 +08:00
|
|
|
u32 pcbr;
|
2014-05-05 20:19:56 +08:00
|
|
|
u32 clock_gate_dis2;
|
|
|
|
};
|
|
|
|
|
2014-07-11 03:31:18 +08:00
|
|
|
struct intel_rps_ei {
|
2017-03-15 23:43:03 +08:00
|
|
|
ktime_t ktime;
|
2014-07-11 03:31:18 +08:00
|
|
|
u32 render_c0;
|
|
|
|
u32 media_c0;
|
2014-07-04 05:33:01 +08:00
|
|
|
};
|
|
|
|
|
2017-10-11 05:30:06 +08:00
|
|
|
struct intel_rps {
|
2019-04-26 16:17:21 +08:00
|
|
|
struct mutex lock; /* protects enabling and the worker */
|
|
|
|
|
drm/i915: sanitize rps irq disabling
When disabling the RPS interrupts there is a tricky dependency between
the thread disabling the interrupts, the RPS interrupt handler and the
corresponding RPS work. The RPS work can reenable the interrupts, so
there is no straightforward order in the disabling thread to (1) make
sure that any RPS work is flushed and to (2) disable all RPS
interrupts. Currently this is solved by masking the interrupts using two
separate mask registers (first level display IMR and PM IMR) and doing
the disabling when all first level interrupts are disabled.
This works, but the requirement to run with all first level interrupts
disabled is unnecessary making the suspend / unload time ordering of RPS
disabling wrt. other unitialization steps difficult and error prone.
Removing this restriction allows us to disable RPS early during suspend
/ unload and forget about it for the rest of the sequence. By adding a
more explicit method for avoiding the above race, it also becomes easier
to prove its correctness. Finally currently we can hit the WARN in
snb_update_pm_irq(), when a final RPS work runs with the first level
interrupts already disabled. This won't lead to any problem (due to the
separate interrupt masks), but with the change in this and the next
patch we can get rid of the WARN, while leaving it in place for other
scenarios.
To address the above points, add a new RPS interrupts_enabled flag and
use this during RPS disabling to avoid requeuing the RPS work and
reenabling of the RPS interrupts. Since the interrupt disabling happens
now in intel_suspend_gt_powersave(), we will disable RPS interrupts
explicitly during suspend (and not just through the first level mask),
but there is no problem doing so, it's also more consistent and allows
us to unify more of the RPS disabling during suspend and unload time in
the next patch.
v2/v3:
- rebase on patch "drm/i915: move rps irq disable one level up" in the
patchset
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19 21:30:04 +08:00
|
|
|
/*
|
|
|
|
* work, interrupts_enabled and pm_iir are protected by
|
|
|
|
* dev_priv->irq_lock
|
|
|
|
*/
|
2012-11-03 02:55:03 +08:00
|
|
|
struct work_struct work;
|
drm/i915: sanitize rps irq disabling
When disabling the RPS interrupts there is a tricky dependency between
the thread disabling the interrupts, the RPS interrupt handler and the
corresponding RPS work. The RPS work can reenable the interrupts, so
there is no straightforward order in the disabling thread to (1) make
sure that any RPS work is flushed and to (2) disable all RPS
interrupts. Currently this is solved by masking the interrupts using two
separate mask registers (first level display IMR and PM IMR) and doing
the disabling when all first level interrupts are disabled.
This works, but the requirement to run with all first level interrupts
disabled is unnecessary making the suspend / unload time ordering of RPS
disabling wrt. other unitialization steps difficult and error prone.
Removing this restriction allows us to disable RPS early during suspend
/ unload and forget about it for the rest of the sequence. By adding a
more explicit method for avoiding the above race, it also becomes easier
to prove its correctness. Finally currently we can hit the WARN in
snb_update_pm_irq(), when a final RPS work runs with the first level
interrupts already disabled. This won't lead to any problem (due to the
separate interrupt masks), but with the change in this and the next
patch we can get rid of the WARN, while leaving it in place for other
scenarios.
To address the above points, add a new RPS interrupts_enabled flag and
use this during RPS disabling to avoid requeuing the RPS work and
reenabling of the RPS interrupts. Since the interrupt disabling happens
now in intel_suspend_gt_powersave(), we will disable RPS interrupts
explicitly during suspend (and not just through the first level mask),
but there is no problem doing so, it's also more consistent and allows
us to unify more of the RPS disabling during suspend and unload time in
the next patch.
v2/v3:
- rebase on patch "drm/i915: move rps irq disable one level up" in the
patchset
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-19 21:30:04 +08:00
|
|
|
bool interrupts_enabled;
|
2012-11-03 02:55:03 +08:00
|
|
|
u32 pm_iir;
|
2013-07-05 05:35:28 +08:00
|
|
|
|
2016-09-13 04:19:35 +08:00
|
|
|
/* PM interrupt bits that should never be masked */
|
2017-03-11 10:37:00 +08:00
|
|
|
u32 pm_intrmsk_mbz;
|
2016-05-31 16:28:27 +08:00
|
|
|
|
2014-03-20 09:31:11 +08:00
|
|
|
/* Frequencies are stored in potentially platform dependent multiples.
|
|
|
|
* In other words, *_freq needs to be multiplied by X to be interesting.
|
|
|
|
* Soft limits are those which are used for the dynamic reclocking done
|
|
|
|
* by the driver (raise frequencies under heavy loads, and lower for
|
|
|
|
* lighter loads). Hard limits are those imposed by the hardware.
|
|
|
|
*
|
|
|
|
* A distinction is made for overclocking, which is never enabled by
|
|
|
|
* default, and is considered to be above the hard limit if it's
|
|
|
|
* possible at all.
|
|
|
|
*/
|
|
|
|
u8 cur_freq; /* Current frequency (cached, may not == HW) */
|
|
|
|
u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
|
|
|
|
u8 max_freq_softlimit; /* Max frequency permitted by the driver */
|
|
|
|
u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
|
|
|
|
u8 min_freq; /* AKA RPn. Minimum frequency */
|
2016-07-13 16:10:35 +08:00
|
|
|
u8 boost_freq; /* Frequency to request when wait boosting */
|
2015-03-18 17:48:21 +08:00
|
|
|
u8 idle_freq; /* Frequency to request when we are idle */
|
2014-03-20 09:31:11 +08:00
|
|
|
u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
|
|
|
|
u8 rp1_freq; /* "less than" RP0 power/freqency */
|
|
|
|
u8 rp0_freq; /* Non-overclocked max frequency. */
|
2016-03-05 03:43:02 +08:00
|
|
|
u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
|
2012-11-03 02:14:00 +08:00
|
|
|
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
int last_adj;
|
drm/i915: Interactive RPS mode
RPS provides a feedback loop where we use the load during the previous
evaluation interval to decide whether to up or down clock the GPU
frequency. Our responsiveness is split into 3 regimes, a high and low
plateau with the intent to keep the gpu clocked high to cover occasional
stalls under high load, and low despite occasional glitches under steady
low load, and inbetween. However, we run into situations like kodi where
we want to stay at low power (video decoding is done efficiently
inside the fixed function HW and doesn't need high clocks even for high
bitrate streams), but just occasionally the pipeline is more complex
than a video decode and we need a smidgen of extra GPU power to present
on time. In the high power regime, we sample at sub frame intervals with
a bias to upclocking, and conversely at low power we sample over a few
frames worth to provide what we consider to be the right levels of
responsiveness respectively. At low power, we more or less expect to be
kicked out to high power at the start of a busy sequence by waitboosting.
Prior to commit e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active
request") whenever we missed the frame or stalled, we would immediate go
full throttle and upclock the GPU to max. But in commit e9af4ea2b9e7, we
relaxed the waitboosting to only apply if the pipeline was deep to avoid
over-committing resources for a near miss. Sadly though, a near miss is
still a miss, and perceptible as jitter in the frame delivery.
To try and prevent the near miss before having to resort to boosting
after the fact, we use the pageflip queue as an indication that we are
in an "interactive" regime and so should sample the load more frequently
to provide power before the frame misses it vblank. This will make us
more favorable to providing a small power increase (one or two bins) as
required rather than going all the way to maximum and then having to
work back down again. (We still keep the waitboosting mechanism around
just in case a dramatic change in system load requires urgent uplocking,
faster than we can provide in a few evaluation intervals.)
v2: Reduce rps_set_interactive to a boolean parameter to avoid the
confusion of what if they wanted a new power mode after pinning to a
different mode (which to choose?)
v3: Only reprogram RPS while the GT is awake, it will be set when we
wake the GT, and while off warns about being used outside of rpm.
v4: Fix deferred application of interactive mode
v5: s/state/interactive/
v6: Group the mutex with its principle in a substruct
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107111
Fixes: e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active request")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180731132629.3381-1-chris@chris-wilson.co.uk
2018-07-31 21:26:29 +08:00
|
|
|
|
|
|
|
struct {
|
|
|
|
struct mutex mutex;
|
|
|
|
|
|
|
|
enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
|
|
|
|
unsigned int interactive;
|
|
|
|
|
|
|
|
u8 up_threshold; /* Current %busy required to uplock */
|
|
|
|
u8 down_threshold; /* Current %busy required to downclock */
|
|
|
|
} power;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-26 00:34:57 +08:00
|
|
|
|
2013-10-11 04:58:50 +08:00
|
|
|
bool enabled;
|
2017-06-28 20:35:48 +08:00
|
|
|
atomic_t num_waiters;
|
|
|
|
atomic_t boosts;
|
2012-11-03 02:14:01 +08:00
|
|
|
|
2014-07-11 03:31:18 +08:00
|
|
|
/* manual wa residency calculations */
|
2017-03-10 05:12:30 +08:00
|
|
|
struct intel_rps_ei ei;
|
2012-11-03 02:55:03 +08:00
|
|
|
};
|
|
|
|
|
2017-10-11 05:30:10 +08:00
|
|
|
struct intel_rc6 {
|
|
|
|
bool enabled;
|
2018-02-09 00:00:36 +08:00
|
|
|
u64 prev_hw_residency[4];
|
|
|
|
u64 cur_residency[4];
|
2017-10-11 05:30:10 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct intel_llc_pstate {
|
|
|
|
bool enabled;
|
|
|
|
};
|
|
|
|
|
2017-10-11 05:30:06 +08:00
|
|
|
struct intel_gen6_power_mgmt {
|
|
|
|
struct intel_rps rps;
|
2017-10-11 05:30:10 +08:00
|
|
|
struct intel_rc6 rc6;
|
|
|
|
struct intel_llc_pstate llc_pstate;
|
2017-10-11 05:30:06 +08:00
|
|
|
};
|
|
|
|
|
2012-11-30 05:18:51 +08:00
|
|
|
/* defined intel_pm.c */
|
|
|
|
extern spinlock_t mchdev_lock;
|
|
|
|
|
2012-11-03 02:55:03 +08:00
|
|
|
struct intel_ilk_power_mgmt {
|
|
|
|
u8 cur_delay;
|
|
|
|
u8 min_delay;
|
|
|
|
u8 max_delay;
|
|
|
|
u8 fmax;
|
|
|
|
u8 fstart;
|
|
|
|
|
|
|
|
u64 last_count1;
|
|
|
|
unsigned long last_time1;
|
|
|
|
unsigned long chipset_power;
|
|
|
|
u64 last_count2;
|
2014-07-17 05:05:06 +08:00
|
|
|
u64 last_time2;
|
2012-11-03 02:55:03 +08:00
|
|
|
unsigned long gfx_power;
|
|
|
|
u8 corr;
|
|
|
|
|
|
|
|
int c_m;
|
|
|
|
int r_t;
|
|
|
|
};
|
|
|
|
|
2013-09-20 02:13:41 +08:00
|
|
|
#define MAX_L3_SLICES 2
|
2012-11-03 02:55:07 +08:00
|
|
|
struct intel_l3_parity {
|
2013-09-20 02:13:41 +08:00
|
|
|
u32 *remap_info[MAX_L3_SLICES];
|
2012-11-03 02:55:07 +08:00
|
|
|
struct work_struct error_work;
|
2013-09-20 02:13:41 +08:00
|
|
|
int which_slice;
|
2012-11-03 02:55:07 +08:00
|
|
|
};
|
|
|
|
|
2012-11-15 00:14:03 +08:00
|
|
|
struct i915_gem_mm {
|
|
|
|
/** Memory allocator for GTT stolen memory */
|
|
|
|
struct drm_mm stolen;
|
2015-07-03 06:25:09 +08:00
|
|
|
/** Protects the usage of the GTT stolen memory allocator. This is
|
|
|
|
* always the inner lock when overlapping with struct_mutex. */
|
|
|
|
struct mutex stolen_lock;
|
|
|
|
|
2017-10-16 19:40:37 +08:00
|
|
|
/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
|
|
|
|
spinlock_t obj_lock;
|
|
|
|
|
2012-11-15 00:14:03 +08:00
|
|
|
/**
|
2019-06-12 18:57:20 +08:00
|
|
|
* List of objects which are purgeable.
|
2012-11-15 00:14:03 +08:00
|
|
|
*/
|
2019-06-12 18:57:20 +08:00
|
|
|
struct list_head purge_list;
|
|
|
|
|
2019-05-31 04:34:59 +08:00
|
|
|
/**
|
2019-06-12 18:57:20 +08:00
|
|
|
* List of objects which have allocated pages and are shrinkable.
|
2019-05-31 04:34:59 +08:00
|
|
|
*/
|
2019-06-12 18:57:20 +08:00
|
|
|
struct list_head shrink_list;
|
2012-11-15 00:14:03 +08:00
|
|
|
|
2016-10-28 20:58:42 +08:00
|
|
|
/**
|
|
|
|
* List of objects which are pending destruction.
|
|
|
|
*/
|
|
|
|
struct llist_head free_list;
|
|
|
|
struct work_struct free_work;
|
2018-02-20 06:06:31 +08:00
|
|
|
/**
|
|
|
|
* Count of objects pending destructions. Used to skip needlessly
|
|
|
|
* waiting on an RCU barrier if no objects are waiting to be freed.
|
|
|
|
*/
|
|
|
|
atomic_t free_count;
|
2016-10-28 20:58:42 +08:00
|
|
|
|
2017-08-23 01:38:28 +08:00
|
|
|
/**
|
|
|
|
* Small stash of WC pages
|
|
|
|
*/
|
2018-07-05 02:55:18 +08:00
|
|
|
struct pagestash wc_stash;
|
2017-08-23 01:38:28 +08:00
|
|
|
|
2017-10-07 06:18:14 +08:00
|
|
|
/**
|
|
|
|
* tmpfs instance used for shmem backed objects
|
|
|
|
*/
|
|
|
|
struct vfsmount *gemfs;
|
|
|
|
|
2014-05-20 15:28:43 +08:00
|
|
|
struct notifier_block oom_notifier;
|
2016-04-04 21:46:43 +08:00
|
|
|
struct notifier_block vmap_notifier;
|
2014-03-25 21:23:04 +08:00
|
|
|
struct shrinker shrinker;
|
2012-11-15 00:14:03 +08:00
|
|
|
|
2017-06-16 22:05:22 +08:00
|
|
|
/**
|
|
|
|
* Workqueue to fault in userptr pages, flushed by the execbuf
|
|
|
|
* when required but otherwise left to userspace to try again
|
|
|
|
* on EAGAIN.
|
|
|
|
*/
|
|
|
|
struct workqueue_struct *userptr_wq;
|
|
|
|
|
2017-05-03 17:39:18 +08:00
|
|
|
u64 unordered_timeline;
|
|
|
|
|
2012-11-15 00:14:03 +08:00
|
|
|
/** Bit 6 swizzling required for X tiling */
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 bit_6_swizzle_x;
|
2012-11-15 00:14:03 +08:00
|
|
|
/** Bit 6 swizzling required for Y tiling */
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 bit_6_swizzle_y;
|
2012-11-15 00:14:03 +08:00
|
|
|
|
2019-05-31 04:35:00 +08:00
|
|
|
/* shrinker accounting, also useful for userland debugging */
|
|
|
|
u64 shrink_memory;
|
|
|
|
u32 shrink_count;
|
2012-11-15 00:14:03 +08:00
|
|
|
};
|
|
|
|
|
2017-12-12 03:41:34 +08:00
|
|
|
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
|
|
|
|
|
2016-10-28 20:58:24 +08:00
|
|
|
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
|
|
|
|
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
|
|
|
|
|
2016-11-18 21:09:04 +08:00
|
|
|
#define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
|
|
|
|
#define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
|
|
|
|
|
2018-06-02 18:48:53 +08:00
|
|
|
#define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
|
|
|
|
|
2013-09-13 04:06:24 +08:00
|
|
|
struct ddi_vbt_port_info {
|
2019-05-31 21:14:52 +08:00
|
|
|
/* Non-NULL if port present. */
|
|
|
|
const struct child_device_config *child;
|
|
|
|
|
2017-10-30 22:57:02 +08:00
|
|
|
int max_tmds_clock;
|
|
|
|
|
2014-08-01 18:07:54 +08:00
|
|
|
/*
|
|
|
|
* This is an index in the HDMI/DVI DDI buffer translation table.
|
|
|
|
* The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
|
|
|
|
* populate this field.
|
|
|
|
*/
|
|
|
|
#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
|
2019-01-18 20:01:24 +08:00
|
|
|
u8 hdmi_level_shift;
|
2013-09-13 04:12:18 +08:00
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
u8 supports_dvi:1;
|
|
|
|
u8 supports_hdmi:1;
|
|
|
|
u8 supports_dp:1;
|
|
|
|
u8 supports_edp:1;
|
|
|
|
u8 supports_typec_usb:1;
|
|
|
|
u8 supports_tbt:1;
|
2015-08-08 08:01:16 +08:00
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
u8 alternate_aux_channel;
|
|
|
|
u8 alternate_ddc_pin;
|
2015-07-10 19:10:55 +08:00
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
u8 dp_boost_level;
|
|
|
|
u8 hdmi_boost_level;
|
2018-02-01 19:03:43 +08:00
|
|
|
int dp_max_link_rate; /* 0 for not limited by VBT */
|
2013-09-13 04:06:24 +08:00
|
|
|
};
|
|
|
|
|
2014-11-15 00:52:30 +08:00
|
|
|
enum psr_lines_to_wait {
|
|
|
|
PSR_0_LINES_TO_WAIT = 0,
|
|
|
|
PSR_1_LINE_TO_WAIT,
|
|
|
|
PSR_4_LINES_TO_WAIT,
|
|
|
|
PSR_8_LINES_TO_WAIT
|
2014-03-28 12:44:57 +08:00
|
|
|
};
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
struct intel_vbt_data {
|
|
|
|
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
|
|
|
|
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
|
|
|
|
|
|
|
|
/* Feature bits */
|
|
|
|
unsigned int int_tv_support:1;
|
|
|
|
unsigned int lvds_dither:1;
|
|
|
|
unsigned int int_crt_support:1;
|
|
|
|
unsigned int lvds_use_ssc:1;
|
2018-05-08 22:08:14 +08:00
|
|
|
unsigned int int_lvds_support:1;
|
2013-05-10 07:03:18 +08:00
|
|
|
unsigned int display_clock_mode:1;
|
|
|
|
unsigned int fdi_rx_polarity_inverted:1;
|
2016-04-08 21:28:12 +08:00
|
|
|
unsigned int panel_type:4;
|
2013-05-10 07:03:18 +08:00
|
|
|
int lvds_ssc_freq;
|
|
|
|
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
|
2018-10-22 22:20:15 +08:00
|
|
|
enum drm_panel_orientation orientation;
|
2013-05-10 07:03:18 +08:00
|
|
|
|
2014-03-28 12:44:57 +08:00
|
|
|
enum drrs_support_type drrs_type;
|
|
|
|
|
2016-03-24 23:50:20 +08:00
|
|
|
struct {
|
|
|
|
int rate;
|
|
|
|
int lanes;
|
|
|
|
int preemphasis;
|
|
|
|
int vswing;
|
2016-03-24 23:50:21 +08:00
|
|
|
bool low_vswing;
|
2016-03-24 23:50:20 +08:00
|
|
|
bool initialized;
|
|
|
|
int bpp;
|
|
|
|
struct edp_power_seq pps;
|
|
|
|
} edp;
|
2013-05-10 07:03:18 +08:00
|
|
|
|
2014-11-15 00:52:30 +08:00
|
|
|
struct {
|
2018-05-09 08:35:24 +08:00
|
|
|
bool enable;
|
2014-11-15 00:52:30 +08:00
|
|
|
bool full_link;
|
|
|
|
bool require_aux_wakeup;
|
|
|
|
int idle_frames;
|
|
|
|
enum psr_lines_to_wait lines_to_wait;
|
2018-05-22 17:27:23 +08:00
|
|
|
int tp1_wakeup_time_us;
|
|
|
|
int tp2_tp3_wakeup_time_us;
|
2019-03-13 03:57:41 +08:00
|
|
|
int psr2_tp2_tp3_wakeup_time_us;
|
2014-11-15 00:52:30 +08:00
|
|
|
} psr;
|
|
|
|
|
2013-12-15 06:38:29 +08:00
|
|
|
struct {
|
|
|
|
u16 pwm_freq_hz;
|
2014-04-09 16:22:06 +08:00
|
|
|
bool present;
|
2013-12-15 06:38:29 +08:00
|
|
|
bool active_low_pwm;
|
2014-06-24 23:27:39 +08:00
|
|
|
u8 min_brightness; /* min_brightness/255 of max */
|
2016-12-08 17:26:18 +08:00
|
|
|
u8 controller; /* brightness controller number */
|
2016-04-26 21:14:24 +08:00
|
|
|
enum intel_backlight_type type;
|
2013-12-15 06:38:29 +08:00
|
|
|
} backlight;
|
|
|
|
|
2013-08-27 20:12:25 +08:00
|
|
|
/* MIPI DSI */
|
|
|
|
struct {
|
|
|
|
u16 panel_id;
|
2014-04-14 13:30:34 +08:00
|
|
|
struct mipi_config *config;
|
|
|
|
struct mipi_pps_data *pps;
|
2017-10-13 20:44:59 +08:00
|
|
|
u16 bl_ports;
|
|
|
|
u16 cabc_ports;
|
2014-04-14 13:30:34 +08:00
|
|
|
u8 seq_version;
|
|
|
|
u32 size;
|
|
|
|
u8 *data;
|
2015-12-21 21:10:57 +08:00
|
|
|
const u8 *sequence[MIPI_SEQ_MAX];
|
drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence v3
So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
index = 3, one of which has been kindly provided to me by Jan Brummer,
where not working with the i915 driver, giving a black screen on the
first modeset.
The problem with at least these Dells is that their VBT defines a MIPI
ASSERT sequence, but not a DEASSERT sequence. Instead they DEASSERT the
reset in their INIT_OTP sequence, but the deassert must be done before
calling intel_dsi_device_ready(), so that is too late.
Simply doing the INIT_OTP sequence earlier is not enough to fix this,
because the INIT_OTP sequence also sends various MIPI packets to the
panel, which can only happen after calling intel_dsi_device_ready().
This commit fixes this by splitting the INIT_OTP sequence into everything
before the first DSI packet and everything else, including the first DSI
packet. The first part (everything before the first DSI packet) is then
used as deassert sequence.
Changed in v2:
-Split the init OTP sequence into a deassert reset and the actual init
OTP sequence, instead of calling it earlier and then having the first
mipi_exec_send_packet() call call intel_dsi_device_ready().
Changes in v3:
-Move the whole shebang to intel_bios.c
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82880
References: https://bugs.freedesktop.org/show_bug.cgi?id=101205
Cc: Jan-Michael Brummer <jan.brummer@tabos.org>
Reported-by: Jan-Michael Brummer <jan.brummer@tabos.org>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180214082151.25015-3-hdegoede@redhat.com
2018-02-14 16:21:51 +08:00
|
|
|
u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
|
2018-10-22 22:20:15 +08:00
|
|
|
enum drm_panel_orientation orientation;
|
2013-08-27 20:12:25 +08:00
|
|
|
} dsi;
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
int crt_ddc_pin;
|
|
|
|
|
|
|
|
int child_dev_num;
|
2017-08-25 02:54:03 +08:00
|
|
|
struct child_device_config *child_dev;
|
2013-09-13 04:06:24 +08:00
|
|
|
|
|
|
|
struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
|
2016-03-24 23:50:22 +08:00
|
|
|
struct sdvo_device_mapping sdvo_mappings[2];
|
2013-05-10 07:03:18 +08:00
|
|
|
};
|
|
|
|
|
2013-08-07 03:24:04 +08:00
|
|
|
enum intel_ddb_partitioning {
|
|
|
|
INTEL_DDB_PART_1_2,
|
|
|
|
INTEL_DDB_PART_5_6, /* IVB+ */
|
|
|
|
};
|
|
|
|
|
2013-08-07 03:24:05 +08:00
|
|
|
struct intel_wm_level {
|
|
|
|
bool enable;
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 pri_val;
|
|
|
|
u32 spr_val;
|
|
|
|
u32 cur_val;
|
|
|
|
u32 fbc_val;
|
2013-08-07 03:24:05 +08:00
|
|
|
};
|
|
|
|
|
2013-12-17 20:46:36 +08:00
|
|
|
struct ilk_wm_values {
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 wm_pipe[3];
|
|
|
|
u32 wm_lp[3];
|
|
|
|
u32 wm_lp_spr[3];
|
|
|
|
u32 wm_linetime[3];
|
2013-10-10 00:18:03 +08:00
|
|
|
bool enable_fbc_wm;
|
|
|
|
enum intel_ddb_partitioning partitioning;
|
|
|
|
};
|
|
|
|
|
2017-04-22 02:14:21 +08:00
|
|
|
struct g4x_pipe_wm {
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 plane[I915_MAX_PLANES];
|
|
|
|
u16 fbc;
|
2015-06-25 03:00:04 +08:00
|
|
|
};
|
2015-03-06 03:19:49 +08:00
|
|
|
|
2017-04-22 02:14:21 +08:00
|
|
|
struct g4x_sr_wm {
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 plane;
|
|
|
|
u16 cursor;
|
|
|
|
u16 fbc;
|
2016-11-29 01:37:08 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct vlv_wm_ddl_values {
|
2019-01-18 20:01:24 +08:00
|
|
|
u8 plane[I915_MAX_PLANES];
|
2015-06-25 03:00:04 +08:00
|
|
|
};
|
2015-03-06 03:19:49 +08:00
|
|
|
|
2015-06-25 03:00:04 +08:00
|
|
|
struct vlv_wm_values {
|
2017-04-22 02:14:21 +08:00
|
|
|
struct g4x_pipe_wm pipe[3];
|
|
|
|
struct g4x_sr_wm sr;
|
2016-11-29 01:37:08 +08:00
|
|
|
struct vlv_wm_ddl_values ddl[3];
|
2019-01-18 20:01:24 +08:00
|
|
|
u8 level;
|
2015-06-25 03:00:03 +08:00
|
|
|
bool cxsr;
|
2015-03-06 03:19:45 +08:00
|
|
|
};
|
|
|
|
|
2017-04-22 02:14:29 +08:00
|
|
|
struct g4x_wm_values {
|
|
|
|
struct g4x_pipe_wm pipe[2];
|
|
|
|
struct g4x_sr_wm sr;
|
|
|
|
struct g4x_sr_wm hpll;
|
|
|
|
bool cxsr;
|
|
|
|
bool hpll_en;
|
|
|
|
bool fbc_en;
|
|
|
|
};
|
|
|
|
|
2014-11-05 01:06:41 +08:00
|
|
|
struct skl_ddb_entry {
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 start, end; /* in number of blocks, 'end' is exclusive */
|
2014-11-05 01:06:41 +08:00
|
|
|
};
|
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
|
2014-11-05 01:06:41 +08:00
|
|
|
{
|
2014-11-05 01:06:53 +08:00
|
|
|
return entry->end - entry->start;
|
2014-11-05 01:06:41 +08:00
|
|
|
}
|
|
|
|
|
2014-11-05 01:06:52 +08:00
|
|
|
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
|
|
|
|
const struct skl_ddb_entry *e2)
|
|
|
|
{
|
|
|
|
if (e1->start == e2->start && e1->end == e2->end)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-11-05 01:06:41 +08:00
|
|
|
struct skl_ddb_allocation {
|
2018-04-26 22:25:15 +08:00
|
|
|
u8 enabled_slices; /* GEN11 has configurable 2 slices */
|
2014-11-05 01:06:41 +08:00
|
|
|
};
|
|
|
|
|
2018-04-09 11:41:00 +08:00
|
|
|
struct skl_ddb_values {
|
2016-05-12 22:06:07 +08:00
|
|
|
unsigned dirty_pipes;
|
2014-11-05 01:06:41 +08:00
|
|
|
struct skl_ddb_allocation ddb;
|
2014-11-05 01:06:40 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
struct skl_wm_level {
|
2018-12-22 01:14:32 +08:00
|
|
|
u16 min_ddb_alloc;
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 plane_res_b;
|
|
|
|
u8 plane_res_l;
|
2018-10-17 06:01:24 +08:00
|
|
|
bool plane_en;
|
2019-02-14 00:54:23 +08:00
|
|
|
bool ignore_lines;
|
2014-11-05 01:06:40 +08:00
|
|
|
};
|
|
|
|
|
2017-08-17 21:45:23 +08:00
|
|
|
/* Stores plane specific WM parameters */
|
|
|
|
struct skl_wm_params {
|
|
|
|
bool x_tiled, y_tiled;
|
|
|
|
bool rc_surface;
|
2018-04-09 11:41:04 +08:00
|
|
|
bool is_planar;
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 width;
|
|
|
|
u8 cpp;
|
|
|
|
u32 plane_pixel_rate;
|
|
|
|
u32 y_min_scanlines;
|
|
|
|
u32 plane_bytes_per_line;
|
2017-08-17 21:45:23 +08:00
|
|
|
uint_fixed_16_16_t plane_blocks_per_line;
|
|
|
|
uint_fixed_16_16_t y_tile_minimum;
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 linetime_us;
|
|
|
|
u32 dbuf_block_size;
|
2017-08-17 21:45:23 +08:00
|
|
|
};
|
|
|
|
|
2013-10-16 19:30:34 +08:00
|
|
|
enum intel_pipe_crc_source {
|
|
|
|
INTEL_PIPE_CRC_SOURCE_NONE,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_PLANE1,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_PLANE2,
|
2019-02-15 03:22:19 +08:00
|
|
|
INTEL_PIPE_CRC_SOURCE_PLANE3,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_PLANE4,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_PLANE5,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_PLANE6,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_PLANE7,
|
2013-10-17 04:55:48 +08:00
|
|
|
INTEL_PIPE_CRC_SOURCE_PIPE,
|
2013-10-17 04:55:58 +08:00
|
|
|
/* TV/DP on pre-gen5/vlv can't use the pipe source. */
|
|
|
|
INTEL_PIPE_CRC_SOURCE_TV,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_DP_B,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_DP_C,
|
|
|
|
INTEL_PIPE_CRC_SOURCE_DP_D,
|
2013-11-01 17:50:20 +08:00
|
|
|
INTEL_PIPE_CRC_SOURCE_AUTO,
|
2013-10-16 19:30:34 +08:00
|
|
|
INTEL_PIPE_CRC_SOURCE_MAX,
|
|
|
|
};
|
|
|
|
|
2013-10-16 01:55:29 +08:00
|
|
|
#define INTEL_PIPE_CRC_ENTRIES_NR 128
|
2013-10-16 01:55:27 +08:00
|
|
|
struct intel_pipe_crc {
|
2013-10-21 21:29:30 +08:00
|
|
|
spinlock_t lock;
|
2017-01-10 21:43:04 +08:00
|
|
|
int skipped;
|
2018-06-28 15:23:02 +08:00
|
|
|
enum intel_pipe_crc_source source;
|
2013-10-16 01:55:27 +08:00
|
|
|
};
|
|
|
|
|
drm/i915: Track frontbuffer invalidation/flushing
So these are the guts of the new beast. This tracks when a frontbuffer
gets invalidated (due to frontbuffer rendering) and hence should be
constantly scaned out, and when it's flushed again and can be
compressed/one-shot-upload.
Rules for flushing are simple: The frontbuffer needs one more full
upload starting from the next vblank. Which means that the flushing
can _only_ be called once the frontbuffer update has been latched.
But this poses a problem for pageflips: We can't just delay the
flushing until the pageflip is latched, since that would pose the risk
that we override frontbuffer rendering that has been scheduled
in-between the pageflip ioctl and the actual latching.
To handle this track asynchronous invalidations (and also pageflip)
state per-ring and delay any in-between flushing until the rendering
has completed. And also cancel any delayed flushing if we get a new
invalidation request (whether delayed or not).
Also call intel_mark_fb_busy in both cases in all cases to make sure
that we keep the screen at the highest refresh rate both on flips,
synchronous plane updates and for frontbuffer rendering.
v2: Lots of improvements
Suggestions from Chris:
- Move invalidate/flush in flush_*_domain and set_to_*_domain.
- Drop the flush in busy_ioctl since it's redundant. Was a leftover
from an earlier concept to track flips/delayed flushes.
- Don't forget about the initial modeset enable/final disable.
Suggested by Chris.
Track flips accurately, too. Since flips complete independently of
rendering we need to track pending flips in a separate mask. Again if
an invalidate happens we need to cancel the evenutal flush to avoid
races.
v3:
Provide correct header declarations for flip functions. Currently not
needed outside of intel_display.c, but part of the proper interface.
v4: Add proper domain management to fbcon so that the fbcon buffer is
also tracked correctly.
v5: Fixup locking around the fbcon set_to_gtt_domain call.
v6: More comments from Chris:
- Split out fbcon changes.
- Drop superflous checks for potential scanout before calling intel_fb
functions - we can micro-optimize this later.
- s/intel_fb_/intel_fb_obj_/ to make it clear that this deals in gem
object. We already have precedence for fb_obj in the pin_and_fence
functions.
v7: Clarify the semantics of the flip flush handling by renaming
things a bit:
- Don't go through a gem object but take the relevant frontbuffer bits
directly. These functions center on the plane, the actual object is
irrelevant - even a flip to the same object as already active should
cause a flush.
- Add a new intel_frontbuffer_flip for synchronous plane updates. It
currently just calls intel_frontbuffer_flush since the implemenation
differs.
This way we achieve a clear split between one-shot update events on
one side and frontbuffer rendering with potentially a very long delay
between the invalidate and flush.
Chris and I also had some discussions about mark_busy and whether it
is appropriate to call from flush. But mark busy is a state which
should be derived from the 3 events (invalidate, flush, flip) we now
have by the users, like psr does by tracking relevant information in
psr.busy_frontbuffer_bits. DRRS (the only real use of mark_busy for
frontbuffer) needs to have similar logic. With that the overall
mark_busy in the core could be removed.
v8: Only when retiring gpu buffers only flush frontbuffer bits we
actually invalidated in a batch. Just for safety since before any
additional usage/invalidate we should always retire current rendering.
Suggested by Chris Wilson.
v9: Actually use intel_frontbuffer_flip in all appropriate places.
Spotted by Chris.
v10: Address more comments from Chris:
- Don't call _flip in set_base when the crtc is inactive, avoids redunancy
in the modeset case with the initial enabling of all planes.
- Add comments explaining that the initial/final plane enable/disable
still has work left to do before it's fully generic.
v11: Only invalidate for gtt/cpu access when writing. Spotted by Chris.
v12: s/_flush/_flip/ in intel_overlay.c per Chris' comment.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-19 22:01:59 +08:00
|
|
|
struct i915_frontbuffer_tracking {
|
2016-08-04 23:32:36 +08:00
|
|
|
spinlock_t lock;
|
drm/i915: Track frontbuffer invalidation/flushing
So these are the guts of the new beast. This tracks when a frontbuffer
gets invalidated (due to frontbuffer rendering) and hence should be
constantly scaned out, and when it's flushed again and can be
compressed/one-shot-upload.
Rules for flushing are simple: The frontbuffer needs one more full
upload starting from the next vblank. Which means that the flushing
can _only_ be called once the frontbuffer update has been latched.
But this poses a problem for pageflips: We can't just delay the
flushing until the pageflip is latched, since that would pose the risk
that we override frontbuffer rendering that has been scheduled
in-between the pageflip ioctl and the actual latching.
To handle this track asynchronous invalidations (and also pageflip)
state per-ring and delay any in-between flushing until the rendering
has completed. And also cancel any delayed flushing if we get a new
invalidation request (whether delayed or not).
Also call intel_mark_fb_busy in both cases in all cases to make sure
that we keep the screen at the highest refresh rate both on flips,
synchronous plane updates and for frontbuffer rendering.
v2: Lots of improvements
Suggestions from Chris:
- Move invalidate/flush in flush_*_domain and set_to_*_domain.
- Drop the flush in busy_ioctl since it's redundant. Was a leftover
from an earlier concept to track flips/delayed flushes.
- Don't forget about the initial modeset enable/final disable.
Suggested by Chris.
Track flips accurately, too. Since flips complete independently of
rendering we need to track pending flips in a separate mask. Again if
an invalidate happens we need to cancel the evenutal flush to avoid
races.
v3:
Provide correct header declarations for flip functions. Currently not
needed outside of intel_display.c, but part of the proper interface.
v4: Add proper domain management to fbcon so that the fbcon buffer is
also tracked correctly.
v5: Fixup locking around the fbcon set_to_gtt_domain call.
v6: More comments from Chris:
- Split out fbcon changes.
- Drop superflous checks for potential scanout before calling intel_fb
functions - we can micro-optimize this later.
- s/intel_fb_/intel_fb_obj_/ to make it clear that this deals in gem
object. We already have precedence for fb_obj in the pin_and_fence
functions.
v7: Clarify the semantics of the flip flush handling by renaming
things a bit:
- Don't go through a gem object but take the relevant frontbuffer bits
directly. These functions center on the plane, the actual object is
irrelevant - even a flip to the same object as already active should
cause a flush.
- Add a new intel_frontbuffer_flip for synchronous plane updates. It
currently just calls intel_frontbuffer_flush since the implemenation
differs.
This way we achieve a clear split between one-shot update events on
one side and frontbuffer rendering with potentially a very long delay
between the invalidate and flush.
Chris and I also had some discussions about mark_busy and whether it
is appropriate to call from flush. But mark busy is a state which
should be derived from the 3 events (invalidate, flush, flip) we now
have by the users, like psr does by tracking relevant information in
psr.busy_frontbuffer_bits. DRRS (the only real use of mark_busy for
frontbuffer) needs to have similar logic. With that the overall
mark_busy in the core could be removed.
v8: Only when retiring gpu buffers only flush frontbuffer bits we
actually invalidated in a batch. Just for safety since before any
additional usage/invalidate we should always retire current rendering.
Suggested by Chris Wilson.
v9: Actually use intel_frontbuffer_flip in all appropriate places.
Spotted by Chris.
v10: Address more comments from Chris:
- Don't call _flip in set_base when the crtc is inactive, avoids redunancy
in the modeset case with the initial enabling of all planes.
- Add comments explaining that the initial/final plane enable/disable
still has work left to do before it's fully generic.
v11: Only invalidate for gtt/cpu access when writing. Spotted by Chris.
v12: s/_flush/_flip/ in intel_overlay.c per Chris' comment.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-19 22:01:59 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Tracking bits for delayed frontbuffer flushing du to gpu activity or
|
|
|
|
* scheduled flips.
|
|
|
|
*/
|
|
|
|
unsigned busy_bits;
|
|
|
|
unsigned flip_bits;
|
|
|
|
};
|
|
|
|
|
2015-02-10 19:05:47 +08:00
|
|
|
struct i915_virtual_gpu {
|
|
|
|
bool active;
|
2017-08-14 15:20:46 +08:00
|
|
|
u32 caps;
|
2015-02-10 19:05:47 +08:00
|
|
|
};
|
|
|
|
|
2015-09-25 06:53:18 +08:00
|
|
|
/* used in computing the new watermarks state */
|
|
|
|
struct intel_wm_config {
|
|
|
|
unsigned int num_pipes_active;
|
|
|
|
bool sprites_enabled;
|
|
|
|
bool sprites_scaled;
|
|
|
|
};
|
|
|
|
|
2016-11-08 03:49:52 +08:00
|
|
|
struct i915_oa_format {
|
|
|
|
u32 format;
|
|
|
|
int size;
|
|
|
|
};
|
|
|
|
|
2016-11-08 03:49:51 +08:00
|
|
|
struct i915_oa_reg {
|
|
|
|
i915_reg_t addr;
|
|
|
|
u32 value;
|
|
|
|
};
|
|
|
|
|
2017-08-04 00:58:08 +08:00
|
|
|
struct i915_oa_config {
|
|
|
|
char uuid[UUID_STRING_LEN + 1];
|
|
|
|
int id;
|
|
|
|
|
|
|
|
const struct i915_oa_reg *mux_regs;
|
|
|
|
u32 mux_regs_len;
|
|
|
|
const struct i915_oa_reg *b_counter_regs;
|
|
|
|
u32 b_counter_regs_len;
|
|
|
|
const struct i915_oa_reg *flex_regs;
|
|
|
|
u32 flex_regs_len;
|
|
|
|
|
|
|
|
struct attribute_group sysfs_metric;
|
|
|
|
struct attribute *attrs[2];
|
|
|
|
struct device_attribute sysfs_metric_id;
|
2017-08-04 01:05:50 +08:00
|
|
|
|
|
|
|
atomic_t ref_count;
|
2017-08-04 00:58:08 +08:00
|
|
|
};
|
|
|
|
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct i915_perf_stream;
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* struct i915_perf_stream_ops - the OPs to support a specific stream type
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct i915_perf_stream_ops {
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @enable: Enables the collection of HW samples, either in response to
|
|
|
|
* `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
|
|
|
|
* without `I915_PERF_FLAG_DISABLED`.
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*/
|
|
|
|
void (*enable)(struct i915_perf_stream *stream);
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @disable: Disables the collection of HW samples, either in response
|
|
|
|
* to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
|
|
|
|
* the stream.
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*/
|
|
|
|
void (*disable)(struct i915_perf_stream *stream);
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @poll_wait: Call poll_wait, passing a wait queue that will be woken
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
* once there is something ready to read() for the stream
|
|
|
|
*/
|
|
|
|
void (*poll_wait)(struct i915_perf_stream *stream,
|
|
|
|
struct file *file,
|
|
|
|
poll_table *wait);
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @wait_unlocked: For handling a blocking read, wait until there is
|
|
|
|
* something to ready to read() for the stream. E.g. wait on the same
|
2016-11-08 03:49:52 +08:00
|
|
|
* wait queue that would be passed to poll_wait().
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*/
|
|
|
|
int (*wait_unlocked)(struct i915_perf_stream *stream);
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @read: Copy buffered metrics as records to userspace
|
|
|
|
* **buf**: the userspace, destination buffer
|
|
|
|
* **count**: the number of bytes to copy, requested by userspace
|
|
|
|
* **offset**: zero at the start of the read, updated as the read
|
|
|
|
* proceeds, it represents how many bytes have been copied so far and
|
|
|
|
* the buffer offset for copying the next record.
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*
|
2016-12-08 05:40:33 +08:00
|
|
|
* Copy as many buffered i915 perf samples and records for this stream
|
|
|
|
* to userspace as will fit in the given buffer.
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*
|
2016-12-08 05:40:33 +08:00
|
|
|
* Only write complete records; returning -%ENOSPC if there isn't room
|
|
|
|
* for a complete record.
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*
|
2016-12-08 05:40:33 +08:00
|
|
|
* Return any error condition that results in a short read such as
|
|
|
|
* -%ENOSPC or -%EFAULT, even though these may be squashed before
|
|
|
|
* returning to userspace.
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*/
|
|
|
|
int (*read)(struct i915_perf_stream *stream,
|
|
|
|
char __user *buf,
|
|
|
|
size_t count,
|
|
|
|
size_t *offset);
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @destroy: Cleanup any stream specific resources.
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
*
|
|
|
|
* The stream will always be disabled before this is called.
|
|
|
|
*/
|
|
|
|
void (*destroy)(struct i915_perf_stream *stream);
|
|
|
|
};
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* struct i915_perf_stream - state for a single open stream FD
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct i915_perf_stream {
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @dev_priv: i915 drm device
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @link: Links the stream into ``&drm_i915_private->streams``
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct list_head link;
|
|
|
|
|
2019-01-15 18:25:05 +08:00
|
|
|
/**
|
|
|
|
* @wakeref: As we keep the device awake while the perf stream is
|
|
|
|
* active, we track our runtime pm reference for later release.
|
|
|
|
*/
|
2019-01-14 22:21:15 +08:00
|
|
|
intel_wakeref_t wakeref;
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
|
|
|
|
* properties given when opening a stream, representing the contents
|
|
|
|
* of a single sample as read() by userspace.
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
u32 sample_flags;
|
2016-12-08 05:40:33 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @sample_size: Considering the configured contents of a sample
|
|
|
|
* combined with the required header size, this is the total size
|
|
|
|
* of a single sample record.
|
|
|
|
*/
|
2016-11-08 03:49:52 +08:00
|
|
|
int sample_size;
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @ctx: %NULL if measuring system-wide across all contexts or a
|
|
|
|
* specific context that is being monitored.
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct i915_gem_context *ctx;
|
2016-12-08 05:40:33 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @enabled: Whether the stream is currently enabled, considering
|
|
|
|
* whether the stream was opened in a disabled state and based
|
|
|
|
* on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
bool enabled;
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* @ops: The callbacks providing the implementation of this specific
|
|
|
|
* type of configured stream.
|
|
|
|
*/
|
2016-11-08 03:49:52 +08:00
|
|
|
const struct i915_perf_stream_ops *ops;
|
2017-08-04 00:58:08 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @oa_config: The OA configuration used by the stream.
|
|
|
|
*/
|
|
|
|
struct i915_oa_config *oa_config;
|
2019-08-07 07:30:02 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* The OA context specific information.
|
|
|
|
*/
|
|
|
|
struct intel_context *pinned_ctx;
|
|
|
|
u32 specific_ctx_id;
|
|
|
|
u32 specific_ctx_id_mask;
|
|
|
|
|
|
|
|
struct hrtimer poll_check_timer;
|
|
|
|
wait_queue_head_t poll_wq;
|
|
|
|
bool pollin;
|
|
|
|
|
|
|
|
bool periodic;
|
|
|
|
int period_exponent;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* State of the OA buffer.
|
|
|
|
*/
|
|
|
|
struct {
|
|
|
|
struct i915_vma *vma;
|
|
|
|
u8 *vaddr;
|
|
|
|
u32 last_ctx_id;
|
|
|
|
int format;
|
|
|
|
int format_size;
|
|
|
|
int size_exponent;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Locks reads and writes to all head/tail state
|
|
|
|
*
|
|
|
|
* Consider: the head and tail pointer state needs to be read
|
|
|
|
* consistently from a hrtimer callback (atomic context) and
|
|
|
|
* read() fop (user context) with tail pointer updates happening
|
|
|
|
* in atomic context and head updates in user context and the
|
|
|
|
* (unlikely) possibility of read() errors needing to reset all
|
|
|
|
* head/tail state.
|
|
|
|
*
|
|
|
|
* Note: Contention/performance aren't currently a significant
|
|
|
|
* concern here considering the relatively low frequency of
|
|
|
|
* hrtimer callbacks (5ms period) and that reads typically only
|
|
|
|
* happen in response to a hrtimer event and likely complete
|
|
|
|
* before the next callback.
|
|
|
|
*
|
|
|
|
* Note: This lock is not held *while* reading and copying data
|
|
|
|
* to userspace so the value of head observed in htrimer
|
|
|
|
* callbacks won't represent any partial consumption of data.
|
|
|
|
*/
|
|
|
|
spinlock_t ptr_lock;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* One 'aging' tail pointer and one 'aged' tail pointer ready to
|
|
|
|
* used for reading.
|
|
|
|
*
|
|
|
|
* Initial values of 0xffffffff are invalid and imply that an
|
|
|
|
* update is required (and should be ignored by an attempted
|
|
|
|
* read)
|
|
|
|
*/
|
|
|
|
struct {
|
|
|
|
u32 offset;
|
|
|
|
} tails[2];
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Index for the aged tail ready to read() data up to.
|
|
|
|
*/
|
|
|
|
unsigned int aged_tail_idx;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* A monotonic timestamp for when the current aging tail pointer
|
|
|
|
* was read; used to determine when it is old enough to trust.
|
|
|
|
*/
|
|
|
|
u64 aging_timestamp;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Although we can always read back the head pointer register,
|
|
|
|
* we prefer to avoid trusting the HW state, just to avoid any
|
|
|
|
* risk that some hardware condition could * somehow bump the
|
|
|
|
* head pointer unpredictably and cause us to forward the wrong
|
|
|
|
* OA buffer data to userspace.
|
|
|
|
*/
|
|
|
|
u32 head;
|
|
|
|
} oa_buffer;
|
2016-11-08 03:49:52 +08:00
|
|
|
};
|
|
|
|
|
2016-12-08 05:40:33 +08:00
|
|
|
/**
|
|
|
|
* struct i915_oa_ops - Gen specific implementation of an OA unit stream
|
|
|
|
*/
|
2016-11-08 03:49:52 +08:00
|
|
|
struct i915_oa_ops {
|
2017-08-04 01:05:50 +08:00
|
|
|
/**
|
|
|
|
* @is_valid_b_counter_reg: Validates register's address for
|
|
|
|
* programming boolean counters for a particular platform.
|
|
|
|
*/
|
|
|
|
bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
|
|
|
|
u32 addr);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @is_valid_mux_reg: Validates register's address for programming mux
|
|
|
|
* for a particular platform.
|
|
|
|
*/
|
|
|
|
bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @is_valid_flex_reg: Validates register's address for programming
|
|
|
|
* flex EU filtering for a particular platform.
|
|
|
|
*/
|
|
|
|
bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
|
|
|
|
|
2017-06-13 19:23:03 +08:00
|
|
|
/**
|
|
|
|
* @enable_metric_set: Selects and applies any MUX configuration to set
|
|
|
|
* up the Boolean and Custom (B/C) counters that are part of the
|
|
|
|
* counter reports being sampled. May apply system constraints such as
|
2016-12-08 05:40:33 +08:00
|
|
|
* disabling EU clock gating as required.
|
|
|
|
*/
|
2018-10-23 18:07:06 +08:00
|
|
|
int (*enable_metric_set)(struct i915_perf_stream *stream);
|
2016-12-08 05:40:33 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @disable_metric_set: Remove system constraints associated with using
|
|
|
|
* the OA unit.
|
|
|
|
*/
|
2019-08-07 07:30:02 +08:00
|
|
|
void (*disable_metric_set)(struct i915_perf_stream *stream);
|
2016-12-08 05:40:33 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @oa_enable: Enable periodic sampling
|
|
|
|
*/
|
2018-10-23 18:07:06 +08:00
|
|
|
void (*oa_enable)(struct i915_perf_stream *stream);
|
2016-12-08 05:40:33 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @oa_disable: Disable periodic sampling
|
|
|
|
*/
|
2018-10-23 18:07:06 +08:00
|
|
|
void (*oa_disable)(struct i915_perf_stream *stream);
|
2016-12-08 05:40:33 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @read: Copy data from the circular OA buffer into a given userspace
|
|
|
|
* buffer.
|
|
|
|
*/
|
2016-11-08 03:49:52 +08:00
|
|
|
int (*read)(struct i915_perf_stream *stream,
|
|
|
|
char __user *buf,
|
|
|
|
size_t count,
|
|
|
|
size_t *offset);
|
2016-12-08 05:40:33 +08:00
|
|
|
|
|
|
|
/**
|
2017-06-13 19:23:03 +08:00
|
|
|
* @oa_hw_tail_read: read the OA tail pointer register
|
2016-12-08 05:40:33 +08:00
|
|
|
*
|
2017-06-13 19:23:03 +08:00
|
|
|
* In particular this enables us to share all the fiddly code for
|
|
|
|
* handling the OA unit tail pointer race that affects multiple
|
|
|
|
* generations.
|
2016-12-08 05:40:33 +08:00
|
|
|
*/
|
2019-08-07 07:30:02 +08:00
|
|
|
u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
};
|
|
|
|
|
2017-02-08 02:33:45 +08:00
|
|
|
struct intel_cdclk_state {
|
2018-01-18 01:25:08 +08:00
|
|
|
unsigned int cdclk, vco, ref, bypass;
|
2017-10-24 17:52:08 +08:00
|
|
|
u8 voltage_level;
|
2017-02-08 02:33:45 +08:00
|
|
|
};
|
|
|
|
|
2014-03-31 19:27:22 +08:00
|
|
|
struct drm_i915_private {
|
2016-06-24 21:00:18 +08:00
|
|
|
struct drm_device drm;
|
|
|
|
|
2018-12-31 22:56:46 +08:00
|
|
|
const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
|
2018-12-31 22:56:41 +08:00
|
|
|
struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
|
2018-02-08 05:05:43 +08:00
|
|
|
struct intel_driver_caps caps;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
2017-12-11 23:18:18 +08:00
|
|
|
/**
|
|
|
|
* Data Stolen Memory - aka "i915 stolen memory" gives us the start and
|
|
|
|
* end of stolen which we can optionally use to create GEM objects
|
2017-12-11 23:18:21 +08:00
|
|
|
* backed by stolen memory. Note that stolen_usable_size tells us
|
2017-12-11 23:18:18 +08:00
|
|
|
* exactly how much of this we are actually allowed to use, given that
|
|
|
|
* some portion of it is in fact reserved for use by hardware functions.
|
|
|
|
*/
|
|
|
|
struct resource dsm;
|
2017-12-11 23:18:19 +08:00
|
|
|
/**
|
|
|
|
* Reseved portion of Data Stolen Memory
|
|
|
|
*/
|
|
|
|
struct resource dsm_reserved;
|
2017-12-11 23:18:18 +08:00
|
|
|
|
2017-12-11 23:18:21 +08:00
|
|
|
/*
|
|
|
|
* Stolen memory is segmented in hardware with different portions
|
|
|
|
* offlimits to certain functions.
|
|
|
|
*
|
|
|
|
* The drm_mm is initialised to the total accessible range, as found
|
|
|
|
* from the PCI config. On Broadwell+, this is further restricted to
|
|
|
|
* avoid the first page! The upper end of stolen memory is reserved for
|
|
|
|
* hardware functions and similarly removed from the accessible range.
|
|
|
|
*/
|
2017-12-11 23:18:22 +08:00
|
|
|
resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
|
2017-12-11 23:18:21 +08:00
|
|
|
|
2013-07-20 03:36:52 +08:00
|
|
|
struct intel_uncore uncore;
|
2019-08-09 14:31:16 +08:00
|
|
|
struct intel_uncore_mmio_debug mmio_debug;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
2015-02-10 19:05:47 +08:00
|
|
|
struct i915_virtual_gpu vgpu;
|
|
|
|
|
2016-10-20 17:15:03 +08:00
|
|
|
struct intel_gvt *gvt;
|
drm/i915: gvt: Introduce the basic architecture of GVT-g
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v12:
- Call intel_gvt_init() in driver early initialization stage. (Chris)
v8:
- Remove the GVT idr and mutex in intel_gvt_host. (Joonas)
v7:
- Refine the URL link in Kconfig. (Joonas)
- Refine the introduction of GVT-g host support in Kconfig. (Joonas)
- Remove the macro GVT_ALIGN(), use round_down() instead. (Joonas)
- Make "struct intel_gvt" a data member in struct drm_i915_private.(Joonas)
- Remove {alloc, free}_gvt_device()
- Rename intel_gvt_{create, destroy}_gvt_device()
- Expost intel_gvt_init_host()
- Remove the dummy "struct intel_gvt" declaration in intel_gvt.h (Joonas)
v6:
- Refine introduction in Kconfig. (Chris)
- The exposed API functions will take struct intel_gvt * instead of
void *. (Chris/Tvrtko)
- Remove most memebers of strct intel_gvt_device_info. Will add them
in the device model patches.(Chris)
- Remove gvt_info() and gvt_err() in debug.h. (Chris)
- Move GVT kernel parameter into i915_params. (Chris)
- Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
- Remove the redundant struct i915_gvt *, as the functions in i915
will directly take struct intel_gvt *.
- Add more comments for reviewer.
v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfig
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization
v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.
Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.
Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-5-git-send-email-zhi.a.wang@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-16 20:07:00 +08:00
|
|
|
|
2018-03-14 08:32:50 +08:00
|
|
|
struct intel_wopcm wopcm;
|
|
|
|
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 20:58:44 +08:00
|
|
|
struct intel_csr csr;
|
|
|
|
|
2015-04-01 15:55:04 +08:00
|
|
|
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
|
2012-12-01 20:53:45 +08:00
|
|
|
|
2012-11-03 02:55:02 +08:00
|
|
|
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
|
|
|
|
* controller on different i2c buses. */
|
|
|
|
struct mutex gmbus_mutex;
|
|
|
|
|
|
|
|
/**
|
2018-07-28 03:36:47 +08:00
|
|
|
* Base address of where the gmbus and gpio blocks are located (either
|
|
|
|
* on PCH or on SoC for platforms without PCH).
|
2012-11-03 02:55:02 +08:00
|
|
|
*/
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 gpio_mmio_base;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
2014-05-19 23:24:03 +08:00
|
|
|
/* MMIO base address for MIPI regs */
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 mipi_mmio_base;
|
2014-05-19 23:24:03 +08:00
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 psr_mmio_base;
|
2015-11-12 02:34:15 +08:00
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 pps_mmio_base;
|
2016-08-10 19:07:29 +08:00
|
|
|
|
2012-12-01 20:53:45 +08:00
|
|
|
wait_queue_head_t gmbus_wait_queue;
|
|
|
|
|
2012-11-03 02:55:02 +08:00
|
|
|
struct pci_dev *bridge_dev;
|
2019-08-06 20:43:00 +08:00
|
|
|
|
2017-10-04 04:34:48 +08:00
|
|
|
/* Context used internally to idle the GPU and setup initial state */
|
|
|
|
struct i915_gem_context *kernel_context;
|
2019-08-06 20:43:00 +08:00
|
|
|
|
|
|
|
struct intel_engine_cs *engine[I915_NUM_ENGINES];
|
|
|
|
struct rb_root uabi_engines;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
|
|
|
struct resource mch_res;
|
|
|
|
|
|
|
|
/* protects the irq masks */
|
|
|
|
spinlock_t irq_lock;
|
|
|
|
|
2014-03-05 01:23:07 +08:00
|
|
|
bool display_irqs_enabled;
|
|
|
|
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
|
|
|
|
struct pm_qos_request pm_qos;
|
|
|
|
|
2015-05-27 01:42:30 +08:00
|
|
|
/* Sideband mailbox protection */
|
|
|
|
struct mutex sb_lock;
|
2019-04-26 16:17:18 +08:00
|
|
|
struct pm_qos_request sb_qos;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
|
|
|
/** Cached value of IMR to avoid reads in updating the bitfield */
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 12:07:09 +08:00
|
|
|
union {
|
|
|
|
u32 irq_mask;
|
|
|
|
u32 de_irq_mask[I915_MAX_PIPES];
|
|
|
|
};
|
2014-03-15 22:53:22 +08:00
|
|
|
u32 pm_rps_events;
|
2014-02-11 00:42:49 +08:00
|
|
|
u32 pipestat_irq_mask[I915_MAX_PIPES];
|
2012-11-03 02:55:02 +08:00
|
|
|
|
2015-05-27 20:03:42 +08:00
|
|
|
struct i915_hotplug hotplug;
|
2016-01-12 03:44:36 +08:00
|
|
|
struct intel_fbc fbc;
|
2014-04-05 14:43:28 +08:00
|
|
|
struct i915_drrs drrs;
|
2012-11-03 02:55:02 +08:00
|
|
|
struct intel_opregion opregion;
|
2013-05-10 07:03:18 +08:00
|
|
|
struct intel_vbt_data vbt;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
2014-10-10 03:57:43 +08:00
|
|
|
bool preserve_bios_swizzle;
|
|
|
|
|
2012-11-03 02:55:02 +08:00
|
|
|
/* overlay */
|
|
|
|
struct intel_overlay *overlay;
|
|
|
|
|
2013-11-08 22:48:54 +08:00
|
|
|
/* backlight registers and fields in struct intel_panel */
|
2014-09-15 20:35:09 +08:00
|
|
|
struct mutex backlight_lock;
|
2013-04-02 20:48:09 +08:00
|
|
|
|
2014-09-04 19:53:14 +08:00
|
|
|
/* protects panel power sequencer state */
|
|
|
|
struct mutex pps_mutex;
|
|
|
|
|
2012-11-03 02:55:02 +08:00
|
|
|
unsigned int fsb_freq, mem_freq, is_ddr3;
|
2016-05-14 04:41:27 +08:00
|
|
|
unsigned int skl_preferred_vco_freq;
|
2017-02-08 02:33:45 +08:00
|
|
|
unsigned int max_cdclk_freq;
|
2016-11-15 00:35:10 +08:00
|
|
|
|
2015-08-18 19:36:59 +08:00
|
|
|
unsigned int max_dotclk_freq;
|
2016-03-02 23:22:13 +08:00
|
|
|
unsigned int rawclk_freq;
|
2014-10-07 22:41:22 +08:00
|
|
|
unsigned int hpll_freq;
|
2017-11-05 21:49:05 +08:00
|
|
|
unsigned int fdi_pll_freq;
|
2015-09-25 04:29:18 +08:00
|
|
|
unsigned int czclk_freq;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
2016-05-14 04:41:32 +08:00
|
|
|
struct {
|
2017-01-21 02:21:59 +08:00
|
|
|
/*
|
|
|
|
* The current logical cdclk state.
|
|
|
|
* See intel_atomic_state.cdclk.logical
|
|
|
|
*
|
|
|
|
* For reading holding any crtc lock is sufficient,
|
|
|
|
* for writing must hold all of them.
|
|
|
|
*/
|
|
|
|
struct intel_cdclk_state logical;
|
|
|
|
/*
|
|
|
|
* The current actual cdclk state.
|
|
|
|
* See intel_atomic_state.cdclk.actual
|
|
|
|
*/
|
|
|
|
struct intel_cdclk_state actual;
|
|
|
|
/* The current hardware cdclk state */
|
2017-02-08 02:33:45 +08:00
|
|
|
struct intel_cdclk_state hw;
|
2019-03-20 21:54:36 +08:00
|
|
|
|
|
|
|
int force_min_cdclk;
|
2017-02-08 02:33:45 +08:00
|
|
|
} cdclk;
|
2016-05-14 04:41:32 +08:00
|
|
|
|
2013-09-02 22:22:25 +08:00
|
|
|
/**
|
|
|
|
* wq - Driver workqueue for GEM.
|
|
|
|
*
|
|
|
|
* NOTE: Work items scheduled here are not allowed to grab any modeset
|
|
|
|
* locks, for otherwise the flushing done in the pageflip code will
|
|
|
|
* result in deadlocks.
|
|
|
|
*/
|
2012-11-03 02:55:02 +08:00
|
|
|
struct workqueue_struct *wq;
|
|
|
|
|
2017-11-13 21:36:22 +08:00
|
|
|
/* ordered wq for modesets */
|
|
|
|
struct workqueue_struct *modeset_wq;
|
|
|
|
|
2012-11-03 02:55:02 +08:00
|
|
|
/* Display functions */
|
|
|
|
struct drm_i915_display_funcs display;
|
|
|
|
|
|
|
|
/* PCH chipset type */
|
|
|
|
enum intel_pch pch_type;
|
2012-11-21 01:12:07 +08:00
|
|
|
unsigned short pch_id;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
|
|
|
unsigned long quirks;
|
|
|
|
|
2016-02-16 17:06:14 +08:00
|
|
|
struct drm_atomic_state *modeset_restore_state;
|
2016-08-06 04:28:27 +08:00
|
|
|
struct drm_modeset_acquire_ctx reset_ctx;
|
2008-07-31 03:06:12 +08:00
|
|
|
|
2016-03-18 16:42:57 +08:00
|
|
|
struct i915_ggtt ggtt; /* VM representing the global address space */
|
2013-01-18 04:45:15 +08:00
|
|
|
|
2012-11-15 00:14:03 +08:00
|
|
|
struct i915_gem_mm mm;
|
2014-08-07 21:20:40 +08:00
|
|
|
DECLARE_HASHTABLE(mm_structs, 7);
|
|
|
|
struct mutex mm_lock;
|
2012-05-02 17:49:32 +08:00
|
|
|
|
|
|
|
/* Kernel Modesetting */
|
|
|
|
|
2016-11-01 04:37:05 +08:00
|
|
|
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
|
|
|
|
struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
|
2009-11-19 00:25:18 +08:00
|
|
|
|
2013-10-22 03:04:07 +08:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
|
|
|
|
#endif
|
|
|
|
|
2015-12-10 19:33:57 +08:00
|
|
|
/* dpll and cdclk state is protected by connection_mutex */
|
2013-06-05 19:34:06 +08:00
|
|
|
int num_shared_dpll;
|
|
|
|
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
|
2016-03-08 23:46:22 +08:00
|
|
|
const struct intel_dpll_mgr *dpll_mgr;
|
2015-12-10 19:33:57 +08:00
|
|
|
|
2016-03-23 21:51:12 +08:00
|
|
|
/*
|
|
|
|
* dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
|
|
|
|
* Must be global rather than per dpll, because on some platforms
|
|
|
|
* plls share registers.
|
|
|
|
*/
|
|
|
|
struct mutex dpll_lock;
|
|
|
|
|
2015-12-10 19:33:57 +08:00
|
|
|
unsigned int active_crtcs;
|
2017-08-31 02:57:03 +08:00
|
|
|
/* minimum acceptable cdclk for each pipe */
|
|
|
|
int min_cdclk[I915_MAX_PIPES];
|
2017-10-24 17:52:14 +08:00
|
|
|
/* minimum acceptable voltage level for each pipe */
|
|
|
|
u8 min_voltage_level[I915_MAX_PIPES];
|
2015-12-10 19:33:57 +08:00
|
|
|
|
2013-11-06 14:36:35 +08:00
|
|
|
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
|
2012-04-21 00:11:53 +08:00
|
|
|
|
2018-12-03 21:33:19 +08:00
|
|
|
struct i915_wa_list gt_wa_list;
|
2014-08-26 21:44:51 +08:00
|
|
|
|
drm/i915: Track frontbuffer invalidation/flushing
So these are the guts of the new beast. This tracks when a frontbuffer
gets invalidated (due to frontbuffer rendering) and hence should be
constantly scaned out, and when it's flushed again and can be
compressed/one-shot-upload.
Rules for flushing are simple: The frontbuffer needs one more full
upload starting from the next vblank. Which means that the flushing
can _only_ be called once the frontbuffer update has been latched.
But this poses a problem for pageflips: We can't just delay the
flushing until the pageflip is latched, since that would pose the risk
that we override frontbuffer rendering that has been scheduled
in-between the pageflip ioctl and the actual latching.
To handle this track asynchronous invalidations (and also pageflip)
state per-ring and delay any in-between flushing until the rendering
has completed. And also cancel any delayed flushing if we get a new
invalidation request (whether delayed or not).
Also call intel_mark_fb_busy in both cases in all cases to make sure
that we keep the screen at the highest refresh rate both on flips,
synchronous plane updates and for frontbuffer rendering.
v2: Lots of improvements
Suggestions from Chris:
- Move invalidate/flush in flush_*_domain and set_to_*_domain.
- Drop the flush in busy_ioctl since it's redundant. Was a leftover
from an earlier concept to track flips/delayed flushes.
- Don't forget about the initial modeset enable/final disable.
Suggested by Chris.
Track flips accurately, too. Since flips complete independently of
rendering we need to track pending flips in a separate mask. Again if
an invalidate happens we need to cancel the evenutal flush to avoid
races.
v3:
Provide correct header declarations for flip functions. Currently not
needed outside of intel_display.c, but part of the proper interface.
v4: Add proper domain management to fbcon so that the fbcon buffer is
also tracked correctly.
v5: Fixup locking around the fbcon set_to_gtt_domain call.
v6: More comments from Chris:
- Split out fbcon changes.
- Drop superflous checks for potential scanout before calling intel_fb
functions - we can micro-optimize this later.
- s/intel_fb_/intel_fb_obj_/ to make it clear that this deals in gem
object. We already have precedence for fb_obj in the pin_and_fence
functions.
v7: Clarify the semantics of the flip flush handling by renaming
things a bit:
- Don't go through a gem object but take the relevant frontbuffer bits
directly. These functions center on the plane, the actual object is
irrelevant - even a flip to the same object as already active should
cause a flush.
- Add a new intel_frontbuffer_flip for synchronous plane updates. It
currently just calls intel_frontbuffer_flush since the implemenation
differs.
This way we achieve a clear split between one-shot update events on
one side and frontbuffer rendering with potentially a very long delay
between the invalidate and flush.
Chris and I also had some discussions about mark_busy and whether it
is appropriate to call from flush. But mark busy is a state which
should be derived from the 3 events (invalidate, flush, flip) we now
have by the users, like psr does by tracking relevant information in
psr.busy_frontbuffer_bits. DRRS (the only real use of mark_busy for
frontbuffer) needs to have similar logic. With that the overall
mark_busy in the core could be removed.
v8: Only when retiring gpu buffers only flush frontbuffer bits we
actually invalidated in a batch. Just for safety since before any
additional usage/invalidate we should always retire current rendering.
Suggested by Chris Wilson.
v9: Actually use intel_frontbuffer_flip in all appropriate places.
Spotted by Chris.
v10: Address more comments from Chris:
- Don't call _flip in set_base when the crtc is inactive, avoids redunancy
in the modeset case with the initial enabling of all planes.
- Add comments explaining that the initial/final plane enable/disable
still has work left to do before it's fully generic.
v11: Only invalidate for gtt/cpu access when writing. Spotted by Chris.
v12: s/_flush/_flip/ in intel_overlay.c per Chris' comment.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-19 22:01:59 +08:00
|
|
|
struct i915_frontbuffer_tracking fb_tracking;
|
|
|
|
|
2017-01-24 05:29:39 +08:00
|
|
|
struct intel_atomic_helper {
|
|
|
|
struct llist_head free_list;
|
|
|
|
struct work_struct free_work;
|
|
|
|
} atomic_helper;
|
|
|
|
|
2009-08-18 04:31:43 +08:00
|
|
|
u16 orig_clock;
|
2010-01-30 03:27:07 +08:00
|
|
|
|
2009-12-17 14:48:43 +08:00
|
|
|
bool mchbar_need_disable;
|
2010-01-30 03:27:07 +08:00
|
|
|
|
2012-11-03 02:55:07 +08:00
|
|
|
struct intel_l3_parity l3_parity;
|
|
|
|
|
2019-03-29 01:45:32 +08:00
|
|
|
/*
|
|
|
|
* edram size in MB.
|
|
|
|
* Cannot be determined by PCIID. You must always read a register.
|
|
|
|
*/
|
|
|
|
u32 edram_size_mb;
|
2013-07-05 02:02:05 +08:00
|
|
|
|
2017-10-11 05:30:06 +08:00
|
|
|
/* gen6+ GT PM state */
|
|
|
|
struct intel_gen6_power_mgmt gt_pm;
|
2012-08-09 05:35:35 +08:00
|
|
|
|
2012-08-09 05:35:39 +08:00
|
|
|
/* ilk-only ips/rps state. Everything in here is protected by the global
|
|
|
|
* mchdev_lock in intel_pm.c */
|
2012-11-03 02:55:03 +08:00
|
|
|
struct intel_ilk_power_mgmt ips;
|
2010-02-06 04:42:41 +08:00
|
|
|
|
2013-10-25 22:36:47 +08:00
|
|
|
struct i915_power_domains power_domains;
|
2013-05-30 22:07:11 +08:00
|
|
|
|
2013-10-04 03:15:06 +08:00
|
|
|
struct i915_psr psr;
|
2013-07-12 05:45:00 +08:00
|
|
|
|
2012-11-15 00:14:04 +08:00
|
|
|
struct i915_gpu_error gpu_error;
|
2010-10-01 21:57:56 +08:00
|
|
|
|
2013-05-09 01:45:13 +08:00
|
|
|
struct drm_i915_gem_object *vlv_pctx;
|
|
|
|
|
2010-03-30 13:34:14 +08:00
|
|
|
/* list of fbdev register on this device */
|
|
|
|
struct intel_fbdev *fbdev;
|
2014-08-13 20:09:46 +08:00
|
|
|
struct work_struct fbdev_suspend_work;
|
2011-02-22 06:23:52 +08:00
|
|
|
|
|
|
|
struct drm_property *broadcast_rgb_property;
|
2011-05-13 05:17:24 +08:00
|
|
|
struct drm_property *force_audio_property;
|
2012-05-26 07:56:22 +08:00
|
|
|
|
2015-01-08 23:54:14 +08:00
|
|
|
/* hda/i915 audio component */
|
2015-08-19 16:48:56 +08:00
|
|
|
struct i915_audio_component *audio_component;
|
2015-01-08 23:54:14 +08:00
|
|
|
bool audio_component_registered;
|
2015-09-02 14:11:39 +08:00
|
|
|
/**
|
|
|
|
* av_mutex - mutex for audio/video sync
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
struct mutex av_mutex;
|
2019-03-20 21:54:36 +08:00
|
|
|
int audio_power_refcount;
|
2015-01-08 23:54:14 +08:00
|
|
|
|
2017-06-20 19:05:45 +08:00
|
|
|
struct {
|
2018-09-04 23:31:17 +08:00
|
|
|
struct mutex mutex;
|
2017-06-20 19:05:45 +08:00
|
|
|
struct list_head list;
|
2017-06-20 19:05:46 +08:00
|
|
|
struct llist_head free_list;
|
|
|
|
struct work_struct free_work;
|
2017-06-20 19:05:45 +08:00
|
|
|
|
|
|
|
/* The hw wants to have a stable context identifier for the
|
|
|
|
* lifetime of the context (for OA, PASID, faults, etc).
|
|
|
|
* This is limited in execlists to 21 bits.
|
|
|
|
*/
|
|
|
|
struct ida hw_ida;
|
|
|
|
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
|
2018-06-02 19:29:45 +08:00
|
|
|
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
|
2018-03-03 00:14:58 +08:00
|
|
|
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
|
2018-09-04 23:31:17 +08:00
|
|
|
struct list_head hw_id_list;
|
2017-06-20 19:05:45 +08:00
|
|
|
} contexts;
|
2012-11-03 02:55:02 +08:00
|
|
|
|
2012-12-12 02:48:29 +08:00
|
|
|
u32 fdi_rx_config;
|
2012-12-01 22:04:26 +08:00
|
|
|
|
2016-03-15 22:39:56 +08:00
|
|
|
/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
|
2015-04-10 23:21:28 +08:00
|
|
|
u32 chv_phy_control;
|
2016-03-15 22:39:56 +08:00
|
|
|
/*
|
|
|
|
* Shadows for CHV DPLL_MD regs to keep the state
|
|
|
|
* checker somewhat working in the presence hardware
|
|
|
|
* crappiness (can't read out DPLL_MD for pipes B & C).
|
|
|
|
*/
|
|
|
|
u32 chv_dpll_md[I915_MAX_PIPES];
|
2016-04-04 22:27:10 +08:00
|
|
|
u32 bxt_phy_grc;
|
2015-04-10 23:21:28 +08:00
|
|
|
|
2014-03-10 17:01:44 +08:00
|
|
|
u32 suspend_count;
|
2018-03-22 22:36:42 +08:00
|
|
|
bool power_domains_suspended;
|
2012-11-03 02:55:02 +08:00
|
|
|
struct i915_suspend_saved_registers regfile;
|
2014-05-05 20:19:56 +08:00
|
|
|
struct vlv_s0ix_state vlv_s0ix_state;
|
2012-11-03 02:55:05 +08:00
|
|
|
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-18 03:55:54 +08:00
|
|
|
enum {
|
2016-09-23 05:00:27 +08:00
|
|
|
I915_SAGV_UNKNOWN = 0,
|
|
|
|
I915_SAGV_DISABLED,
|
|
|
|
I915_SAGV_ENABLED,
|
|
|
|
I915_SAGV_NOT_CONTROLLED
|
|
|
|
} sagv_status;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-18 03:55:54 +08:00
|
|
|
|
2013-08-01 21:18:50 +08:00
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* Raw watermark latency values:
|
|
|
|
* in 0.1us units for WM0,
|
|
|
|
* in 0.5us units for WM1+.
|
|
|
|
*/
|
|
|
|
/* primary */
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 pri_latency[5];
|
2013-08-01 21:18:50 +08:00
|
|
|
/* sprite */
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 spr_latency[5];
|
2013-08-01 21:18:50 +08:00
|
|
|
/* cursor */
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 cur_latency[5];
|
2014-11-05 01:06:38 +08:00
|
|
|
/*
|
|
|
|
* Raw watermark memory latency values
|
|
|
|
* for SKL for all 8 levels
|
|
|
|
* in 1us units.
|
|
|
|
*/
|
2019-01-18 20:01:24 +08:00
|
|
|
u16 skl_latency[8];
|
2013-10-10 00:18:03 +08:00
|
|
|
|
|
|
|
/* current hardware state */
|
2014-11-05 01:06:42 +08:00
|
|
|
union {
|
|
|
|
struct ilk_wm_values hw;
|
2018-04-09 11:41:00 +08:00
|
|
|
struct skl_ddb_values skl_hw;
|
2015-03-06 03:19:45 +08:00
|
|
|
struct vlv_wm_values vlv;
|
2017-04-22 02:14:29 +08:00
|
|
|
struct g4x_wm_values g4x;
|
2014-11-05 01:06:42 +08:00
|
|
|
};
|
2015-09-09 02:05:12 +08:00
|
|
|
|
2019-01-18 20:01:24 +08:00
|
|
|
u8 max_level;
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 09:20:13 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Should be held around atomic WM register writing; also
|
|
|
|
* protects * intel_crtc->wm.active and
|
2019-06-28 16:55:17 +08:00
|
|
|
* crtc_state->wm.need_postvbl_update.
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 09:20:13 +08:00
|
|
|
*/
|
|
|
|
struct mutex wm_mutex;
|
2016-05-12 22:06:02 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set during HW readout of watermarks/DDB. Some platforms
|
|
|
|
* need to know when we're still using BIOS-provided values
|
|
|
|
* (which we don't fully trust).
|
|
|
|
*/
|
|
|
|
bool distrust_bios_wm;
|
2013-08-01 21:18:50 +08:00
|
|
|
} wm;
|
|
|
|
|
2018-08-24 17:32:21 +08:00
|
|
|
struct dram_info {
|
|
|
|
bool valid;
|
2018-08-31 19:09:42 +08:00
|
|
|
bool is_16gb_dimm;
|
2018-08-24 17:32:21 +08:00
|
|
|
u8 num_channels;
|
2019-03-07 04:35:40 +08:00
|
|
|
u8 ranks;
|
2018-08-24 17:32:21 +08:00
|
|
|
u32 bandwidth_kbps;
|
2018-08-24 17:32:25 +08:00
|
|
|
bool symmetric_memory;
|
2019-03-07 04:35:51 +08:00
|
|
|
enum intel_dram_type {
|
|
|
|
INTEL_DRAM_UNKNOWN,
|
|
|
|
INTEL_DRAM_DDR3,
|
|
|
|
INTEL_DRAM_DDR4,
|
|
|
|
INTEL_DRAM_LPDDR3,
|
|
|
|
INTEL_DRAM_LPDDR4
|
|
|
|
} type;
|
2018-08-24 17:32:21 +08:00
|
|
|
} dram_info;
|
|
|
|
|
2019-05-24 23:36:14 +08:00
|
|
|
struct intel_bw_info {
|
2019-06-06 20:42:10 +08:00
|
|
|
unsigned int deratedbw[3]; /* for each QGV point */
|
|
|
|
u8 num_qgv_points;
|
|
|
|
u8 num_planes;
|
2019-05-24 23:36:14 +08:00
|
|
|
} max_bw[6];
|
|
|
|
|
|
|
|
struct drm_private_obj bw_obj;
|
|
|
|
|
2019-06-14 07:21:52 +08:00
|
|
|
struct intel_runtime_pm runtime_pm;
|
2013-12-07 06:32:13 +08:00
|
|
|
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct {
|
|
|
|
bool initialized;
|
2016-11-08 03:49:52 +08:00
|
|
|
|
2016-11-08 03:49:53 +08:00
|
|
|
struct kobject *metrics_kobj;
|
2016-11-08 03:49:54 +08:00
|
|
|
struct ctl_table_header *sysctl_header;
|
2016-11-08 03:49:53 +08:00
|
|
|
|
2017-08-04 01:05:50 +08:00
|
|
|
/*
|
|
|
|
* Lock associated with adding/modifying/removing OA configs
|
|
|
|
* in dev_priv->perf.metrics_idr.
|
|
|
|
*/
|
|
|
|
struct mutex metrics_lock;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* List of dynamic configurations, you need to hold
|
|
|
|
* dev_priv->perf.metrics_lock to access it.
|
|
|
|
*/
|
|
|
|
struct idr metrics_idr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Lock associated with anything below within this structure
|
|
|
|
* except exclusive_stream.
|
|
|
|
*/
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
struct mutex lock;
|
|
|
|
struct list_head streams;
|
2016-11-08 03:49:51 +08:00
|
|
|
|
2019-08-07 07:30:02 +08:00
|
|
|
/*
|
|
|
|
* The stream currently using the OA unit. If accessed
|
|
|
|
* outside a syscall associated to its file
|
|
|
|
* descriptor, you need to hold
|
|
|
|
* dev_priv->drm.struct_mutex.
|
|
|
|
*/
|
|
|
|
struct i915_perf_stream *exclusive_stream;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* For rate limiting any notifications of spurious
|
|
|
|
* invalid OA reports
|
|
|
|
*/
|
|
|
|
struct ratelimit_state spurious_report_rs;
|
2016-11-08 03:49:52 +08:00
|
|
|
|
2019-08-07 07:30:02 +08:00
|
|
|
struct i915_oa_config test_config;
|
2016-11-08 03:49:52 +08:00
|
|
|
|
2019-08-07 07:30:02 +08:00
|
|
|
u32 gen7_latched_oastatus1;
|
|
|
|
u32 ctx_oactxctrl_offset;
|
|
|
|
u32 ctx_flexeu0_offset;
|
2016-11-08 03:49:52 +08:00
|
|
|
|
2019-08-07 07:30:02 +08:00
|
|
|
/**
|
|
|
|
* The RPT_ID/reason field for Gen8+ includes a bit
|
|
|
|
* to determine if the CTX ID in the report is valid
|
|
|
|
* but the specific bit differs between Gen 8 and 9
|
|
|
|
*/
|
|
|
|
u32 gen8_valid_ctx_bit;
|
2016-11-08 03:49:52 +08:00
|
|
|
|
2019-08-07 07:30:02 +08:00
|
|
|
struct i915_oa_ops ops;
|
|
|
|
const struct i915_oa_format *oa_formats;
|
drm/i915: Add i915 perf infrastructure
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl() to enable or disable capture and poll() to wait for
data.
A stream is opened something like:
uint64_t properties[] = {
/* Single context sampling */
DRM_I915_PERF_PROP_CTX_HANDLE, ctx_handle,
/* Include OA reports in samples */
DRM_I915_PERF_PROP_SAMPLE_OA, true,
/* OA unit configuration */
DRM_I915_PERF_PROP_OA_METRICS_SET, metrics_set_id,
DRM_I915_PERF_PROP_OA_FORMAT, report_format,
DRM_I915_PERF_PROP_OA_EXPONENT, period_exponent,
};
struct drm_i915_perf_open_param parm = {
.flags = I915_PERF_FLAG_FD_CLOEXEC |
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
.properties_ptr = (uint64_t)properties,
.num_properties = sizeof(properties) / 16,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
Records read all start with a common { type, size } header with
DRM_I915_PERF_RECORD_SAMPLE being of most interest. Sample records
contain an extensible number of fields and it's the
DRM_I915_PERF_PROP_SAMPLE_xyz properties given when opening that
determine what's included in every sample.
No specific streams are supported yet so any attempt to open a stream
will return an error.
v2:
use i915_gem_context_get() - Chris Wilson
v3:
update read() interface to avoid passing state struct - Chris Wilson
fix some rebase fallout, with i915-perf init/deinit
v4:
s/DRM_IORW/DRM_IOW/ - Emil Velikov
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161107194957.3385-2-robert@sixbynine.org
2016-11-08 03:49:47 +08:00
|
|
|
} perf;
|
|
|
|
|
2014-07-25 00:04:21 +08:00
|
|
|
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
|
2019-06-21 15:07:40 +08:00
|
|
|
struct intel_gt gt;
|
2019-04-25 04:07:14 +08:00
|
|
|
|
|
|
|
struct {
|
drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-25 04:07:17 +08:00
|
|
|
struct notifier_block pm_notifier;
|
|
|
|
|
2016-07-04 15:08:31 +08:00
|
|
|
/**
|
|
|
|
* We leave the user IRQ off as much as possible,
|
|
|
|
* but this means that requests will finish and never
|
|
|
|
* be retired once the system goes idle. Set a timer to
|
|
|
|
* fire periodically while the ring is running. When it
|
|
|
|
* fires, go retire requests.
|
|
|
|
*/
|
|
|
|
struct delayed_work retire_work;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* When we detect an idle GPU, we want to turn on
|
|
|
|
* powersaving features. So once we see that there
|
|
|
|
* are no more requests outstanding and no more
|
|
|
|
* arrive within a small period of time, we fire
|
|
|
|
* off the idle_work.
|
|
|
|
*/
|
2019-05-07 20:11:06 +08:00
|
|
|
struct work_struct idle_work;
|
2019-04-25 04:07:14 +08:00
|
|
|
} gem;
|
2014-07-25 00:04:21 +08:00
|
|
|
|
2019-03-23 02:08:03 +08:00
|
|
|
/* For i945gm vblank irq vs. C3 workaround */
|
|
|
|
struct {
|
|
|
|
struct work_struct work;
|
|
|
|
struct pm_qos_request pm_qos;
|
|
|
|
u8 c3_disable_latency;
|
|
|
|
u8 enabled;
|
|
|
|
} i945gm_vblank;
|
|
|
|
|
2015-09-08 23:05:45 +08:00
|
|
|
/* perform PHY state sanity checks? */
|
|
|
|
bool chv_phy_assert[2];
|
|
|
|
|
2016-12-01 23:49:34 +08:00
|
|
|
bool ipc_enabled;
|
|
|
|
|
drm/i915/dp: DP audio API changes for MST
DP MST provides the capability to send multiple video and audio streams
through a single port. This requires the API's between i915 and audio
drivers to distinguish between multiple audio capable displays that can be
connected to a port. Currently only the port identity is shared in the
APIs. This patch adds support for MST with an additional parameter
'int pipe'. The existing parameter 'port' does not change it's meaning.
pipe =
MST : display pipe that the stream originates from
Non-MST : -1
Affected APIs:
struct i915_audio_component_ops
- int (*sync_audio_rate)(struct device *, int port, int rate);
+ int (*sync_audio_rate)(struct device *, int port, int pipe,
+ int rate);
- int (*get_eld)(struct device *, int port, bool *enabled,
- unsigned char *buf, int max_bytes);
+ int (*get_eld)(struct device *, int port, int pipe,
+ bool *enabled, unsigned char *buf, int max_bytes);
struct i915_audio_component_audio_ops
- void (*pin_eld_notify)(void *audio_ptr, int port);
+ void (*pin_eld_notify)(void *audio_ptr, int port, int pipe);
This patch makes dummy changes in the audio drivers (thanks Libin) for
build to succeed. The audio side drivers will send the right 'pipe' values
for MST in patches that will follow.
v2:
Renamed the new API parameter from 'dev_id' to 'pipe'. (Jim, Ville)
Included Asoc driver API compatibility changes from Jeeja.
Added WARN_ON() for invalid pipe in get_saved_encoder(). (Takashi)
Added comment for av_enc_map[] definition. (Takashi)
v3:
Fixed logic error introduced while renaming 'dev_id' as 'pipe' (Ville)
Renamed get_saved_encoder() to get_saved_enc() to reduce line length
v4:
Rebased.
Parameter check for pipe < -1 values in get_saved_enc() (Ville)
Switched to for_each_pipe() in get_saved_enc() (Ville)
Renamed 'pipe' to 'dev_id' in audio side code (Takashi)
v5:
Included a comment for the dev_id arg. (Libin)
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1474488168-2343-1-git-send-email-dhinakaran.pandiyan@intel.com
2016-09-22 04:02:48 +08:00
|
|
|
/* Used to save the pipe-to-encoder mapping for audio */
|
|
|
|
struct intel_encoder *av_enc_map[I915_MAX_PIPES];
|
2015-12-01 01:19:39 +08:00
|
|
|
|
2017-01-25 06:57:49 +08:00
|
|
|
/* necessary resource sharing with HDMI LPE audio driver. */
|
|
|
|
struct {
|
|
|
|
struct platform_device *platdev;
|
|
|
|
int irq;
|
|
|
|
} lpe_audio;
|
|
|
|
|
drm/i915/pmu: Expose a PMU interface for perf queries
From: Chris Wilson <chris@chris-wilson.co.uk>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
From: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system, but also
runs the risk of hanging the machine.) As an alternative we can use the
perf event counter interface to sample the ring registers periodically
and send those results to userspace.
Functionality we are exporting to userspace is via the existing perf PMU
API and can be exercised via the existing tools. For example:
perf stat -a -e i915/rcs0-busy/ -I 1000
Will print the render engine busynnes once per second. All the performance
counters can be enumerated (perf list) and have their unit of measure
correctly reported in sysfs.
v1-v2 (Chris Wilson):
v2: Use a common timer for the ring sampling.
v3: (Tvrtko Ursulin)
* Decouple uAPI from i915 engine ids.
* Complete uAPI defines.
* Refactor some code to helpers for clarity.
* Skip sampling disabled engines.
* Expose counters in sysfs.
* Pass in fake regs to avoid null ptr deref in perf core.
* Convert to class/instance uAPI.
* Use shared driver code for rc6 residency, power and frequency.
v4: (Dmitry Rogozhkin)
* Register PMU with .task_ctx_nr=perf_invalid_context
* Expose cpumask for the PMU with the single CPU in the mask
* Properly support pmu->stop(): it should call pmu->read()
* Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE)
* Introduce refcounting of event subscriptions.
* Make pmu.busy_stats a refcounter to avoid busy stats going away
with some deleted event.
* Expose cpumask for i915 PMU to avoid multiple events creation of
the same type followed by counter aggregation by perf-stat.
* Track CPUs getting online/offline to migrate perf context. If (likely)
cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be
needed to see effect of CPU status tracking.
* End result is that only global events are supported and perf stat
works correctly.
* Deny perf driver level sampling - it is prohibited for uncore PMU.
v5: (Tvrtko Ursulin)
* Don't hardcode number of engine samplers.
* Rewrite event ref-counting for correctness and simplicity.
* Store initial counter value when starting already enabled events
to correctly report values to all listeners.
* Fix RC6 residency readout.
* Comments, GPL header.
v6:
* Add missing entry to v4 changelog.
* Fix accounting in CPU hotplug case by copying the approach from
arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin)
v7:
* Log failure message only on failure.
* Remove CPU hotplug notification state on unregister.
v8:
* Fix error unwind on failed registration.
* Checkpatch cleanup.
v9:
* Drop the energy metric, it is available via intel_rapl_perf.
(Ville Syrjälä)
* Use HAS_RC6(p). (Chris Wilson)
* Handle unsupported non-engine events. (Dmitry Rogozhkin)
* Rebase for intel_rc6_residency_ns needing caller managed
runtime pm.
* Drop HAS_RC6 checks from the read callback since creating those
events will be rejected at init time already.
* Add counter units to sysfs so perf stat output is nicer.
* Cleanup the attribute tables for brevity and readability.
v10:
* Fixed queued accounting.
v11:
* Move intel_engine_lookup_user to intel_engine_cs.c
* Commit update. (Joonas Lahtinen)
v12:
* More accurate sampling. (Chris Wilson)
* Store and report frequency in MHz for better usability from
perf stat.
* Removed metrics: queued, interrupts, rc6 counters.
* Sample engine busyness based on seqno difference only
for less MMIO (and forcewake) on all platforms. (Chris Wilson)
v13:
* Comment spelling, use mul_u32_u32 to work around potential GCC
issue and somne code alignment changes. (Chris Wilson)
v14:
* Rebase.
v15:
* Rebase for RPS refactoring.
v16:
* Use the dynamic slot in the CPU hotplug state machine so that we are
free to setup our state as multi-instance. Previously we were re-using
the CPUHP_AP_PERF_X86_UNCORE_ONLINE slot which is neither used as
multi-instance, nor owned by our driver to start with.
* Register the CPU hotplug handlers after the PMU, otherwise the callback
will get called before the PMU is initialized which can end up in
perf_pmu_migrate_context with an un-initialized base.
* Added workaround for a probable bug in cpuhp core.
v17:
* Remove workaround for the cpuhp bug.
v18:
* Rebase for drm_i915_gem_engine_class getting upstream before us.
v19:
* Rebase. (trivial)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-2-tvrtko.ursulin@linux.intel.com
2017-11-22 02:18:45 +08:00
|
|
|
struct i915_pmu pmu;
|
|
|
|
|
2019-02-17 01:36:51 +08:00
|
|
|
struct i915_hdcp_comp_master *hdcp_master;
|
|
|
|
bool hdcp_comp_added;
|
|
|
|
|
|
|
|
/* Mutex to protect the above hdcp component related values. */
|
|
|
|
struct mutex hdcp_comp_mutex;
|
|
|
|
|
2014-05-21 23:37:52 +08:00
|
|
|
/*
|
|
|
|
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
|
|
|
|
* will be rejected. Instead look for a better place.
|
|
|
|
*/
|
2014-03-31 19:27:22 +08:00
|
|
|
};
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2019-03-07 04:35:42 +08:00
|
|
|
struct dram_dimm_info {
|
|
|
|
u8 size, width, ranks;
|
|
|
|
};
|
|
|
|
|
2018-08-24 17:32:22 +08:00
|
|
|
struct dram_channel_info {
|
2019-03-07 04:35:48 +08:00
|
|
|
struct dram_dimm_info dimm_l, dimm_s;
|
2019-03-07 04:35:40 +08:00
|
|
|
u8 ranks;
|
2018-08-31 19:09:42 +08:00
|
|
|
bool is_16gb_dimm;
|
2018-08-24 17:32:22 +08:00
|
|
|
};
|
|
|
|
|
2013-08-02 01:39:55 +08:00
|
|
|
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
|
|
|
|
{
|
2016-06-24 21:00:21 +08:00
|
|
|
return container_of(dev, struct drm_i915_private, drm);
|
2013-08-02 01:39:55 +08:00
|
|
|
}
|
|
|
|
|
2016-08-22 18:32:42 +08:00
|
|
|
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
|
2015-01-08 23:54:13 +08:00
|
|
|
{
|
2019-08-06 15:42:19 +08:00
|
|
|
return dev_get_drvdata(kdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return pci_get_drvdata(pdev);
|
2015-01-08 23:54:13 +08:00
|
|
|
}
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
/* Simple iterator over all initialised engines */
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-14 01:14:48 +08:00
|
|
|
#define for_each_engine(engine__, dev_priv__, id__) \
|
|
|
|
for ((id__) = 0; \
|
|
|
|
(id__) < I915_NUM_ENGINES; \
|
|
|
|
(id__)++) \
|
|
|
|
for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
|
2016-03-24 02:19:53 +08:00
|
|
|
|
|
|
|
/* Iterator over subset of engines selected by mask */
|
2016-08-27 15:54:01 +08:00
|
|
|
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
|
2019-03-06 02:03:30 +08:00
|
|
|
for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
|
2018-04-06 19:44:07 +08:00
|
|
|
(tmp__) ? \
|
|
|
|
((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
|
|
|
|
0;)
|
2016-03-16 23:54:00 +08:00
|
|
|
|
2019-08-06 20:43:00 +08:00
|
|
|
#define rb_to_uabi_engine(rb) \
|
|
|
|
rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
|
|
|
|
|
|
|
|
#define for_each_uabi_engine(engine__, i915__) \
|
|
|
|
for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
|
|
|
|
(engine__); \
|
|
|
|
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
|
|
|
|
|
2013-07-04 19:06:28 +08:00
|
|
|
#define I915_GTT_OFFSET_NONE ((u32)-1)
|
2012-11-15 19:32:19 +08:00
|
|
|
|
2014-06-19 05:28:09 +08:00
|
|
|
/*
|
|
|
|
* Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
|
2015-09-15 00:05:42 +08:00
|
|
|
* considered to be the frontbuffer for the given plane interface-wise. This
|
2014-06-19 05:28:09 +08:00
|
|
|
* doesn't mean that the hw necessarily already scans it out, but that any
|
|
|
|
* rendering (by the cpu or gpu) will land in the frontbuffer eventually.
|
|
|
|
*
|
|
|
|
* We have one bit per pipe and per scanout plane type.
|
|
|
|
*/
|
2015-09-15 00:05:42 +08:00
|
|
|
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
|
2018-01-25 02:36:42 +08:00
|
|
|
#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
|
|
|
|
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
|
|
|
|
BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
|
|
|
|
BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
|
|
|
|
})
|
2014-06-19 05:28:09 +08:00
|
|
|
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
|
2018-01-25 02:36:42 +08:00
|
|
|
BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
|
2014-06-18 19:59:13 +08:00
|
|
|
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
|
2018-01-25 02:36:42 +08:00
|
|
|
GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
|
|
|
|
INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
|
2014-06-19 05:28:09 +08:00
|
|
|
|
2018-12-31 22:56:46 +08:00
|
|
|
#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
|
2018-12-31 22:56:41 +08:00
|
|
|
#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
|
2018-07-06 18:14:41 +08:00
|
|
|
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
|
2016-10-13 18:02:58 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
|
2018-12-31 22:56:41 +08:00
|
|
|
#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
|
2010-11-09 17:17:32 +08:00
|
|
|
|
2015-10-20 20:22:02 +08:00
|
|
|
#define REVID_FOREVER 0xff
|
2016-11-04 22:42:46 +08:00
|
|
|
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
|
2016-05-10 17:57:08 +08:00
|
|
|
|
2017-09-13 19:52:54 +08:00
|
|
|
#define INTEL_GEN_MASK(s, e) ( \
|
|
|
|
BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
|
|
|
|
BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
|
2018-10-27 03:51:43 +08:00
|
|
|
GENMASK((e) - 1, (s) - 1))
|
2017-09-13 19:52:54 +08:00
|
|
|
|
2018-10-27 03:51:43 +08:00
|
|
|
/* Returns true if Gen is in inclusive range [Start, End] */
|
2018-12-13 02:10:42 +08:00
|
|
|
#define IS_GEN_RANGE(dev_priv, s, e) \
|
2018-12-31 22:56:44 +08:00
|
|
|
(!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
|
2016-05-10 17:57:08 +08:00
|
|
|
|
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
|
|
|
#define IS_GEN(dev_priv, n) \
|
|
|
|
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gen == (n))
|
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
|
|
|
|
2015-10-20 20:22:02 +08:00
|
|
|
/*
|
|
|
|
* Return true if revision is in range [since,until] inclusive.
|
|
|
|
*
|
|
|
|
* Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
|
|
|
|
*/
|
|
|
|
#define IS_REVID(p, since, until) \
|
|
|
|
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
|
|
|
|
|
2019-03-27 22:23:28 +08:00
|
|
|
static __always_inline unsigned int
|
|
|
|
__platform_mask_index(const struct intel_runtime_info *info,
|
|
|
|
enum intel_platform p)
|
|
|
|
{
|
|
|
|
const unsigned int pbits =
|
|
|
|
BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
|
|
|
|
|
|
|
|
/* Expand the platform_mask array if this fails. */
|
|
|
|
BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
|
|
|
|
pbits * ARRAY_SIZE(info->platform_mask));
|
|
|
|
|
|
|
|
return p / pbits;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __always_inline unsigned int
|
|
|
|
__platform_mask_bit(const struct intel_runtime_info *info,
|
|
|
|
enum intel_platform p)
|
|
|
|
{
|
|
|
|
const unsigned int pbits =
|
|
|
|
BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
|
|
|
|
|
|
|
|
return p % pbits + INTEL_SUBPLATFORM_BITS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32
|
|
|
|
intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
|
|
|
|
{
|
|
|
|
const unsigned int pi = __platform_mask_index(info, p);
|
|
|
|
|
|
|
|
return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __always_inline bool
|
|
|
|
IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
|
|
|
|
{
|
|
|
|
const struct intel_runtime_info *info = RUNTIME_INFO(i915);
|
|
|
|
const unsigned int pi = __platform_mask_index(info, p);
|
|
|
|
const unsigned int pb = __platform_mask_bit(info, p);
|
|
|
|
|
|
|
|
BUILD_BUG_ON(!__builtin_constant_p(p));
|
|
|
|
|
|
|
|
return info->platform_mask[pi] & BIT(pb);
|
|
|
|
}
|
|
|
|
|
|
|
|
static __always_inline bool
|
|
|
|
IS_SUBPLATFORM(const struct drm_i915_private *i915,
|
|
|
|
enum intel_platform p, unsigned int s)
|
|
|
|
{
|
|
|
|
const struct intel_runtime_info *info = RUNTIME_INFO(i915);
|
|
|
|
const unsigned int pi = __platform_mask_index(info, p);
|
|
|
|
const unsigned int pb = __platform_mask_bit(info, p);
|
|
|
|
const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
|
|
|
|
const u32 mask = info->platform_mask[pi];
|
|
|
|
|
|
|
|
BUILD_BUG_ON(!__builtin_constant_p(p));
|
|
|
|
BUILD_BUG_ON(!__builtin_constant_p(s));
|
|
|
|
BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
|
|
|
|
|
|
|
|
/* Shift and test on the MSB position so sign flag can be used. */
|
|
|
|
return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
|
|
|
|
}
|
2017-09-20 17:26:59 +08:00
|
|
|
|
2019-03-26 15:40:55 +08:00
|
|
|
#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
|
|
|
|
|
2017-09-20 17:26:59 +08:00
|
|
|
#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
|
|
|
|
#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
|
|
|
|
#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
|
|
|
|
#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
|
|
|
|
#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
|
|
|
|
#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
|
|
|
|
#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
|
|
|
|
#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
|
|
|
|
#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
|
|
|
|
#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
|
|
|
|
#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
|
|
|
|
#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
|
2016-11-30 23:43:05 +08:00
|
|
|
#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
|
2017-09-20 17:26:59 +08:00
|
|
|
#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
|
|
|
|
#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
|
2019-03-26 15:40:55 +08:00
|
|
|
#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
|
|
|
|
#define IS_IRONLAKE_M(dev_priv) \
|
|
|
|
(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
|
2017-09-20 17:26:59 +08:00
|
|
|
#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
|
2017-08-31 00:12:07 +08:00
|
|
|
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 1)
|
2017-09-20 17:26:59 +08:00
|
|
|
#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
|
|
|
|
#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
|
|
|
|
#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
|
|
|
|
#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
|
|
|
|
#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
|
|
|
|
#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
|
|
|
|
#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
|
|
|
|
#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
|
|
|
|
#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
|
|
|
|
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
|
2018-01-12 02:00:04 +08:00
|
|
|
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
|
2019-03-23 01:58:43 +08:00
|
|
|
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
|
2019-07-12 01:30:56 +08:00
|
|
|
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
|
2016-10-13 18:02:58 +08:00
|
|
|
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
|
|
|
|
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
|
2019-03-27 22:23:28 +08:00
|
|
|
#define IS_BDW_ULT(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
|
|
|
|
#define IS_BDW_ULX(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
|
2016-10-13 18:02:58 +08:00
|
|
|
#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 3)
|
2019-03-27 22:23:28 +08:00
|
|
|
#define IS_HSW_ULT(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
|
2016-10-13 18:02:58 +08:00
|
|
|
#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 3)
|
2018-12-28 22:07:34 +08:00
|
|
|
#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 1)
|
2014-04-29 22:00:22 +08:00
|
|
|
/* ULX machines are also considered ULT. */
|
2019-03-27 22:23:28 +08:00
|
|
|
#define IS_HSW_ULX(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
|
|
|
|
#define IS_SKL_ULT(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
|
|
|
|
#define IS_SKL_ULX(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
|
|
|
|
#define IS_KBL_ULT(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
|
|
|
|
#define IS_KBL_ULX(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
|
2017-06-13 19:23:03 +08:00
|
|
|
#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 2)
|
2016-10-13 18:02:58 +08:00
|
|
|
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 3)
|
2016-10-13 18:02:58 +08:00
|
|
|
#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 4)
|
2017-06-13 19:23:07 +08:00
|
|
|
#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 2)
|
2017-06-13 19:23:07 +08:00
|
|
|
#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 3)
|
2019-03-27 22:23:28 +08:00
|
|
|
#define IS_CFL_ULT(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
|
2019-06-06 00:29:46 +08:00
|
|
|
#define IS_CFL_ULX(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
|
2017-09-18 19:21:24 +08:00
|
|
|
#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 2)
|
2017-11-11 03:08:40 +08:00
|
|
|
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
|
2018-12-31 22:56:44 +08:00
|
|
|
INTEL_INFO(dev_priv)->gt == 3)
|
2019-03-27 22:23:28 +08:00
|
|
|
#define IS_CNL_WITH_PORT_F(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
|
|
|
|
#define IS_ICL_WITH_PORT_F(dev_priv) \
|
|
|
|
IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
|
2015-09-12 12:47:50 +08:00
|
|
|
|
2015-10-20 20:22:00 +08:00
|
|
|
#define SKL_REVID_A0 0x0
|
|
|
|
#define SKL_REVID_B0 0x1
|
|
|
|
#define SKL_REVID_C0 0x2
|
|
|
|
#define SKL_REVID_D0 0x3
|
|
|
|
#define SKL_REVID_E0 0x4
|
|
|
|
#define SKL_REVID_F0 0x5
|
2016-07-20 19:26:12 +08:00
|
|
|
#define SKL_REVID_G0 0x6
|
|
|
|
#define SKL_REVID_H0 0x7
|
2015-10-20 20:22:00 +08:00
|
|
|
|
2015-10-20 20:22:02 +08:00
|
|
|
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
|
|
|
|
|
2015-10-20 20:22:00 +08:00
|
|
|
#define BXT_REVID_A0 0x0
|
2015-10-20 20:22:01 +08:00
|
|
|
#define BXT_REVID_A1 0x1
|
2015-10-20 20:22:00 +08:00
|
|
|
#define BXT_REVID_B0 0x3
|
2016-11-24 21:23:27 +08:00
|
|
|
#define BXT_REVID_B_LAST 0x8
|
2015-10-20 20:22:00 +08:00
|
|
|
#define BXT_REVID_C0 0x9
|
2015-03-20 17:03:52 +08:00
|
|
|
|
2016-10-13 18:03:04 +08:00
|
|
|
#define IS_BXT_REVID(dev_priv, since, until) \
|
|
|
|
(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
|
2015-10-20 20:22:02 +08:00
|
|
|
|
2016-06-07 22:18:55 +08:00
|
|
|
#define KBL_REVID_A0 0x0
|
|
|
|
#define KBL_REVID_B0 0x1
|
2016-06-07 22:19:03 +08:00
|
|
|
#define KBL_REVID_C0 0x2
|
|
|
|
#define KBL_REVID_D0 0x3
|
|
|
|
#define KBL_REVID_E0 0x4
|
2016-06-07 22:18:55 +08:00
|
|
|
|
2016-10-13 18:03:02 +08:00
|
|
|
#define IS_KBL_REVID(dev_priv, since, until) \
|
|
|
|
(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
|
2016-06-07 22:18:55 +08:00
|
|
|
|
2017-02-22 14:34:29 +08:00
|
|
|
#define GLK_REVID_A0 0x0
|
|
|
|
#define GLK_REVID_A1 0x1
|
|
|
|
|
|
|
|
#define IS_GLK_REVID(dev_priv, since, until) \
|
|
|
|
(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
|
|
|
|
|
2017-06-07 04:30:34 +08:00
|
|
|
#define CNL_REVID_A0 0x0
|
|
|
|
#define CNL_REVID_B0 0x1
|
2017-08-23 07:58:28 +08:00
|
|
|
#define CNL_REVID_C0 0x2
|
2017-06-07 04:30:34 +08:00
|
|
|
|
|
|
|
#define IS_CNL_REVID(p, since, until) \
|
|
|
|
(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
|
|
|
|
|
2018-05-09 05:29:23 +08:00
|
|
|
#define ICL_REVID_A0 0x0
|
|
|
|
#define ICL_REVID_A2 0x1
|
|
|
|
#define ICL_REVID_B0 0x3
|
|
|
|
#define ICL_REVID_B2 0x4
|
|
|
|
#define ICL_REVID_C0 0x5
|
|
|
|
|
|
|
|
#define IS_ICL_REVID(p, since, until) \
|
|
|
|
(IS_ICELAKE(p) && IS_REVID(p, since, until))
|
|
|
|
|
2016-12-19 05:36:26 +08:00
|
|
|
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
|
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
|
|
|
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
|
|
|
|
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
|
2016-11-10 23:23:09 +08:00
|
|
|
|
2019-03-06 02:03:30 +08:00
|
|
|
#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
|
2016-06-23 21:52:41 +08:00
|
|
|
|
2019-03-22 08:24:31 +08:00
|
|
|
#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
|
|
|
|
unsigned int first__ = (first); \
|
|
|
|
unsigned int count__ = (count); \
|
|
|
|
(INTEL_INFO(dev_priv)->engine_mask & \
|
2019-03-27 02:00:07 +08:00
|
|
|
GENMASK(first__ + count__ - 1, first__)) >> first__; \
|
2019-03-22 08:24:31 +08:00
|
|
|
})
|
|
|
|
#define VDBOX_MASK(dev_priv) \
|
|
|
|
ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
|
|
|
|
#define VEBOX_MASK(dev_priv) \
|
|
|
|
ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
|
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
|
|
|
|
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
|
2019-03-29 01:45:32 +08:00
|
|
|
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
|
2016-10-13 18:03:00 +08:00
|
|
|
#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
|
|
|
|
IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
|
2010-11-09 17:17:32 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
|
2012-02-10 00:15:46 +08:00
|
|
|
|
2016-11-04 22:42:44 +08:00
|
|
|
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
|
2018-12-31 22:56:44 +08:00
|
|
|
(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
|
2018-03-03 00:14:59 +08:00
|
|
|
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
|
2018-12-31 22:56:44 +08:00
|
|
|
(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
|
2017-10-26 04:00:18 +08:00
|
|
|
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
|
2018-12-31 22:56:44 +08:00
|
|
|
(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
|
2017-11-21 04:55:00 +08:00
|
|
|
|
|
|
|
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
|
|
|
|
|
2019-03-15 06:38:36 +08:00
|
|
|
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
|
2018-09-27 04:12:22 +08:00
|
|
|
#define HAS_PPGTT(dev_priv) \
|
|
|
|
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
|
|
|
|
#define HAS_FULL_PPGTT(dev_priv) \
|
|
|
|
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
|
|
|
|
|
2017-10-07 06:18:18 +08:00
|
|
|
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
|
|
|
|
GEM_BUG_ON((sizes) == 0); \
|
2018-12-31 22:56:44 +08:00
|
|
|
((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
|
2017-10-07 06:18:18 +08:00
|
|
|
})
|
2016-11-04 22:42:44 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
|
2016-11-04 22:42:44 +08:00
|
|
|
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
|
2018-12-31 22:56:44 +08:00
|
|
|
(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
|
2010-11-09 17:17:32 +08:00
|
|
|
|
2012-12-17 23:21:27 +08:00
|
|
|
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
|
2016-11-30 23:43:04 +08:00
|
|
|
#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
|
2015-12-17 01:18:37 +08:00
|
|
|
|
2018-02-23 04:05:35 +08:00
|
|
|
/* WaRsDisableCoarsePowerGating:skl,cnl */
|
2016-06-21 22:07:14 +08:00
|
|
|
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
|
2018-02-23 04:05:35 +08:00
|
|
|
(IS_CANNONLAKE(dev_priv) || \
|
|
|
|
IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
|
2016-04-05 20:56:16 +08:00
|
|
|
|
2017-08-19 02:37:05 +08:00
|
|
|
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
|
2018-06-28 21:34:49 +08:00
|
|
|
#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
|
|
|
|
IS_GEMINILAKE(dev_priv) || \
|
|
|
|
IS_KABYLAKE(dev_priv))
|
2012-12-17 23:21:27 +08:00
|
|
|
|
2010-11-09 17:17:32 +08:00
|
|
|
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
|
|
|
|
* rows, which changed the alignment requirements and fence programming.
|
|
|
|
*/
|
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
|
|
|
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
|
2016-10-13 18:02:58 +08:00
|
|
|
!(IS_I915G(dev_priv) || \
|
|
|
|
IS_I915GM(dev_priv)))
|
2018-12-31 22:56:44 +08:00
|
|
|
#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
|
|
|
|
#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
|
2010-11-09 17:17:32 +08:00
|
|
|
|
2016-11-07 17:29:20 +08:00
|
|
|
#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
|
2019-02-05 06:25:38 +08:00
|
|
|
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
|
2010-11-09 17:17:32 +08:00
|
|
|
|
2016-10-13 18:02:58 +08:00
|
|
|
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
|
2013-06-25 01:29:34 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
|
2015-05-18 22:10:01 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
|
|
|
|
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
|
|
|
|
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
|
2019-02-23 07:02:54 +08:00
|
|
|
#define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
|
2017-12-01 19:30:30 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
|
|
|
|
#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
|
2017-12-01 19:30:30 +08:00
|
|
|
#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
|
2012-11-24 01:30:39 +08:00
|
|
|
|
2019-04-19 21:48:36 +08:00
|
|
|
#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
|
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 20:58:44 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
|
|
|
|
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
|
2016-11-03 16:39:46 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
|
2017-08-17 21:45:27 +08:00
|
|
|
|
2019-07-25 08:18:06 +08:00
|
|
|
#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
|
2015-08-12 22:43:36 +08:00
|
|
|
|
2019-07-31 07:07:40 +08:00
|
|
|
/* Having GuC is not the same as using GuC */
|
2019-08-01 06:33:18 +08:00
|
|
|
#define USES_GUC(dev_priv) intel_uc_supports_guc(&(dev_priv)->gt.uc)
|
|
|
|
#define USES_GUC_SUBMISSION(dev_priv) intel_uc_supports_guc_submission(&(dev_priv)->gt.uc)
|
2017-12-06 21:53:12 +08:00
|
|
|
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
|
2016-06-03 13:34:33 +08:00
|
|
|
|
2019-07-31 02:04:06 +08:00
|
|
|
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
|
|
|
|
|
2010-11-09 17:17:32 +08:00
|
|
|
|
2019-02-05 06:25:38 +08:00
|
|
|
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
|
2014-07-21 17:53:38 +08:00
|
|
|
|
2017-06-10 06:26:14 +08:00
|
|
|
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
|
2016-10-14 22:26:50 +08:00
|
|
|
|
2013-09-20 02:01:40 +08:00
|
|
|
/* DPF == dynamic parity feature */
|
2018-12-31 22:56:44 +08:00
|
|
|
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
|
2016-10-13 18:02:58 +08:00
|
|
|
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
|
|
|
|
2 : HAS_L3_DPF(dev_priv))
|
2012-07-25 11:47:31 +08:00
|
|
|
|
2012-09-08 10:43:39 +08:00
|
|
|
#define GT_FREQUENCY_MULTIPLIER 50
|
2015-03-06 13:37:14 +08:00
|
|
|
#define GEN9_FREQ_SCALER 3
|
2012-09-08 10:43:39 +08:00
|
|
|
|
2018-12-01 07:20:47 +08:00
|
|
|
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
|
|
|
|
|
2017-05-25 20:16:12 +08:00
|
|
|
static inline bool intel_vtd_active(void)
|
2016-06-24 21:07:14 +08:00
|
|
|
{
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
2017-05-25 20:16:12 +08:00
|
|
|
if (intel_iommu_gfx_mapped)
|
2016-06-24 21:07:14 +08:00
|
|
|
return true;
|
|
|
|
#endif
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-05-25 20:16:12 +08:00
|
|
|
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
|
|
|
|
}
|
|
|
|
|
2017-05-24 23:54:11 +08:00
|
|
|
static inline bool
|
|
|
|
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2017-05-25 20:16:12 +08:00
|
|
|
return IS_BROXTON(dev_priv) && intel_vtd_active();
|
2017-05-24 23:54:11 +08:00
|
|
|
}
|
|
|
|
|
2016-06-24 21:00:22 +08:00
|
|
|
/* i915_drv.c */
|
2012-04-17 05:07:40 +08:00
|
|
|
#ifdef CONFIG_COMPAT
|
2019-07-12 19:24:25 +08:00
|
|
|
long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
|
2016-11-01 23:40:44 +08:00
|
|
|
#else
|
|
|
|
#define i915_compat_ioctl NULL
|
2012-04-17 05:07:40 +08:00
|
|
|
#endif
|
2016-09-15 21:28:54 +08:00
|
|
|
extern const struct dev_pm_ops i915_pm_ops;
|
|
|
|
|
2019-07-12 19:24:26 +08:00
|
|
|
int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
|
2019-08-06 15:42:19 +08:00
|
|
|
void i915_driver_remove(struct drm_i915_private *i915);
|
2019-01-16 23:33:04 +08:00
|
|
|
|
2019-07-12 19:24:25 +08:00
|
|
|
void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
|
2014-04-18 21:35:02 +08:00
|
|
|
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
|
2010-05-21 05:28:11 +08:00
|
|
|
|
drm/i915: gvt: Introduce the basic architecture of GVT-g
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v12:
- Call intel_gvt_init() in driver early initialization stage. (Chris)
v8:
- Remove the GVT idr and mutex in intel_gvt_host. (Joonas)
v7:
- Refine the URL link in Kconfig. (Joonas)
- Refine the introduction of GVT-g host support in Kconfig. (Joonas)
- Remove the macro GVT_ALIGN(), use round_down() instead. (Joonas)
- Make "struct intel_gvt" a data member in struct drm_i915_private.(Joonas)
- Remove {alloc, free}_gvt_device()
- Rename intel_gvt_{create, destroy}_gvt_device()
- Expost intel_gvt_init_host()
- Remove the dummy "struct intel_gvt" declaration in intel_gvt.h (Joonas)
v6:
- Refine introduction in Kconfig. (Chris)
- The exposed API functions will take struct intel_gvt * instead of
void *. (Chris/Tvrtko)
- Remove most memebers of strct intel_gvt_device_info. Will add them
in the device model patches.(Chris)
- Remove gvt_info() and gvt_err() in debug.h. (Chris)
- Move GVT kernel parameter into i915_params. (Chris)
- Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
- Remove the redundant struct i915_gvt *, as the functions in i915
will directly take struct intel_gvt *.
- Add more comments for reviewer.
v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfig
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization
v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.
Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.
Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-5-git-send-email-zhi.a.wang@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-16 20:07:00 +08:00
|
|
|
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2016-10-20 17:15:03 +08:00
|
|
|
return dev_priv->gvt;
|
drm/i915: gvt: Introduce the basic architecture of GVT-g
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v12:
- Call intel_gvt_init() in driver early initialization stage. (Chris)
v8:
- Remove the GVT idr and mutex in intel_gvt_host. (Joonas)
v7:
- Refine the URL link in Kconfig. (Joonas)
- Refine the introduction of GVT-g host support in Kconfig. (Joonas)
- Remove the macro GVT_ALIGN(), use round_down() instead. (Joonas)
- Make "struct intel_gvt" a data member in struct drm_i915_private.(Joonas)
- Remove {alloc, free}_gvt_device()
- Rename intel_gvt_{create, destroy}_gvt_device()
- Expost intel_gvt_init_host()
- Remove the dummy "struct intel_gvt" declaration in intel_gvt.h (Joonas)
v6:
- Refine introduction in Kconfig. (Chris)
- The exposed API functions will take struct intel_gvt * instead of
void *. (Chris/Tvrtko)
- Remove most memebers of strct intel_gvt_device_info. Will add them
in the device model patches.(Chris)
- Remove gvt_info() and gvt_err() in debug.h. (Chris)
- Move GVT kernel parameter into i915_params. (Chris)
- Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
- Remove the redundant struct i915_gvt *, as the functions in i915
will directly take struct intel_gvt *.
- Add more comments for reviewer.
v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfig
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization
v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.
Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.
Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-5-git-send-email-zhi.a.wang@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-16 20:07:00 +08:00
|
|
|
}
|
|
|
|
|
2016-05-06 22:40:21 +08:00
|
|
|
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
|
2015-02-10 19:05:47 +08:00
|
|
|
{
|
2016-05-06 22:40:21 +08:00
|
|
|
return dev_priv->vgpu.active;
|
2015-02-10 19:05:47 +08:00
|
|
|
}
|
2011-04-07 03:13:38 +08:00
|
|
|
|
2019-08-07 22:20:41 +08:00
|
|
|
int i915_getparam_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
|
|
|
|
2008-07-31 03:06:12 +08:00
|
|
|
/* i915_gem.c */
|
2017-06-16 22:05:22 +08:00
|
|
|
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
|
|
|
|
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
|
2017-01-24 19:01:35 +08:00
|
|
|
void i915_gem_sanitize(struct drm_i915_private *i915);
|
2018-03-23 20:34:49 +08:00
|
|
|
int i915_gem_init_early(struct drm_i915_private *dev_priv);
|
|
|
|
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
|
2016-09-21 21:51:07 +08:00
|
|
|
int i915_gem_freeze(struct drm_i915_private *dev_priv);
|
2016-05-14 14:26:33 +08:00
|
|
|
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
|
|
|
|
|
2016-12-23 22:57:56 +08:00
|
|
|
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
|
|
|
|
{
|
2019-07-03 17:17:17 +08:00
|
|
|
/*
|
|
|
|
* A single pass should suffice to release all the freed objects (along
|
2016-12-23 22:57:56 +08:00
|
|
|
* most call paths) , but be a little more paranoid in that freeing
|
|
|
|
* the objects does take a little amount of time, during which the rcu
|
|
|
|
* callbacks could have added new objects into the freed list, and
|
|
|
|
* armed the work again.
|
|
|
|
*/
|
2019-07-03 17:17:17 +08:00
|
|
|
while (atomic_read(&i915->mm.free_count)) {
|
|
|
|
flush_work(&i915->mm.free_work);
|
2016-12-23 22:57:56 +08:00
|
|
|
rcu_barrier();
|
2019-07-03 17:17:17 +08:00
|
|
|
}
|
2016-12-23 22:57:56 +08:00
|
|
|
}
|
|
|
|
|
2017-07-18 21:41:24 +08:00
|
|
|
static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Similar to objects above (see i915_gem_drain_freed-objects), in
|
|
|
|
* general we have workers that are armed by RCU and then rearm
|
|
|
|
* themselves in their callbacks. To be paranoid, we need to
|
|
|
|
* drain the workqueue a second time after waiting for the RCU
|
|
|
|
* grace period so that we catch work queued via RCU from the first
|
|
|
|
* pass. As neither drain_workqueue() nor flush_workqueue() report
|
|
|
|
* a result, we make an assumption that we only don't require more
|
2019-05-01 21:57:51 +08:00
|
|
|
* than 3 passes to catch all _recursive_ RCU delayed work.
|
2017-07-18 21:41:24 +08:00
|
|
|
*
|
|
|
|
*/
|
2019-05-01 21:57:51 +08:00
|
|
|
int pass = 3;
|
2017-07-18 21:41:24 +08:00
|
|
|
do {
|
2019-07-04 01:19:13 +08:00
|
|
|
flush_workqueue(i915->wq);
|
2017-07-18 21:41:24 +08:00
|
|
|
rcu_barrier();
|
2019-04-06 18:40:34 +08:00
|
|
|
i915_gem_drain_freed_objects(i915);
|
2017-07-18 21:41:24 +08:00
|
|
|
} while (--pass);
|
2019-05-01 21:57:51 +08:00
|
|
|
drain_workqueue(i915->wq);
|
2017-07-18 21:41:24 +08:00
|
|
|
}
|
|
|
|
|
2016-08-15 17:49:06 +08:00
|
|
|
struct i915_vma * __must_check
|
2015-03-16 20:11:13 +08:00
|
|
|
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
|
|
|
|
const struct i915_ggtt_view *view,
|
2016-08-04 23:32:23 +08:00
|
|
|
u64 size,
|
2016-08-04 23:32:22 +08:00
|
|
|
u64 alignment,
|
|
|
|
u64 flags);
|
2014-12-11 01:27:58 +08:00
|
|
|
|
2019-07-03 17:17:17 +08:00
|
|
|
int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
|
|
|
|
unsigned long flags);
|
|
|
|
#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
|
2010-09-24 23:02:42 +08:00
|
|
|
|
2016-10-24 20:42:18 +08:00
|
|
|
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
|
|
|
|
|
2019-02-08 23:37:03 +08:00
|
|
|
static inline int __must_check
|
|
|
|
i915_mutex_lock_interruptible(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
return mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
}
|
|
|
|
|
2011-02-07 10:16:14 +08:00
|
|
|
int i915_gem_dumb_create(struct drm_file *file_priv,
|
|
|
|
struct drm_device *dev,
|
|
|
|
struct drm_mode_create_dumb *args);
|
2014-12-24 11:11:17 +08:00
|
|
|
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
|
2019-01-18 20:01:24 +08:00
|
|
|
u32 handle, u64 *offset);
|
2016-08-26 02:05:19 +08:00
|
|
|
int i915_gem_mmap_gtt_version(void);
|
2016-05-20 18:54:06 +08:00
|
|
|
|
2016-10-28 20:58:46 +08:00
|
|
|
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
|
2011-12-14 20:57:08 +08:00
|
|
|
|
2013-11-12 20:44:19 +08:00
|
|
|
static inline u32 i915_reset_count(struct i915_gpu_error *error)
|
|
|
|
{
|
2019-07-13 03:29:53 +08:00
|
|
|
return atomic_read(&error->reset_count);
|
2012-11-16 00:17:22 +08:00
|
|
|
}
|
2012-02-15 19:25:36 +08:00
|
|
|
|
2017-06-20 17:57:48 +08:00
|
|
|
static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
2019-07-13 03:29:53 +08:00
|
|
|
return atomic_read(&error->reset_engine_count[engine->uabi_class]);
|
2017-06-20 17:57:48 +08:00
|
|
|
}
|
|
|
|
|
2017-01-24 19:01:35 +08:00
|
|
|
void i915_gem_init_mmio(struct drm_i915_private *i915);
|
2016-12-01 22:16:38 +08:00
|
|
|
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
|
|
|
|
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
|
2019-08-06 20:42:59 +08:00
|
|
|
void i915_gem_driver_register(struct drm_i915_private *i915);
|
|
|
|
void i915_gem_driver_unregister(struct drm_i915_private *i915);
|
2019-07-12 19:24:29 +08:00
|
|
|
void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
|
2019-07-12 19:24:28 +08:00
|
|
|
void i915_gem_driver_release(struct drm_i915_private *dev_priv);
|
2017-02-14 01:15:58 +08:00
|
|
|
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
|
2018-07-09 20:20:42 +08:00
|
|
|
unsigned int flags, long timeout);
|
2019-03-08 17:36:54 +08:00
|
|
|
void i915_gem_suspend(struct drm_i915_private *dev_priv);
|
2018-05-31 16:22:46 +08:00
|
|
|
void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
|
2016-12-01 22:16:38 +08:00
|
|
|
void i915_gem_resume(struct drm_i915_private *dev_priv);
|
2018-06-07 05:45:20 +08:00
|
|
|
vm_fault_t i915_gem_fault(struct vm_fault *vmf);
|
2016-11-15 04:41:05 +08:00
|
|
|
|
2017-06-20 19:05:45 +08:00
|
|
|
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
|
2010-11-09 03:18:58 +08:00
|
|
|
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
|
2008-07-31 03:06:12 +08:00
|
|
|
|
2011-04-04 16:44:39 +08:00
|
|
|
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
|
|
|
|
enum i915_cache_level cache_level);
|
|
|
|
|
2012-05-10 21:25:09 +08:00
|
|
|
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
|
|
|
|
struct dma_buf *dma_buf);
|
|
|
|
|
|
|
|
struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
|
|
|
|
struct drm_gem_object *gem_obj, int flags);
|
|
|
|
|
2017-06-20 19:05:47 +08:00
|
|
|
static inline struct i915_gem_context *
|
|
|
|
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
|
|
|
|
{
|
|
|
|
return idr_find(&file_priv->context_idr, id);
|
|
|
|
}
|
|
|
|
|
2016-05-24 21:53:36 +08:00
|
|
|
static inline struct i915_gem_context *
|
|
|
|
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
|
|
|
|
{
|
|
|
|
struct i915_gem_context *ctx;
|
|
|
|
|
2017-06-20 19:05:47 +08:00
|
|
|
rcu_read_lock();
|
|
|
|
ctx = __i915_gem_context_lookup_rcu(file_priv, id);
|
|
|
|
if (ctx && !kref_get_unless_zero(&ctx->ref))
|
|
|
|
ctx = NULL;
|
|
|
|
rcu_read_unlock();
|
2016-05-24 21:53:36 +08:00
|
|
|
|
|
|
|
return ctx;
|
|
|
|
}
|
|
|
|
|
2013-12-07 06:11:23 +08:00
|
|
|
/* i915_gem_evict.c */
|
2016-08-04 23:32:18 +08:00
|
|
|
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
|
2016-08-04 23:32:22 +08:00
|
|
|
u64 min_size, u64 alignment,
|
2013-12-07 06:11:23 +08:00
|
|
|
unsigned cache_level,
|
2016-08-04 23:32:22 +08:00
|
|
|
u64 start, u64 end,
|
2014-02-14 21:01:11 +08:00
|
|
|
unsigned flags);
|
2017-01-11 19:23:11 +08:00
|
|
|
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
|
|
|
|
struct drm_mm_node *node,
|
|
|
|
unsigned int flags);
|
drm/i915: Eliminate lots of iterations over the execobjects array
The major scaling bottleneck in execbuffer is the processing of the
execobjects. Creating an auxiliary list is inefficient when compared to
using the execobject array we already have allocated.
Reservation is then split into phases. As we lookup up the VMA, we
try and bind it back into active location. Only if that fails, do we add
it to the unbound list for phase 2. In phase 2, we try and add all those
objects that could not fit into their previous location, with fallback
to retrying all objects and evicting the VM in case of severe
fragmentation. (This is the same as before, except that phase 1 is now
done inline with looking up the VMA to avoid an iteration over the
execobject array. In the ideal case, we eliminate the separate reservation
phase). During the reservation phase, we only evict from the VM between
passes (rather than currently as we try to fit every new VMA). In
testing with Unreal Engine's Atlantis demo which stresses the eviction
logic on gen7 class hardware, this speed up the framerate by a factor of
2.
The second loop amalgamation is between move_to_gpu and move_to_active.
As we always submit the request, even if incomplete, we can use the
current request to track active VMA as we perform the flushes and
synchronisation required.
The next big advancement is to avoid copying back to the user any
execobjects and relocations that are not changed.
v2: Add a Theory of Operation spiel.
v3: Fall back to slow relocations in preparation for flushing userptrs.
v4: Document struct members, factor out eb_validate_vma(), add a few
more comments to explain some magic and hide other magic behind macros.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2017-06-16 22:05:19 +08:00
|
|
|
int i915_gem_evict_vm(struct i915_address_space *vm);
|
2012-02-10 00:15:46 +08:00
|
|
|
|
2016-10-28 20:58:30 +08:00
|
|
|
/* i915_gem_internal.c */
|
|
|
|
struct drm_i915_gem_object *
|
|
|
|
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
|
2017-01-12 21:04:31 +08:00
|
|
|
phys_addr_t size);
|
2016-10-28 20:58:30 +08:00
|
|
|
|
2008-07-31 03:06:12 +08:00
|
|
|
/* i915_gem_tiling.c */
|
2013-08-02 01:39:55 +08:00
|
|
|
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
|
2012-12-04 05:03:14 +08:00
|
|
|
{
|
2016-06-24 21:00:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
|
2012-12-04 05:03:14 +08:00
|
|
|
|
|
|
|
return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
|
2016-08-05 17:14:23 +08:00
|
|
|
i915_gem_object_is_tiled(obj);
|
2012-12-04 05:03:14 +08:00
|
|
|
}
|
|
|
|
|
2017-01-10 00:16:13 +08:00
|
|
|
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
|
|
|
|
unsigned int tiling, unsigned int stride);
|
|
|
|
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
|
|
|
|
unsigned int tiling, unsigned int stride);
|
|
|
|
|
2014-08-22 21:41:39 +08:00
|
|
|
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
|
2009-02-18 09:08:50 +08:00
|
|
|
|
2014-02-19 02:15:46 +08:00
|
|
|
/* i915_cmd_parser.c */
|
2016-05-04 21:25:36 +08:00
|
|
|
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
|
2016-08-19 00:17:10 +08:00
|
|
|
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
|
2016-07-27 16:07:26 +08:00
|
|
|
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
|
|
|
|
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
|
|
|
|
struct drm_i915_gem_object *batch_obj,
|
|
|
|
struct drm_i915_gem_object *shadow_batch_obj,
|
|
|
|
u32 batch_start_offset,
|
|
|
|
u32 batch_len,
|
|
|
|
bool is_master);
|
2014-02-19 02:15:46 +08:00
|
|
|
|
2016-07-05 17:40:20 +08:00
|
|
|
/* intel_device_info.c */
|
|
|
|
static inline struct intel_device_info *
|
|
|
|
mkwrite_device_info(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2018-12-31 22:56:44 +08:00
|
|
|
return (struct intel_device_info *)INTEL_INFO(dev_priv);
|
2016-07-05 17:40:20 +08:00
|
|
|
}
|
|
|
|
|
2012-07-13 02:01:05 +08:00
|
|
|
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file);
|
2012-03-29 04:39:37 +08:00
|
|
|
|
2019-03-26 05:49:36 +08:00
|
|
|
#define __I915_REG_OP(op__, dev_priv__, ...) \
|
|
|
|
intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
|
2013-10-05 12:22:51 +08:00
|
|
|
|
2019-03-26 05:49:36 +08:00
|
|
|
#define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
|
|
|
|
#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
|
2013-10-05 12:22:51 +08:00
|
|
|
|
2019-03-26 05:49:36 +08:00
|
|
|
#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
|
2010-11-09 17:17:32 +08:00
|
|
|
|
2015-04-07 23:21:02 +08:00
|
|
|
/* These are untraced mmio-accessors that are only valid to be used inside
|
2016-10-25 20:48:02 +08:00
|
|
|
* critical sections, such as inside IRQ handlers, where forcewake is explicitly
|
2015-04-07 23:21:02 +08:00
|
|
|
* controlled.
|
2016-10-25 20:48:02 +08:00
|
|
|
*
|
2015-04-07 23:21:02 +08:00
|
|
|
* Think twice, and think again, before using these.
|
2016-10-25 20:48:02 +08:00
|
|
|
*
|
|
|
|
* As an example, these accessors can possibly be used between:
|
|
|
|
*
|
|
|
|
* spin_lock_irq(&dev_priv->uncore.lock);
|
|
|
|
* intel_uncore_forcewake_get__locked();
|
|
|
|
*
|
|
|
|
* and
|
|
|
|
*
|
|
|
|
* intel_uncore_forcewake_put__locked();
|
|
|
|
* spin_unlock_irq(&dev_priv->uncore.lock);
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* Note: some registers may not need forcewake held, so
|
|
|
|
* intel_uncore_forcewake_{get,put} can be omitted, see
|
|
|
|
* intel_uncore_forcewake_for_reg().
|
|
|
|
*
|
|
|
|
* Certain architectures will die if the same cacheline is concurrently accessed
|
|
|
|
* by different clients (e.g. on Ivybridge). Access to registers should
|
|
|
|
* therefore generally be serialised, by either the dev_priv->uncore.lock or
|
|
|
|
* a more localised lock guarding all access to that bank of registers.
|
2015-04-07 23:21:02 +08:00
|
|
|
*/
|
2019-03-26 05:49:36 +08:00
|
|
|
#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
|
|
|
|
#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
|
2015-04-07 23:21:02 +08:00
|
|
|
|
2016-08-19 23:54:28 +08:00
|
|
|
/* i915_mm.c */
|
|
|
|
int remap_io_mapping(struct vm_area_struct *vma,
|
|
|
|
unsigned long addr, unsigned long pfn, unsigned long size,
|
|
|
|
struct io_mapping *iomap);
|
|
|
|
|
2017-09-13 16:56:05 +08:00
|
|
|
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
if (INTEL_GEN(i915) >= 10)
|
|
|
|
return CNL_HWS_CSB_WRITE_INDEX;
|
|
|
|
else
|
|
|
|
return I915_HWS_CSB_WRITE_INDEX;
|
|
|
|
}
|
|
|
|
|
2019-05-28 17:29:44 +08:00
|
|
|
static inline enum i915_map_type
|
|
|
|
i915_coherent_map_type(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#endif
|