2019-06-13 01:52:38 +08:00
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=======================================
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Silicon Errata and Software Workarounds
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=======================================
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2015-11-17 22:45:47 +08:00
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Author: Will Deacon <will.deacon@arm.com>
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2019-06-13 01:52:38 +08:00
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2015-11-17 22:45:47 +08:00
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Date : 27 November 2015
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It is an unfortunate fact of life that hardware is often produced with
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so-called "errata", which can cause it to deviate from the architecture
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under specific circumstances. For hardware produced by ARM, these
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errata are broadly classified into the following categories:
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2019-06-13 01:52:38 +08:00
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========== ========================================================
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Category A A critical error without a viable workaround.
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Category B A significant or critical error with an acceptable
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2015-11-17 22:45:47 +08:00
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workaround.
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2019-06-13 01:52:38 +08:00
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Category C A minor error that is not expected to occur under normal
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2015-11-17 22:45:47 +08:00
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operation.
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2019-06-13 01:52:38 +08:00
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========== ========================================================
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2015-11-17 22:45:47 +08:00
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For more information, consult one of the "Software Developers Errata
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Notice" documents available on infocenter.arm.com (registration
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required).
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As far as Linux is concerned, Category B errata may require some special
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treatment in the operating system. For example, avoiding a particular
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sequence of code, or configuring the processor in a particular way. A
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less common situation may require similar actions in order to declassify
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a Category A erratum into a Category C erratum. These are collectively
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known as "software workarounds" and are only required in the minority of
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cases (e.g. those cases that both require a non-secure workaround *and*
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can be triggered by Linux).
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For software workarounds that may adversely impact systems unaffected by
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the erratum in question, a Kconfig entry is added under "Kernel
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Features" -> "ARM errata workarounds via the alternatives framework".
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These are enabled by default and patched in at runtime when an affected
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CPU is detected. For less-intrusive workarounds, a Kconfig option is not
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available and the code is structured (preferably with a comment) in such
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a way that the erratum will not be hit.
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This approach can make it slightly onerous to determine exactly which
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errata are worked around in an arbitrary kernel source tree, so this
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file acts as a registry of software workarounds in the Linux Kernel and
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will be updated when new workarounds are committed and backported to
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stable kernels.
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2017-02-10 01:00:34 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-06-13 01:52:38 +08:00
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| Implementor | Component | Erratum ID | Kconfig |
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+================+=================+=================+=============================+
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clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability
The Allwinner A64 SoC is known[1] to have an unstable architectural
timer, which manifests itself most obviously in the time jumping forward
a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a
timer frequency of 24 MHz, implying that the time went slightly backward
(and this was interpreted by the kernel as it jumping forward and
wrapping around past the epoch).
Investigation revealed instability in the low bits of CNTVCT at the
point a high bit rolls over. This leads to power-of-two cycle forward
and backward jumps. (Testing shows that forward jumps are about twice as
likely as backward jumps.) Since the counter value returns to normal
after an indeterminate read, each "jump" really consists of both a
forward and backward jump from the software perspective.
Unless the kernel is trapping CNTVCT reads, a userspace program is able
to read the register in a loop faster than it changes. A test program
running on all 4 CPU cores that reported jumps larger than 100 ms was
run for 13.6 hours and reported the following:
Count | Event
-------+---------------------------
9940 | jumped backward 699ms
268 | jumped backward 1398ms
1 | jumped backward 2097ms
16020 | jumped forward 175ms
6443 | jumped forward 699ms
2976 | jumped forward 1398ms
9 | jumped forward 356516ms
9 | jumped forward 357215ms
4 | jumped forward 714430ms
1 | jumped forward 3578440ms
This works out to a jump larger than 100 ms about every 5.5 seconds on
each CPU core.
The largest jump (almost an hour!) was the following sequence of reads:
0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000
Note that the middle bits don't necessarily all read as all zeroes or
all ones during the anomalous behavior; however the low 10 bits checked
by the function in this patch have never been observed with any other
value.
Also note that smaller jumps are much more common, with backward jumps
of 2048 (2^11) cycles observed over 400 times per second on each core.
(Of course, this is partially explained by lower bits rolling over more
frequently.) Any one of these could have caused the 95 year time skip.
Similar anomalies were observed while reading CNTPCT (after patching the
kernel to allow reads from userspace). However, the CNTPCT jumps are
much less frequent, and only small jumps were observed. The same program
as before (except now reading CNTPCT) observed after 72 hours:
Count | Event
-------+---------------------------
17 | jumped backward 699ms
52 | jumped forward 175ms
2831 | jumped forward 699ms
5 | jumped forward 1398ms
Further investigation showed that the instability in CNTPCT/CNTVCT also
affected the respective timer's TVAL register. The following values were
observed immediately after writing CNVT_TVAL to 0x10000000:
CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
--------------------+------------+--------------------+-----------------
0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000
0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000
0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000
0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000
The pattern of errors in CNTV_TVAL seemed to depend on exactly which
value was written to it. For example, after writing 0x10101010:
CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error
--------------------+------------+--------------------+-----------------
0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000
0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000
0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000
0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000
0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000
0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000
I was also twice able to reproduce the issue covered by Allwinner's
workaround[4], that writing to TVAL sometimes fails, and both CVAL and
TVAL are left with entirely bogus values. One was the following values:
CNTVCT | CNTV_TVAL | CNTV_CVAL
--------------------+------------+--------------------------------------
0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past)
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
========================================================================
Because the CPU can read the CNTPCT/CNTVCT registers faster than they
change, performing two reads of the register and comparing the high bits
(like other workarounds) is not a workable solution. And because the
timer can jump both forward and backward, no pair of reads can
distinguish a good value from a bad one. The only way to guarantee a
good value from consecutive reads would be to read _three_ times, and
take the middle value only if the three values are 1) each unique and
2) increasing. This takes at minimum 3 counter cycles (125 ns), or more
if an anomaly is detected.
However, since there is a distinct pattern to the bad values, we can
optimize the common case (1022/1024 of the time) to a single read by
simply ignoring values that match the error pattern. This still takes no
more than 3 cycles in the worst case, and requires much less code. As an
additional safety check, we still limit the loop iteration to the number
of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods.
For the TVAL registers, the simple solution is to not use them. Instead,
read or write the CVAL and calculate the TVAL value in software.
Although the manufacturer is aware of at least part of the erratum[4],
there is no official name for it. For now, use the kernel-internal name
"UNKNOWN1".
[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9
[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/
[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26
[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2019-01-13 10:17:18 +08:00
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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A57 | #852523 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-01-09 22:36:34 +08:00
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| ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| ARM | Cortex-A72 | #853709 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-01-09 22:36:34 +08:00
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| ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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2017-03-21 01:18:06 +08:00
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2018-03-26 22:12:49 +08:00
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| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-05-23 18:24:50 +08:00
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| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2018-12-07 01:31:26 +08:00
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| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2018-11-19 19:27:28 +08:00
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| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-04-29 20:03:57 +08:00
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-12-16 19:56:31 +08:00
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| ARM | Cortex-A55 | #1530923 | ARM64_ERRATUM_1530923 |
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+----------------+-----------------+-----------------+-----------------------------+
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2019-05-23 18:24:50 +08:00
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-06-18 23:17:38 +08:00
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| ARM | Neoverse-N1 | #1349291 | N/A |
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2019-07-13 06:35:14 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-10-18 01:42:58 +08:00
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
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2019-05-23 18:24:50 +08:00
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| ARM | MMU-500 | #841119,826419 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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2019-11-01 05:47:23 +08:00
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| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
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+----------------+-----------------+-----------------+-----------------------------+
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2019-11-01 05:47:25 +08:00
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| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 |
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+----------------+-----------------+-----------------+-----------------------------+
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2019-11-01 05:47:23 +08:00
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2019-05-23 18:24:50 +08:00
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| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2020-03-11 19:56:49 +08:00
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| Cavium | ThunderX GICv3 | #38539 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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2019-06-13 01:52:38 +08:00
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2017-06-09 19:49:48 +08:00
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| Cavium | ThunderX Core | #30115 | CAVIUM_ERRATUM_30115 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| Cavium | ThunderX SMMUv2 | #27704 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-06-22 20:05:37 +08:00
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| Cavium | ThunderX2 SMMUv3| #74 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-06-23 21:34:36 +08:00
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| Cavium | ThunderX2 SMMUv3| #126 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-09-13 17:57:50 +08:00
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| Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 |
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+----------------+-----------------+-----------------+-----------------------------+
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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2017-02-10 01:00:34 +08:00
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| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-05-17 17:12:05 +08:00
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| Hisilicon | Hip0{6,7} | #161010701 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-08-01 00:29:33 +08:00
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| Hisilicon | Hip0{6,7} | #161010803 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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2017-07-29 04:20:37 +08:00
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| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-03-26 23:17:53 +08:00
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| Hisilicon | Hip08 SMMU PMCG | #162001800 | N/A |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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2017-12-14 06:19:37 +08:00
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| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2019-10-30 07:27:38 +08:00
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| Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-03-07 22:20:38 +08:00
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| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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2017-12-12 06:42:32 +08:00
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| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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2019-02-27 02:43:41 +08:00
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| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
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2019-06-13 01:52:38 +08:00
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+----------------+-----------------+-----------------+-----------------------------+
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