2017-08-28 14:47:43 +08:00
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/*
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* Interrupt descriptor table related code
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*
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* This file is licensed under the GPL V2
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*/
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#include <linux/interrupt.h>
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2017-08-28 14:47:49 +08:00
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#include <asm/traps.h>
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#include <asm/proto.h>
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2017-08-28 14:47:43 +08:00
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#include <asm/desc.h>
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2017-08-28 14:47:49 +08:00
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struct idt_data {
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unsigned int vector;
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unsigned int segment;
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struct idt_bits bits;
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const void *addr;
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};
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#define DPL0 0x0
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#define DPL3 0x3
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#define DEFAULT_STACK 0
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#define G(_vector, _addr, _ist, _type, _dpl, _segment) \
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{ \
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.vector = _vector, \
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.bits.ist = _ist, \
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.bits.type = _type, \
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.bits.dpl = _dpl, \
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.bits.p = 1, \
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.addr = _addr, \
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.segment = _segment, \
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}
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/* Interrupt gate */
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#define INTG(_vector, _addr) \
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G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
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/* System interrupt gate */
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#define SYSG(_vector, _addr) \
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G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
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/* Interrupt gate with interrupt stack */
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#define ISTG(_vector, _addr, _ist) \
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G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
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/* Task gate */
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#define TSKG(_vector, _gdt) \
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G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
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2017-08-28 14:47:50 +08:00
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/*
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* Early traps running on the DEFAULT_STACK because the other interrupt
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* stacks work only after cpu_init().
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*/
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static const __initdata struct idt_data early_idts[] = {
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INTG(X86_TRAP_DB, debug),
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SYSG(X86_TRAP_BP, int3),
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#ifdef CONFIG_X86_32
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INTG(X86_TRAP_PF, page_fault),
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#endif
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};
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#ifdef CONFIG_X86_64
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/*
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* Early traps running on the DEFAULT_STACK because the other interrupt
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* stacks work only after cpu_init().
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*/
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static const __initdata struct idt_data early_pf_idts[] = {
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INTG(X86_TRAP_PF, page_fault),
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};
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2017-08-28 14:47:51 +08:00
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/*
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* Override for the debug_idt. Same as the default, but with interrupt
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* stack set to DEFAULT_STACK (0). Required for NMI trap handling.
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*/
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static const __initdata struct idt_data dbg_idts[] = {
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INTG(X86_TRAP_DB, debug),
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INTG(X86_TRAP_BP, int3),
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};
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2017-08-28 14:47:50 +08:00
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#endif
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2017-08-28 14:47:43 +08:00
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/* Must be page-aligned because the real IDT is used in a fixmap. */
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gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
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struct desc_ptr idt_descr __ro_after_init = {
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2017-08-28 14:47:44 +08:00
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.size = (IDT_ENTRIES * 2 * sizeof(unsigned long)) - 1,
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2017-08-28 14:47:43 +08:00
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.address = (unsigned long) idt_table,
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};
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2017-08-28 14:47:44 +08:00
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#ifdef CONFIG_X86_64
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/* No need to be aligned, but done to keep all IDTs defined the same way. */
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gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
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2017-08-28 14:47:51 +08:00
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/*
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* Override for the debug_idt. Same as the default, but with interrupt
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* stack set to DEFAULT_STACK (0). Required for NMI trap handling.
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*/
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2017-08-28 14:47:43 +08:00
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const struct desc_ptr debug_idt_descr = {
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.size = IDT_ENTRIES * 16 - 1,
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.address = (unsigned long) debug_idt_table,
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};
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#endif
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2017-08-28 14:47:46 +08:00
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2017-08-28 14:47:49 +08:00
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static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
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{
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unsigned long addr = (unsigned long) d->addr;
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gate->offset_low = (u16) addr;
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gate->segment = (u16) d->segment;
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gate->bits = d->bits;
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gate->offset_middle = (u16) (addr >> 16);
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#ifdef CONFIG_X86_64
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gate->offset_high = (u32) (addr >> 32);
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gate->reserved = 0;
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#endif
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}
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static __init void
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idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size)
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{
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gate_desc desc;
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for (; size > 0; t++, size--) {
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idt_init_desc(&desc, t);
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set_bit(t->vector, used_vectors);
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write_idt_entry(idt, t->vector, &desc);
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}
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}
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2017-08-28 14:47:50 +08:00
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/**
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* idt_setup_early_traps - Initialize the idt table with early traps
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*
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* On X8664 these traps do not use interrupt stacks as they can't work
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* before cpu_init() is invoked and sets up TSS. The IST variants are
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* installed after that.
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*/
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void __init idt_setup_early_traps(void)
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{
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idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts));
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load_idt(&idt_descr);
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}
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#ifdef CONFIG_X86_64
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/**
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* idt_setup_early_pf - Initialize the idt table with early pagefault handler
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*
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* On X8664 this does not use interrupt stacks as they can't work before
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* cpu_init() is invoked and sets up TSS. The IST variant is installed
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* after that.
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*
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* FIXME: Why is 32bit and 64bit installing the PF handler at different
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* places in the early setup code?
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*/
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void __init idt_setup_early_pf(void)
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{
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idt_setup_from_table(idt_table, early_pf_idts,
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ARRAY_SIZE(early_pf_idts));
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}
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2017-08-28 14:47:51 +08:00
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/**
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* idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
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*/
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void __init idt_setup_debugidt_traps(void)
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{
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memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16);
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idt_setup_from_table(debug_idt_table, dbg_idts, ARRAY_SIZE(dbg_idts));
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}
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2017-08-28 14:47:50 +08:00
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#endif
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2017-08-28 14:47:47 +08:00
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/**
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* idt_setup_early_handler - Initializes the idt table with early handlers
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*/
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void __init idt_setup_early_handler(void)
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{
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int i;
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for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
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set_intr_gate(i, early_idt_handler_array[i]);
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2017-08-28 14:47:48 +08:00
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#ifdef CONFIG_X86_32
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for ( ; i < NR_VECTORS; i++)
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set_intr_gate(i, early_ignore_irq);
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#endif
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2017-08-28 14:47:47 +08:00
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load_idt(&idt_descr);
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}
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2017-08-28 14:47:46 +08:00
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/**
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* idt_invalidate - Invalidate interrupt descriptor table
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* @addr: The virtual address of the 'invalid' IDT
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*/
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void idt_invalidate(void *addr)
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{
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struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };
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load_idt(&idt);
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}
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