2010-05-15 03:05:26 +08:00
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/*
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* OMAP4 specific common source file.
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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2012-10-18 17:20:08 +08:00
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#include <linux/irq.h>
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2012-11-06 06:18:28 +08:00
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#include <linux/irqchip.h>
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2010-05-15 03:05:26 +08:00
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#include <linux/platform_device.h>
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2011-06-26 09:04:31 +08:00
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#include <linux/memblock.h>
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2012-08-28 08:43:01 +08:00
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/export.h>
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2012-12-28 03:10:24 +08:00
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#include <linux/irqchip/arm-gic.h>
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2010-05-15 03:05:26 +08:00
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#include <asm/hardware/cache-l2x0.h>
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2011-06-26 09:04:31 +08:00
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#include <asm/mach/map.h>
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2012-01-13 23:00:51 +08:00
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#include <asm/memblock.h>
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2012-10-18 17:20:08 +08:00
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#include <asm/smp_twd.h>
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2010-05-15 03:05:26 +08:00
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2012-09-21 02:41:16 +08:00
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#include "omap-wakeupgen.h"
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2012-09-01 01:59:07 +08:00
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#include "soc.h"
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2012-10-30 10:50:21 +08:00
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#include "iomap.h"
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2011-11-11 05:45:17 +08:00
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#include "common.h"
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2012-10-16 03:09:43 +08:00
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#include "mmc.h"
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2012-04-25 19:57:46 +08:00
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#include "hsmmc.h"
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2012-10-30 10:56:07 +08:00
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#include "prminst44xx.h"
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2012-10-30 10:57:39 +08:00
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#include "prcm_mpu44xx.h"
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2011-01-01 22:26:04 +08:00
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#include "omap4-sar-layout.h"
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2012-10-02 02:47:06 +08:00
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#include "omap-secure.h"
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2012-10-30 00:35:35 +08:00
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#include "sram.h"
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2010-05-15 03:05:26 +08:00
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#ifdef CONFIG_CACHE_L2X0
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2011-03-03 20:33:25 +08:00
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static void __iomem *l2cache_base;
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2010-05-15 03:05:26 +08:00
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#endif
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2011-01-01 22:26:04 +08:00
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static void __iomem *sar_ram_base;
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
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static void __iomem *gic_dist_base_addr;
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2012-10-18 17:20:08 +08:00
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static void __iomem *twd_base;
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#define IRQ_LOCALTIMER 29
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2011-01-01 22:26:04 +08:00
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2011-06-26 09:04:31 +08:00
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#ifdef CONFIG_OMAP4_ERRATA_I688
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/* Used to implement memory barrier on DRAM path */
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#define OMAP4_DRAM_BARRIER_VA 0xfe600000
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void __iomem *dram_sync, *sram_sync;
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2012-02-02 22:03:55 +08:00
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static phys_addr_t paddr;
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static u32 size;
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2011-06-26 09:04:31 +08:00
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void omap_bus_sync(void)
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{
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if (dram_sync && sram_sync) {
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writel_relaxed(readl_relaxed(dram_sync), dram_sync);
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writel_relaxed(readl_relaxed(sram_sync), sram_sync);
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isb();
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}
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}
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2012-03-02 19:01:18 +08:00
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EXPORT_SYMBOL(omap_bus_sync);
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2011-06-26 09:04:31 +08:00
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2012-02-02 22:03:55 +08:00
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/* Steal one page physical memory for barrier implementation */
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int __init omap_barrier_reserve_memblock(void)
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2011-06-26 09:04:31 +08:00
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{
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size = ALIGN(PAGE_SIZE, SZ_1M);
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2012-01-13 23:00:51 +08:00
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paddr = arm_memblock_steal(size, SZ_1M);
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2012-02-02 22:03:55 +08:00
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return 0;
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}
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void __init omap_barriers_init(void)
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{
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struct map_desc dram_io_desc[1];
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2011-06-26 09:04:31 +08:00
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dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
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dram_io_desc[0].pfn = __phys_to_pfn(paddr);
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dram_io_desc[0].length = size;
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dram_io_desc[0].type = MT_MEMORY_SO;
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iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
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dram_sync = (void __iomem *) dram_io_desc[0].virtual;
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sram_sync = (void __iomem *) OMAP4_SRAM_VA;
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pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
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(long long) paddr, dram_io_desc[0].virtual);
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}
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2012-02-02 22:03:55 +08:00
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#else
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void __init omap_barriers_init(void)
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{}
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2011-06-26 09:04:31 +08:00
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#endif
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2010-05-15 03:05:26 +08:00
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void __init gic_init_irq(void)
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{
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2011-11-16 01:22:45 +08:00
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void __iomem *omap_irq_base;
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2010-05-15 03:05:26 +08:00
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/* Static mapping, never released */
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gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
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BUG_ON(!gic_dist_base_addr);
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2012-10-18 17:20:08 +08:00
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twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
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BUG_ON(!twd_base);
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2010-05-15 03:05:26 +08:00
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/* Static mapping, never released */
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2011-05-17 18:51:26 +08:00
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omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
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BUG_ON(!omap_irq_base);
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2010-12-04 23:55:14 +08:00
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2010-06-17 00:49:47 +08:00
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omap_wakeupgen_init();
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2011-05-17 18:51:26 +08:00
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gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
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2010-05-15 03:05:26 +08:00
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}
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 17:20:05 +08:00
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void gic_dist_disable(void)
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{
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if (gic_dist_base_addr)
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__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
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}
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2012-10-18 17:20:08 +08:00
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bool gic_dist_disabled(void)
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{
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return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
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}
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void gic_timer_retrigger(void)
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{
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u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
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u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
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u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
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if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
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/*
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* The local timer interrupt got lost while the distributor was
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* disabled. Ack the pending interrupt, and retrigger it.
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*/
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pr_warn("%s: lost localtimer interrupt\n", __func__);
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__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
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if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
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__raw_writel(1, twd_base + TWD_TIMER_COUNTER);
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twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
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__raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
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}
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}
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}
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2010-05-15 03:05:26 +08:00
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#ifdef CONFIG_CACHE_L2X0
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2010-08-01 00:10:10 +08:00
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2011-03-03 20:33:25 +08:00
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void __iomem *omap4_get_l2cache_base(void)
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{
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return l2cache_base;
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}
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2010-08-01 00:10:10 +08:00
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static void omap4_l2x0_disable(void)
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{
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/* Disable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x0);
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}
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2011-02-22 17:00:44 +08:00
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static void omap4_l2x0_set_debug(unsigned long val)
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{
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/* Program PL310 L2 Cache controller debug register */
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omap_smc1(0x100, val);
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}
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2010-05-15 03:05:26 +08:00
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static int __init omap_l2_cache_init(void)
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{
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2010-11-20 01:31:03 +08:00
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u32 aux_ctrl = 0;
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2010-05-15 03:05:26 +08:00
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/*
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (!cpu_is_omap44xx())
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return -ENODEV;
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/* Static mapping, never released */
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l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
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2011-03-03 20:06:52 +08:00
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if (WARN_ON(!l2cache_base))
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return -ENOMEM;
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2010-05-15 03:05:26 +08:00
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/*
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2010-09-16 21:14:47 +08:00
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* 16-way associativity, parity disabled
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* Way size - 32KB (es1.0)
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* Way size - 64KB (es2.0 +)
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2010-05-15 03:05:26 +08:00
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*/
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2010-11-20 01:31:03 +08:00
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|
|
aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
|
|
|
|
(0x1 << 25) |
|
|
|
|
(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
|
|
|
|
(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
|
|
|
|
|
omap4: l2x0: enable instruction and data prefetching
Enabling L2 prefetching improves performance as shown on Panda
ES2.1 board with mem test, and it has measurable impact on
performances. I think we should consider it, even though it damages
"writes" a bit. (rebased to k.org)
Usually the prefetch is used at both levels together L1 + L2, however,
to enable the CP15 prefetch engines, these are under security, and on
GP devices, we cannot enable it(e.g. on PandaBoard). However, just
enabling PL310 prefetch seems to provide performance improvement,
as shown in the data below (from Ubuntu) and would be a great thing
to pull in.
What prefetch does is enable automatic next line prefetching. With this
enabled, whenever the PL310 receives a cachable read request, it
automatically prefetches the following cache line as well.
Measurement Data:
==
STOCK 10.10 WITHOUT PATCH
========================
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2aaad000 0x2b2ad000
copy libc 133 MB/s
copy Android v5 273 MB/s
copy Android NEON 235 MB/s
copy INT32 116 MB/s
copy ASM ARM 187 MB/s
copy ASM VLDM 64 204 MB/s
copy ASM VLDM 128 173 MB/s
copy ASM VLD1 216 MB/s
read ASM ARM 286 MB/s
read ASM VLDM 242 MB/s
read ASM VLD1 286 MB/s
write libc 1947 MB/s
write ASM ARM 1943 MB/s
write ASM VSTM 1942 MB/s
write ASM VST1 1935 MB/s
10.10 + PATCH
=============
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2ab17000 0x2b317000
copy libc 129 MB/s
copy Android v5 256 MB/s
copy Android NEON 356 MB/s
copy INT32 127 MB/s
copy ASM ARM 321 MB/s
copy ASM VLDM 64 337 MB/s
copy ASM VLDM 128 321 MB/s
copy ASM VLD1 350 MB/s
read ASM ARM 496 MB/s
read ASM VLDM 470 MB/s
read ASM VLD1 488 MB/s
write libc 1701 MB/s
write ASM ARM 1682 MB/s
write ASM VSTM 1693 MB/s
write ASM VST1 1681 MB/s
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-11-20 01:31:04 +08:00
|
|
|
if (omap_rev() == OMAP4430_REV_ES1_0) {
|
2010-11-20 01:31:03 +08:00
|
|
|
aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
|
omap4: l2x0: enable instruction and data prefetching
Enabling L2 prefetching improves performance as shown on Panda
ES2.1 board with mem test, and it has measurable impact on
performances. I think we should consider it, even though it damages
"writes" a bit. (rebased to k.org)
Usually the prefetch is used at both levels together L1 + L2, however,
to enable the CP15 prefetch engines, these are under security, and on
GP devices, we cannot enable it(e.g. on PandaBoard). However, just
enabling PL310 prefetch seems to provide performance improvement,
as shown in the data below (from Ubuntu) and would be a great thing
to pull in.
What prefetch does is enable automatic next line prefetching. With this
enabled, whenever the PL310 receives a cachable read request, it
automatically prefetches the following cache line as well.
Measurement Data:
==
STOCK 10.10 WITHOUT PATCH
========================
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2aaad000 0x2b2ad000
copy libc 133 MB/s
copy Android v5 273 MB/s
copy Android NEON 235 MB/s
copy INT32 116 MB/s
copy ASM ARM 187 MB/s
copy ASM VLDM 64 204 MB/s
copy ASM VLDM 128 173 MB/s
copy ASM VLD1 216 MB/s
read ASM ARM 286 MB/s
read ASM VLDM 242 MB/s
read ASM VLD1 286 MB/s
write libc 1947 MB/s
write ASM ARM 1943 MB/s
write ASM VSTM 1942 MB/s
write ASM VST1 1935 MB/s
10.10 + PATCH
=============
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2ab17000 0x2b317000
copy libc 129 MB/s
copy Android v5 256 MB/s
copy Android NEON 356 MB/s
copy INT32 127 MB/s
copy ASM ARM 321 MB/s
copy ASM VLDM 64 337 MB/s
copy ASM VLDM 128 321 MB/s
copy ASM VLD1 350 MB/s
read ASM ARM 496 MB/s
read ASM VLDM 470 MB/s
read ASM VLD1 488 MB/s
write libc 1701 MB/s
write ASM ARM 1682 MB/s
write ASM VSTM 1693 MB/s
write ASM VST1 1681 MB/s
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-11-20 01:31:04 +08:00
|
|
|
} else {
|
|
|
|
aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
|
2010-11-20 01:31:05 +08:00
|
|
|
(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
|
omap4: l2x0: enable instruction and data prefetching
Enabling L2 prefetching improves performance as shown on Panda
ES2.1 board with mem test, and it has measurable impact on
performances. I think we should consider it, even though it damages
"writes" a bit. (rebased to k.org)
Usually the prefetch is used at both levels together L1 + L2, however,
to enable the CP15 prefetch engines, these are under security, and on
GP devices, we cannot enable it(e.g. on PandaBoard). However, just
enabling PL310 prefetch seems to provide performance improvement,
as shown in the data below (from Ubuntu) and would be a great thing
to pull in.
What prefetch does is enable automatic next line prefetching. With this
enabled, whenever the PL310 receives a cachable read request, it
automatically prefetches the following cache line as well.
Measurement Data:
==
STOCK 10.10 WITHOUT PATCH
========================
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2aaad000 0x2b2ad000
copy libc 133 MB/s
copy Android v5 273 MB/s
copy Android NEON 235 MB/s
copy INT32 116 MB/s
copy ASM ARM 187 MB/s
copy ASM VLDM 64 204 MB/s
copy ASM VLDM 128 173 MB/s
copy ASM VLD1 216 MB/s
read ASM ARM 286 MB/s
read ASM VLDM 242 MB/s
read ASM VLD1 286 MB/s
write libc 1947 MB/s
write ASM ARM 1943 MB/s
write ASM VSTM 1942 MB/s
write ASM VST1 1935 MB/s
10.10 + PATCH
=============
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2ab17000 0x2b317000
copy libc 129 MB/s
copy Android v5 256 MB/s
copy Android NEON 356 MB/s
copy INT32 127 MB/s
copy ASM ARM 321 MB/s
copy ASM VLDM 64 337 MB/s
copy ASM VLDM 128 321 MB/s
copy ASM VLD1 350 MB/s
read ASM ARM 496 MB/s
read ASM VLDM 470 MB/s
read ASM VLD1 488 MB/s
write libc 1701 MB/s
write ASM ARM 1682 MB/s
write ASM VSTM 1693 MB/s
write ASM VST1 1681 MB/s
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-11-20 01:31:04 +08:00
|
|
|
(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
|
2010-11-20 01:31:06 +08:00
|
|
|
(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
|
|
|
|
(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
|
omap4: l2x0: enable instruction and data prefetching
Enabling L2 prefetching improves performance as shown on Panda
ES2.1 board with mem test, and it has measurable impact on
performances. I think we should consider it, even though it damages
"writes" a bit. (rebased to k.org)
Usually the prefetch is used at both levels together L1 + L2, however,
to enable the CP15 prefetch engines, these are under security, and on
GP devices, we cannot enable it(e.g. on PandaBoard). However, just
enabling PL310 prefetch seems to provide performance improvement,
as shown in the data below (from Ubuntu) and would be a great thing
to pull in.
What prefetch does is enable automatic next line prefetching. With this
enabled, whenever the PL310 receives a cachable read request, it
automatically prefetches the following cache line as well.
Measurement Data:
==
STOCK 10.10 WITHOUT PATCH
========================
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2aaad000 0x2b2ad000
copy libc 133 MB/s
copy Android v5 273 MB/s
copy Android NEON 235 MB/s
copy INT32 116 MB/s
copy ASM ARM 187 MB/s
copy ASM VLDM 64 204 MB/s
copy ASM VLDM 128 173 MB/s
copy ASM VLD1 216 MB/s
read ASM ARM 286 MB/s
read ASM VLDM 242 MB/s
read ASM VLD1 286 MB/s
write libc 1947 MB/s
write ASM ARM 1943 MB/s
write ASM VSTM 1942 MB/s
write ASM VST1 1935 MB/s
10.10 + PATCH
=============
~# ./memspeed
size 8388608 8192k 8M
offset 8388608, 0
buffers 0x2ab17000 0x2b317000
copy libc 129 MB/s
copy Android v5 256 MB/s
copy Android NEON 356 MB/s
copy INT32 127 MB/s
copy ASM ARM 321 MB/s
copy ASM VLDM 64 337 MB/s
copy ASM VLDM 128 321 MB/s
copy ASM VLD1 350 MB/s
read ASM ARM 496 MB/s
read ASM VLDM 470 MB/s
read ASM VLD1 488 MB/s
write libc 1701 MB/s
write ASM ARM 1682 MB/s
write ASM VSTM 1693 MB/s
write ASM VST1 1681 MB/s
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-11-20 01:31:04 +08:00
|
|
|
}
|
|
|
|
if (omap_rev() != OMAP4430_REV_ES1_0)
|
|
|
|
omap_smc1(0x109, aux_ctrl);
|
|
|
|
|
|
|
|
/* Enable PL310 L2 Cache controller */
|
|
|
|
omap_smc1(0x102, 0x1);
|
2010-11-20 01:31:03 +08:00
|
|
|
|
2012-07-04 20:27:34 +08:00
|
|
|
if (of_have_populated_dt())
|
|
|
|
l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
|
|
|
|
else
|
|
|
|
l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
|
2010-05-15 03:05:26 +08:00
|
|
|
|
2010-08-01 00:10:10 +08:00
|
|
|
/*
|
|
|
|
* Override default outer_cache.disable with a OMAP4
|
|
|
|
* specific one
|
|
|
|
*/
|
|
|
|
outer_cache.disable = omap4_l2x0_disable;
|
2011-02-22 17:00:44 +08:00
|
|
|
outer_cache.set_debug = omap4_l2x0_set_debug;
|
2010-08-01 00:10:10 +08:00
|
|
|
|
2010-05-15 03:05:26 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2013-01-12 03:24:18 +08:00
|
|
|
omap_early_initcall(omap_l2_cache_init);
|
2010-05-15 03:05:26 +08:00
|
|
|
#endif
|
2011-01-01 22:26:04 +08:00
|
|
|
|
|
|
|
void __iomem *omap4_get_sar_ram_base(void)
|
|
|
|
{
|
|
|
|
return sar_ram_base;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* SAR RAM used to save and restore the HW
|
|
|
|
* context in low power modes
|
|
|
|
*/
|
|
|
|
static int __init omap4_sar_ram_init(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* To avoid code running on other OMAPs in
|
|
|
|
* multi-omap builds
|
|
|
|
*/
|
|
|
|
if (!cpu_is_omap44xx())
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/* Static mapping, never released */
|
|
|
|
sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
|
|
|
|
if (WARN_ON(!sar_ram_base))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2013-01-12 03:24:18 +08:00
|
|
|
omap_early_initcall(omap4_sar_ram_init);
|
2012-04-25 19:57:46 +08:00
|
|
|
|
2012-06-05 19:01:06 +08:00
|
|
|
void __init omap_gic_of_init(void)
|
|
|
|
{
|
|
|
|
omap_wakeupgen_init();
|
2012-11-06 06:18:28 +08:00
|
|
|
irqchip_init();
|
2012-06-05 19:01:06 +08:00
|
|
|
}
|
|
|
|
|
2012-04-25 19:57:46 +08:00
|
|
|
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
|
|
|
|
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
|
|
|
|
{
|
|
|
|
int irq = 0;
|
|
|
|
struct platform_device *pdev = container_of(dev,
|
|
|
|
struct platform_device, dev);
|
|
|
|
struct omap_mmc_platform_data *pdata = dev->platform_data;
|
|
|
|
|
|
|
|
/* Setting MMC1 Card detect Irq */
|
|
|
|
if (pdev->id == 0) {
|
|
|
|
irq = twl6030_mmc_card_detect_config();
|
|
|
|
if (irq < 0) {
|
|
|
|
dev_err(dev, "%s: Error card detect config(%d)\n",
|
|
|
|
__func__, irq);
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
pdata->slots[0].card_detect_irq = irq;
|
|
|
|
pdata->slots[0].card_detect = twl6030_mmc_card_detect;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
|
|
|
|
{
|
|
|
|
struct omap_mmc_platform_data *pdata;
|
|
|
|
|
|
|
|
/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
|
|
|
|
if (!dev) {
|
|
|
|
pr_err("Failed %s\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
pdata = dev->platform_data;
|
|
|
|
pdata->init = omap4_twl6030_hsmmc_late_init;
|
|
|
|
}
|
|
|
|
|
|
|
|
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
|
|
|
{
|
|
|
|
struct omap2_hsmmc_info *c;
|
|
|
|
|
|
|
|
omap_hsmmc_init(controllers);
|
|
|
|
for (c = controllers; c->mmc; c++) {
|
|
|
|
/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
|
|
|
|
if (!c->pdev)
|
|
|
|
continue;
|
|
|
|
omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
2012-10-30 10:56:07 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* omap44xx_restart - trigger a software restart of the SoC
|
|
|
|
* @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
|
|
|
|
* @cmd: passed from the userspace program rebooting the system (if provided)
|
|
|
|
*
|
|
|
|
* Resets the SoC. For @cmd, see the 'reboot' syscall in
|
|
|
|
* kernel/sys.c. No return value.
|
|
|
|
*/
|
|
|
|
void omap44xx_restart(char mode, const char *cmd)
|
|
|
|
{
|
|
|
|
/* XXX Should save 'cmd' into scratchpad for use after reboot */
|
|
|
|
omap4_prminst_global_warm_sw_reset(); /* never returns */
|
|
|
|
while (1);
|
|
|
|
}
|
|
|
|
|