2012-03-05 19:49:30 +08:00
|
|
|
/*
|
|
|
|
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* SMP initialisation and IPI support
|
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|
|
* Based on arch/arm/kernel/smp.c
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*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2015-05-13 21:12:47 +08:00
|
|
|
#include <linux/acpi.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
#include <linux/delay.h>
|
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|
|
|
#include <linux/init.h>
|
|
|
|
|
#include <linux/spinlock.h>
|
2017-02-02 02:08:20 +08:00
|
|
|
#include <linux/sched/mm.h>
|
2017-02-09 01:51:36 +08:00
|
|
|
#include <linux/sched/hotplug.h>
|
2017-02-09 01:51:37 +08:00
|
|
|
#include <linux/sched/task_stack.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
#include <linux/interrupt.h>
|
|
|
|
|
#include <linux/cache.h>
|
|
|
|
|
#include <linux/profile.h>
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|
|
|
|
#include <linux/errno.h>
|
|
|
|
|
#include <linux/mm.h>
|
|
|
|
|
#include <linux/err.h>
|
|
|
|
|
#include <linux/cpu.h>
|
|
|
|
|
#include <linux/smp.h>
|
|
|
|
|
#include <linux/seq_file.h>
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|
|
|
|
#include <linux/irq.h>
|
|
|
|
|
#include <linux/percpu.h>
|
|
|
|
|
#include <linux/clockchips.h>
|
|
|
|
|
#include <linux/completion.h>
|
|
|
|
|
#include <linux/of.h>
|
2014-05-12 23:48:51 +08:00
|
|
|
#include <linux/irq_work.h>
|
2017-04-03 10:24:36 +08:00
|
|
|
#include <linux/kexec.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2014-11-14 23:54:08 +08:00
|
|
|
#include <asm/alternative.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
#include <asm/atomic.h>
|
|
|
|
|
#include <asm/cacheflush.h>
|
2014-07-16 23:32:44 +08:00
|
|
|
#include <asm/cpu.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
#include <asm/cputype.h>
|
2013-10-25 03:30:15 +08:00
|
|
|
#include <asm/cpu_ops.h>
|
2017-11-02 20:12:34 +08:00
|
|
|
#include <asm/daifflags.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
#include <asm/mmu_context.h>
|
2016-04-09 06:50:27 +08:00
|
|
|
#include <asm/numa.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
#include <asm/pgtable.h>
|
|
|
|
|
#include <asm/pgalloc.h>
|
|
|
|
|
#include <asm/processor.h>
|
2012-08-29 16:47:19 +08:00
|
|
|
#include <asm/smp_plat.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
#include <asm/sections.h>
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|
|
|
#include <asm/tlbflush.h>
|
|
|
|
|
#include <asm/ptrace.h>
|
2015-07-29 19:07:57 +08:00
|
|
|
#include <asm/virt.h>
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2014-07-26 04:05:32 +08:00
|
|
|
#define CREATE_TRACE_POINTS
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|
|
|
#include <trace/events/ipi.h>
|
|
|
|
|
|
arm64: make cpu number a percpu variable
In the absence of CONFIG_THREAD_INFO_IN_TASK, core code maintains
thread_info::cpu, and low-level architecture code can access this to
build raw_smp_processor_id(). With CONFIG_THREAD_INFO_IN_TASK, core code
maintains task_struct::cpu, which for reasons of hte header soup is not
accessible to low-level arch code.
Instead, we can maintain a percpu variable containing the cpu number.
For both the old and new implementation of raw_smp_processor_id(), we
read a syreg into a GPR, add an offset, and load the result. As the
offset is now larger, it may not be folded into the load, but otherwise
the assembly shouldn't change much.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-04 04:23:11 +08:00
|
|
|
DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number);
|
|
|
|
|
EXPORT_PER_CPU_SYMBOL(cpu_number);
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
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|
|
|
* as from 2.5, kernels no longer have an init_tasks structure
|
|
|
|
|
* so we need some other way of telling a new secondary core
|
|
|
|
|
* where to place its SVC stack
|
|
|
|
|
*/
|
|
|
|
|
struct secondary_data secondary_data;
|
2016-02-23 18:31:42 +08:00
|
|
|
/* Number of CPUs which aren't online, but looping in kernel text. */
|
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|
|
|
int cpus_stuck_in_kernel;
|
2012-03-05 19:49:30 +08:00
|
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|
|
enum ipi_msg_type {
|
|
|
|
|
IPI_RESCHEDULE,
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|
|
|
|
IPI_CALL_FUNC,
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|
|
|
|
IPI_CPU_STOP,
|
2017-04-03 10:24:36 +08:00
|
|
|
IPI_CPU_CRASH_STOP,
|
2013-09-04 17:55:17 +08:00
|
|
|
IPI_TIMER,
|
2014-05-12 23:48:51 +08:00
|
|
|
IPI_IRQ_WORK,
|
2016-01-26 19:10:38 +08:00
|
|
|
IPI_WAKEUP
|
2012-03-05 19:49:30 +08:00
|
|
|
};
|
|
|
|
|
|
2016-04-13 21:41:33 +08:00
|
|
|
#ifdef CONFIG_ARM64_VHE
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|
|
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|
|
/* Whether the boot CPU is running in HYP mode or not*/
|
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|
|
static bool boot_cpu_hyp_mode;
|
|
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|
|
|
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|
|
static inline void save_boot_cpu_run_el(void)
|
|
|
|
|
{
|
|
|
|
|
boot_cpu_hyp_mode = is_kernel_in_hyp_mode();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool is_boot_cpu_in_hyp_mode(void)
|
|
|
|
|
{
|
|
|
|
|
return boot_cpu_hyp_mode;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
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|
|
|
|
* Verify that a secondary CPU is running the kernel at the same
|
|
|
|
|
* EL as that of the boot CPU.
|
|
|
|
|
*/
|
|
|
|
|
void verify_cpu_run_el(void)
|
|
|
|
|
{
|
|
|
|
|
bool in_el2 = is_kernel_in_hyp_mode();
|
|
|
|
|
bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode();
|
|
|
|
|
|
|
|
|
|
if (in_el2 ^ boot_cpu_el2) {
|
|
|
|
|
pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n",
|
|
|
|
|
smp_processor_id(),
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|
|
|
|
in_el2 ? 2 : 1,
|
|
|
|
|
boot_cpu_el2 ? 2 : 1);
|
|
|
|
|
cpu_panic_kernel();
|
|
|
|
|
}
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|
|
|
|
}
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|
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|
|
|
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|
|
#else
|
|
|
|
|
static inline void save_boot_cpu_run_el(void) {}
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-02-23 18:31:42 +08:00
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
|
static int op_cpu_kill(unsigned int cpu);
|
|
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|
|
#else
|
|
|
|
|
static inline int op_cpu_kill(unsigned int cpu)
|
|
|
|
|
{
|
|
|
|
|
return -ENOSYS;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
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|
|
|
|
* Boot a secondary CPU, and assign it the specified idle task.
|
|
|
|
|
* This also gives us the initial stack to use for this CPU.
|
|
|
|
|
*/
|
2013-06-18 22:18:31 +08:00
|
|
|
static int boot_secondary(unsigned int cpu, struct task_struct *idle)
|
2012-03-05 19:49:30 +08:00
|
|
|
{
|
arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-25 03:30:16 +08:00
|
|
|
if (cpu_ops[cpu]->cpu_boot)
|
|
|
|
|
return cpu_ops[cpu]->cpu_boot(cpu);
|
2012-03-05 19:49:30 +08:00
|
|
|
|
arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-25 03:30:16 +08:00
|
|
|
return -EOPNOTSUPP;
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static DECLARE_COMPLETION(cpu_running);
|
|
|
|
|
|
2013-06-18 22:18:31 +08:00
|
|
|
int __cpu_up(unsigned int cpu, struct task_struct *idle)
|
2012-03-05 19:49:30 +08:00
|
|
|
{
|
|
|
|
|
int ret;
|
2016-02-23 18:31:42 +08:00
|
|
|
long status;
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We need to tell the secondary core where to find its stack and the
|
|
|
|
|
* page tables.
|
|
|
|
|
*/
|
arm64: split thread_info from task stack
This patch moves arm64's struct thread_info from the task stack into
task_struct. This protects thread_info from corruption in the case of
stack overflows, and makes its address harder to determine if stack
addresses are leaked, making a number of attacks more difficult. Precise
detection and handling of overflow is left for subsequent patches.
Largely, this involves changing code to store the task_struct in sp_el0,
and acquire the thread_info from the task struct. Core code now
implements current_thread_info(), and as noted in <linux/sched.h> this
relies on offsetof(task_struct, thread_info) == 0, enforced by core
code.
This change means that the 'tsk' register used in entry.S now points to
a task_struct, rather than a thread_info as it used to. To make this
clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets
appropriately updated to account for the structural change.
Userspace clobbers sp_el0, and we can no longer restore this from the
stack. Instead, the current task is cached in a per-cpu variable that we
can safely access from early assembly as interrupts are disabled (and we
are thus not preemptible).
Both secondary entry and idle are updated to stash the sp and task
pointer separately.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-04 04:23:13 +08:00
|
|
|
secondary_data.task = idle;
|
arm64: kernel: remove {THREAD,IRQ_STACK}_START_SP
For historical reasons, we leave the top 16 bytes of our task and IRQ
stacks unused, a practice used to ensure that the SP can always be
masked to find the base of the current stack (historically, where
thread_info could be found).
However, this is not necessary, as:
* When an exception is taken from a task stack, we decrement the SP by
S_FRAME_SIZE and stash the exception registers before we compare the
SP against the task stack. In such cases, the SP must be at least
S_FRAME_SIZE below the limit, and can be safely masked to determine
whether the task stack is in use.
* When transitioning to an IRQ stack, we'll place a dummy frame onto the
IRQ stack before enabling asynchronous exceptions, or executing code
we expect to trigger faults. Thus, if an exception is taken from the
IRQ stack, the SP must be at least 16 bytes below the limit.
* We no longer mask the SP to find the thread_info, which is now found
via sp_el0. Note that historically, the offset was critical to ensure
that cpu_switch_to() found the correct stack for new threads that
hadn't yet executed ret_from_fork().
Given that, this initial offset serves no purpose, and can be removed.
This brings us in-line with other architectures (e.g. x86) which do not
rely on this masking.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[Mark: rebase, kill THREAD_START_SP, commit msg additions]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
2017-07-21 00:15:45 +08:00
|
|
|
secondary_data.stack = task_stack_page(idle) + THREAD_SIZE;
|
2016-02-23 18:31:42 +08:00
|
|
|
update_cpu_boot_status(CPU_MMU_OFF);
|
2012-03-05 19:49:30 +08:00
|
|
|
__flush_dcache_area(&secondary_data, sizeof(secondary_data));
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now bring the CPU into our world.
|
|
|
|
|
*/
|
|
|
|
|
ret = boot_secondary(cpu, idle);
|
|
|
|
|
if (ret == 0) {
|
|
|
|
|
/*
|
|
|
|
|
* CPU was successfully started, wait for it to come online or
|
|
|
|
|
* time out.
|
|
|
|
|
*/
|
|
|
|
|
wait_for_completion_timeout(&cpu_running,
|
|
|
|
|
msecs_to_jiffies(1000));
|
|
|
|
|
|
|
|
|
|
if (!cpu_online(cpu)) {
|
|
|
|
|
pr_crit("CPU%u: failed to come online\n", cpu);
|
|
|
|
|
ret = -EIO;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
|
|
|
|
|
}
|
|
|
|
|
|
arm64: split thread_info from task stack
This patch moves arm64's struct thread_info from the task stack into
task_struct. This protects thread_info from corruption in the case of
stack overflows, and makes its address harder to determine if stack
addresses are leaked, making a number of attacks more difficult. Precise
detection and handling of overflow is left for subsequent patches.
Largely, this involves changing code to store the task_struct in sp_el0,
and acquire the thread_info from the task struct. Core code now
implements current_thread_info(), and as noted in <linux/sched.h> this
relies on offsetof(task_struct, thread_info) == 0, enforced by core
code.
This change means that the 'tsk' register used in entry.S now points to
a task_struct, rather than a thread_info as it used to. To make this
clear, the TI_* field offsets are renamed to TSK_TI_*, with asm-offsets
appropriately updated to account for the structural change.
Userspace clobbers sp_el0, and we can no longer restore this from the
stack. Instead, the current task is cached in a per-cpu variable that we
can safely access from early assembly as interrupts are disabled (and we
are thus not preemptible).
Both secondary entry and idle are updated to stash the sp and task
pointer separately.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: James Morse <james.morse@arm.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-04 04:23:13 +08:00
|
|
|
secondary_data.task = NULL;
|
2012-03-05 19:49:30 +08:00
|
|
|
secondary_data.stack = NULL;
|
2016-02-23 18:31:42 +08:00
|
|
|
status = READ_ONCE(secondary_data.status);
|
|
|
|
|
if (ret && status) {
|
|
|
|
|
|
|
|
|
|
if (status == CPU_MMU_OFF)
|
|
|
|
|
status = READ_ONCE(__early_cpu_boot_status);
|
|
|
|
|
|
|
|
|
|
switch (status) {
|
|
|
|
|
default:
|
|
|
|
|
pr_err("CPU%u: failed in unknown state : 0x%lx\n",
|
|
|
|
|
cpu, status);
|
|
|
|
|
break;
|
|
|
|
|
case CPU_KILL_ME:
|
|
|
|
|
if (!op_cpu_kill(cpu)) {
|
|
|
|
|
pr_crit("CPU%u: died during early boot\n", cpu);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
/* Fall through */
|
|
|
|
|
pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
|
|
|
|
|
case CPU_STUCK_IN_KERNEL:
|
|
|
|
|
pr_crit("CPU%u: is stuck in kernel\n", cpu);
|
|
|
|
|
cpus_stuck_in_kernel++;
|
|
|
|
|
break;
|
|
|
|
|
case CPU_PANIC_KERNEL:
|
|
|
|
|
panic("CPU%u detected unsupported configuration\n", cpu);
|
|
|
|
|
}
|
|
|
|
|
}
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This is the secondary CPU boot entry. We're using this CPUs
|
|
|
|
|
* idle thread stack, but a set of temporary page tables.
|
|
|
|
|
*/
|
2013-06-18 22:18:31 +08:00
|
|
|
asmlinkage void secondary_start_kernel(void)
|
2012-03-05 19:49:30 +08:00
|
|
|
{
|
2017-09-27 21:50:38 +08:00
|
|
|
u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
|
2012-03-05 19:49:30 +08:00
|
|
|
struct mm_struct *mm = &init_mm;
|
2016-11-04 04:23:10 +08:00
|
|
|
unsigned int cpu;
|
|
|
|
|
|
|
|
|
|
cpu = task_cpu(current);
|
|
|
|
|
set_my_cpu_offset(per_cpu_offset(cpu));
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* All kernel threads share the same mm context; grab a
|
|
|
|
|
* reference and switch to it.
|
|
|
|
|
*/
|
2017-02-28 06:30:07 +08:00
|
|
|
mmgrab(mm);
|
2012-03-05 19:49:30 +08:00
|
|
|
current->active_mm = mm;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TTBR0 is only used for the identity mapping at this stage. Make it
|
|
|
|
|
* point to zero page to avoid speculatively fetching new entries.
|
|
|
|
|
*/
|
2016-01-25 19:44:58 +08:00
|
|
|
cpu_uninstall_idmap();
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
preempt_disable();
|
|
|
|
|
trace_hardirqs_off();
|
|
|
|
|
|
arm64: Delay cpu feature capability checks
At the moment we run through the arm64_features capability list for
each CPU and set the capability if one of the CPU supports it. This
could be problematic in a heterogeneous system with differing capabilities.
Delay the CPU feature checks until all the enabled CPUs are up(i.e,
smp_cpus_done(), so that we can make better decisions based on the
overall system capability. Once we decide and advertise the capabilities
the alternatives can be applied. From this state, we cannot roll back
a feature to disabled based on the values from a new hotplugged CPU,
due to the runtime patching and other reasons. So, for all new CPUs,
we need to make sure that they have the established system capabilities.
Failing which, we bring the CPU down, preventing it from turning online.
Once the capabilities are decided, any new CPU booting up goes through
verification to ensure that it has all the enabled capabilities and also
invokes the respective enable() method on the CPU.
The CPU errata checks are not delayed and is still executed per-CPU
to detect the respective capabilities. If we ever come across a non-errata
capability that needs to be checked on each-CPU, we could introduce them via
a new capability table(or introduce a flag), which can be processed per CPU.
The next patch will make the feature checks use the system wide
safe value of a feature register.
NOTE: The enable() methods associated with the capability is scheduled
on all the CPUs (which is the only use case at the moment). If we need
a different type of 'enable()' which only needs to be run once on any CPU,
we should be able to handle that when needed.
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Tested-by: Dave Martin <Dave.Martin@arm.com>
[catalin.marinas@arm.com: static variable and coding style fixes]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-10-19 21:24:50 +08:00
|
|
|
/*
|
|
|
|
|
* If the system has established the capabilities, make sure
|
|
|
|
|
* this CPU ticks all of those. If it doesn't, the CPU will
|
|
|
|
|
* fail to come online.
|
|
|
|
|
*/
|
2016-09-09 21:07:10 +08:00
|
|
|
check_local_cpu_capabilities();
|
arm64: Delay cpu feature capability checks
At the moment we run through the arm64_features capability list for
each CPU and set the capability if one of the CPU supports it. This
could be problematic in a heterogeneous system with differing capabilities.
Delay the CPU feature checks until all the enabled CPUs are up(i.e,
smp_cpus_done(), so that we can make better decisions based on the
overall system capability. Once we decide and advertise the capabilities
the alternatives can be applied. From this state, we cannot roll back
a feature to disabled based on the values from a new hotplugged CPU,
due to the runtime patching and other reasons. So, for all new CPUs,
we need to make sure that they have the established system capabilities.
Failing which, we bring the CPU down, preventing it from turning online.
Once the capabilities are decided, any new CPU booting up goes through
verification to ensure that it has all the enabled capabilities and also
invokes the respective enable() method on the CPU.
The CPU errata checks are not delayed and is still executed per-CPU
to detect the respective capabilities. If we ever come across a non-errata
capability that needs to be checked on each-CPU, we could introduce them via
a new capability table(or introduce a flag), which can be processed per CPU.
The next patch will make the feature checks use the system wide
safe value of a feature register.
NOTE: The enable() methods associated with the capability is scheduled
on all the CPUs (which is the only use case at the moment). If we need
a different type of 'enable()' which only needs to be run once on any CPU,
we should be able to handle that when needed.
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Tested-by: Dave Martin <Dave.Martin@arm.com>
[catalin.marinas@arm.com: static variable and coding style fixes]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2015-10-19 21:24:50 +08:00
|
|
|
|
arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-25 03:30:16 +08:00
|
|
|
if (cpu_ops[cpu]->cpu_postboot)
|
|
|
|
|
cpu_ops[cpu]->cpu_postboot();
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2014-07-16 23:32:44 +08:00
|
|
|
/*
|
|
|
|
|
* Log the CPU info before it is marked online and might get read.
|
|
|
|
|
*/
|
|
|
|
|
cpuinfo_store_cpu();
|
|
|
|
|
|
2013-11-05 00:55:22 +08:00
|
|
|
/*
|
|
|
|
|
* Enable GIC and timers.
|
|
|
|
|
*/
|
|
|
|
|
notify_cpu_starting(cpu);
|
|
|
|
|
|
arm64: Call numa_store_cpu_info() earlier.
The wq_numa_init() function makes a private CPU to node map by calling
cpu_to_node() early in the boot process, before the non-boot CPUs are
brought online. Since the default implementation of cpu_to_node()
returns zero for CPUs that have never been brought online, the
workqueue system's view is that *all* CPUs are on node zero.
When the unbound workqueue for a non-zero node is created, the
tsk_cpus_allowed() for the worker threads is the empty set because
there are, in the view of the workqueue system, no CPUs on non-zero
nodes. The code in try_to_wake_up() using this empty cpumask ends up
using the cpumask empty set value of NR_CPUS as an index into the
per-CPU area pointer array, and gets garbage as it is one past the end
of the array. This results in:
[ 0.881970] Unable to handle kernel paging request at virtual address fffffb1008b926a4
[ 1.970095] pgd = fffffc00094b0000
[ 1.973530] [fffffb1008b926a4] *pgd=0000000000000000, *pud=0000000000000000, *pmd=0000000000000000
[ 1.982610] Internal error: Oops: 96000004 [#1] SMP
[ 1.987541] Modules linked in:
[ 1.990631] CPU: 48 PID: 295 Comm: cpuhp/48 Tainted: G W 4.8.0-rc6-preempt-vol+ #9
[ 1.999435] Hardware name: Cavium ThunderX CN88XX board (DT)
[ 2.005159] task: fffffe0fe89cc300 task.stack: fffffe0fe8b8c000
[ 2.011158] PC is at try_to_wake_up+0x194/0x34c
[ 2.015737] LR is at try_to_wake_up+0x150/0x34c
[ 2.020318] pc : [<fffffc00080e7468>] lr : [<fffffc00080e7424>] pstate: 600000c5
[ 2.027803] sp : fffffe0fe8b8fb10
[ 2.031149] x29: fffffe0fe8b8fb10 x28: 0000000000000000
[ 2.036522] x27: fffffc0008c63bc8 x26: 0000000000001000
[ 2.041896] x25: fffffc0008c63c80 x24: fffffc0008bfb200
[ 2.047270] x23: 00000000000000c0 x22: 0000000000000004
[ 2.052642] x21: fffffe0fe89d25bc x20: 0000000000001000
[ 2.058014] x19: fffffe0fe89d1d00 x18: 0000000000000000
[ 2.063386] x17: 0000000000000000 x16: 0000000000000000
[ 2.068760] x15: 0000000000000018 x14: 0000000000000000
[ 2.074133] x13: 0000000000000000 x12: 0000000000000000
[ 2.079505] x11: 0000000000000000 x10: 0000000000000000
[ 2.084879] x9 : 0000000000000000 x8 : 0000000000000000
[ 2.090251] x7 : 0000000000000040 x6 : 0000000000000000
[ 2.095621] x5 : ffffffffffffffff x4 : 0000000000000000
[ 2.100991] x3 : 0000000000000000 x2 : 0000000000000000
[ 2.106364] x1 : fffffc0008be4c24 x0 : ffffff0ffffada80
[ 2.111737]
[ 2.113236] Process cpuhp/48 (pid: 295, stack limit = 0xfffffe0fe8b8c020)
[ 2.120102] Stack: (0xfffffe0fe8b8fb10 to 0xfffffe0fe8b90000)
[ 2.125914] fb00: fffffe0fe8b8fb80 fffffc00080e7648
.
.
.
[ 2.442859] Call trace:
[ 2.445327] Exception stack(0xfffffe0fe8b8f940 to 0xfffffe0fe8b8fa70)
[ 2.451843] f940: fffffe0fe89d1d00 0000040000000000 fffffe0fe8b8fb10 fffffc00080e7468
[ 2.459767] f960: fffffe0fe8b8f980 fffffc00080e4958 ffffff0ff91ab200 fffffc00080e4b64
[ 2.467690] f980: fffffe0fe8b8f9d0 fffffc00080e515c fffffe0fe8b8fa80 0000000000000000
[ 2.475614] f9a0: fffffe0fe8b8f9d0 fffffc00080e58e4 fffffe0fe8b8fa80 0000000000000000
[ 2.483540] f9c0: fffffe0fe8d10000 0000000000000040 fffffe0fe8b8fa50 fffffc00080e5ac4
[ 2.491465] f9e0: ffffff0ffffada80 fffffc0008be4c24 0000000000000000 0000000000000000
[ 2.499387] fa00: 0000000000000000 ffffffffffffffff 0000000000000000 0000000000000040
[ 2.507309] fa20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 2.515233] fa40: 0000000000000000 0000000000000000 0000000000000000 0000000000000018
[ 2.523156] fa60: 0000000000000000 0000000000000000
[ 2.528089] [<fffffc00080e7468>] try_to_wake_up+0x194/0x34c
[ 2.533723] [<fffffc00080e7648>] wake_up_process+0x28/0x34
[ 2.539275] [<fffffc00080d3764>] create_worker+0x110/0x19c
[ 2.544824] [<fffffc00080d69dc>] alloc_unbound_pwq+0x3cc/0x4b0
[ 2.550724] [<fffffc00080d6bcc>] wq_update_unbound_numa+0x10c/0x1e4
[ 2.557066] [<fffffc00080d7d78>] workqueue_online_cpu+0x220/0x28c
[ 2.563234] [<fffffc00080bd288>] cpuhp_invoke_callback+0x6c/0x168
[ 2.569398] [<fffffc00080bdf74>] cpuhp_up_callbacks+0x44/0xe4
[ 2.575210] [<fffffc00080be194>] cpuhp_thread_fun+0x13c/0x148
[ 2.581027] [<fffffc00080dfbac>] smpboot_thread_fn+0x19c/0x1a8
[ 2.586929] [<fffffc00080dbd64>] kthread+0xdc/0xf0
[ 2.591776] [<fffffc0008083380>] ret_from_fork+0x10/0x50
[ 2.597147] Code: b00057e1 91304021 91005021 b8626822 (b8606821)
[ 2.603464] ---[ end trace 58c0cd36b88802bc ]---
[ 2.608138] Kernel panic - not syncing: Fatal exception
Fix by moving call to numa_store_cpu_info() for all CPUs into
smp_prepare_cpus(), which happens before wq_numa_init(). Since
smp_store_cpu_info() now contains only a single function call,
simplify by removing the function and out-lining its contents.
Suggested-by: Robert Richter <rric@kernel.org>
Fixes: 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")
Cc: <stable@vger.kernel.org> # 4.7.x-
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Robert Richter <rrichter@cavium.com>
Tested-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-09-21 02:46:35 +08:00
|
|
|
store_cpu_topology(cpu);
|
2014-03-04 15:51:17 +08:00
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
|
|
|
|
|
* OK, now it's safe to let the boot CPU continue. Wait for
|
|
|
|
|
* the CPU migration code to notice that the CPU is online
|
|
|
|
|
* before we continue.
|
|
|
|
|
*/
|
2017-09-27 21:50:38 +08:00
|
|
|
pr_info("CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n",
|
|
|
|
|
cpu, (unsigned long)mpidr,
|
|
|
|
|
read_cpuid_id());
|
2016-02-23 18:31:42 +08:00
|
|
|
update_cpu_boot_status(CPU_BOOT_SUCCESS);
|
2012-03-05 19:49:30 +08:00
|
|
|
set_cpu_online(cpu, true);
|
2012-11-08 01:00:05 +08:00
|
|
|
complete(&cpu_running);
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2017-11-02 20:12:36 +08:00
|
|
|
local_daif_restore(DAIF_PROCCTX);
|
2013-07-19 22:08:15 +08:00
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
|
|
|
|
|
* OK, it's off to the idle thread for us
|
|
|
|
|
*/
|
2016-02-27 02:43:40 +08:00
|
|
|
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
|
2013-10-25 03:30:18 +08:00
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
|
static int op_cpu_disable(unsigned int cpu)
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* If we don't have a cpu_die method, abort before we reach the point
|
|
|
|
|
* of no return. CPU0 may not have an cpu_ops, so test for it.
|
|
|
|
|
*/
|
|
|
|
|
if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We may need to abort a hot unplug for some other mechanism-specific
|
|
|
|
|
* reason.
|
|
|
|
|
*/
|
|
|
|
|
if (cpu_ops[cpu]->cpu_disable)
|
|
|
|
|
return cpu_ops[cpu]->cpu_disable(cpu);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* __cpu_disable runs on the processor to be shutdown.
|
|
|
|
|
*/
|
|
|
|
|
int __cpu_disable(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = op_cpu_disable(cpu);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Take this CPU offline. Once we clear this, we can't return,
|
|
|
|
|
* and we must not schedule until we're ready to give up the cpu.
|
|
|
|
|
*/
|
|
|
|
|
set_cpu_online(cpu, false);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* OK - migrate IRQs away from this CPU
|
|
|
|
|
*/
|
2015-09-24 17:32:14 +08:00
|
|
|
irq_migrate_all_off_this_cpu();
|
|
|
|
|
|
2013-10-25 03:30:18 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-05-07 22:18:36 +08:00
|
|
|
static int op_cpu_kill(unsigned int cpu)
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* If we have no means of synchronising with the dying CPU, then assume
|
|
|
|
|
* that it is really dead. We can only wait for an arbitrary length of
|
|
|
|
|
* time and hope that it's dead, so let's skip the wait and just hope.
|
|
|
|
|
*/
|
|
|
|
|
if (!cpu_ops[cpu]->cpu_kill)
|
2015-04-21 00:55:30 +08:00
|
|
|
return 0;
|
2014-05-07 22:18:36 +08:00
|
|
|
|
|
|
|
|
return cpu_ops[cpu]->cpu_kill(cpu);
|
|
|
|
|
}
|
|
|
|
|
|
2013-10-25 03:30:18 +08:00
|
|
|
/*
|
|
|
|
|
* called on the thread which is asking for a CPU to be shutdown -
|
|
|
|
|
* waits until shutdown has completed, or it is timed out.
|
|
|
|
|
*/
|
|
|
|
|
void __cpu_die(unsigned int cpu)
|
|
|
|
|
{
|
2015-04-21 00:55:30 +08:00
|
|
|
int err;
|
|
|
|
|
|
2015-05-13 05:50:05 +08:00
|
|
|
if (!cpu_wait_death(cpu, 5)) {
|
2013-10-25 03:30:18 +08:00
|
|
|
pr_crit("CPU%u: cpu didn't die\n", cpu);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
pr_notice("CPU%u: shutdown\n", cpu);
|
2014-05-07 22:18:36 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now that the dying CPU is beyond the point of no return w.r.t.
|
|
|
|
|
* in-kernel synchronisation, try to get the firwmare to help us to
|
|
|
|
|
* verify that it has really left the kernel before we consider
|
|
|
|
|
* clobbering anything it might still be using.
|
|
|
|
|
*/
|
2015-04-21 00:55:30 +08:00
|
|
|
err = op_cpu_kill(cpu);
|
|
|
|
|
if (err)
|
|
|
|
|
pr_warn("CPU%d may not have shut down cleanly: %d\n",
|
|
|
|
|
cpu, err);
|
2013-10-25 03:30:18 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Called from the idle thread for the CPU which has been shutdown.
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
void cpu_die(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
|
|
|
|
|
|
idle_task_exit();
|
|
|
|
|
|
2017-11-02 20:12:34 +08:00
|
|
|
local_daif_mask();
|
2013-10-25 03:30:18 +08:00
|
|
|
|
|
|
|
|
/* Tell __cpu_die() that this CPU is now safe to dispose of */
|
2015-05-13 05:50:05 +08:00
|
|
|
(void)cpu_report_death();
|
2013-10-25 03:30:18 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Actually shutdown the CPU. This must never fail. The specific hotplug
|
|
|
|
|
* mechanism must perform all required cache maintenance to ensure that
|
|
|
|
|
* no dirty lines are lost in the process of shutting down the CPU.
|
|
|
|
|
*/
|
|
|
|
|
cpu_ops[cpu]->cpu_die(cpu);
|
|
|
|
|
|
|
|
|
|
BUG();
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-02-23 18:31:41 +08:00
|
|
|
/*
|
|
|
|
|
* Kill the calling secondary CPU, early in bringup before it is turned
|
|
|
|
|
* online.
|
|
|
|
|
*/
|
|
|
|
|
void cpu_die_early(void)
|
|
|
|
|
{
|
|
|
|
|
int cpu = smp_processor_id();
|
|
|
|
|
|
|
|
|
|
pr_crit("CPU%d: will not boot\n", cpu);
|
|
|
|
|
|
|
|
|
|
/* Mark this CPU absent */
|
|
|
|
|
set_cpu_present(cpu, 0);
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
2016-02-23 18:31:42 +08:00
|
|
|
update_cpu_boot_status(CPU_KILL_ME);
|
2016-02-23 18:31:41 +08:00
|
|
|
/* Check if we can park ourselves */
|
|
|
|
|
if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
|
|
|
|
|
cpu_ops[cpu]->cpu_die(cpu);
|
|
|
|
|
#endif
|
2016-02-23 18:31:42 +08:00
|
|
|
update_cpu_boot_status(CPU_STUCK_IN_KERNEL);
|
2016-02-23 18:31:41 +08:00
|
|
|
|
|
|
|
|
cpu_park_loop();
|
|
|
|
|
}
|
|
|
|
|
|
2015-07-29 19:07:57 +08:00
|
|
|
static void __init hyp_mode_check(void)
|
|
|
|
|
{
|
|
|
|
|
if (is_hyp_mode_available())
|
|
|
|
|
pr_info("CPU: All CPU(s) started at EL2\n");
|
|
|
|
|
else if (is_hyp_mode_mismatched())
|
|
|
|
|
WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC,
|
|
|
|
|
"CPU: CPUs started in inconsistent modes");
|
|
|
|
|
else
|
|
|
|
|
pr_info("CPU: All CPU(s) started at EL1\n");
|
|
|
|
|
}
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
|
|
|
|
{
|
2013-08-31 01:06:48 +08:00
|
|
|
pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
|
2015-10-19 21:24:39 +08:00
|
|
|
setup_cpu_features();
|
2015-07-29 19:07:57 +08:00
|
|
|
hyp_mode_check();
|
|
|
|
|
apply_alternatives_all();
|
2017-03-10 04:52:01 +08:00
|
|
|
mark_linear_text_alias_ro();
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init smp_prepare_boot_cpu(void)
|
|
|
|
|
{
|
2016-07-21 18:12:55 +08:00
|
|
|
set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
|
2016-09-06 01:25:48 +08:00
|
|
|
/*
|
|
|
|
|
* Initialise the static keys early as they may be enabled by the
|
|
|
|
|
* cpufeature code.
|
|
|
|
|
*/
|
|
|
|
|
jump_label_init();
|
2015-10-19 21:24:40 +08:00
|
|
|
cpuinfo_store_boot_cpu();
|
2016-04-13 21:41:33 +08:00
|
|
|
save_boot_cpu_run_el();
|
2016-09-09 21:07:10 +08:00
|
|
|
/*
|
|
|
|
|
* Run the errata work around checks on the boot CPU, once we have
|
|
|
|
|
* initialised the cpu feature infrastructure from
|
|
|
|
|
* cpuinfo_store_boot_cpu() above.
|
|
|
|
|
*/
|
|
|
|
|
update_cpu_errata_workarounds();
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
|
2015-05-13 21:12:47 +08:00
|
|
|
static u64 __init of_get_cpu_mpidr(struct device_node *dn)
|
|
|
|
|
{
|
|
|
|
|
const __be32 *cell;
|
|
|
|
|
u64 hwid;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* A cpu node with missing "reg" property is
|
|
|
|
|
* considered invalid to build a cpu_logical_map
|
|
|
|
|
* entry.
|
|
|
|
|
*/
|
|
|
|
|
cell = of_get_property(dn, "reg", NULL);
|
|
|
|
|
if (!cell) {
|
2017-07-19 05:42:42 +08:00
|
|
|
pr_err("%pOF: missing reg property\n", dn);
|
2015-05-13 21:12:47 +08:00
|
|
|
return INVALID_HWID;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
hwid = of_read_number(cell, of_n_addr_cells(dn));
|
|
|
|
|
/*
|
|
|
|
|
* Non affinity bits must be set to 0 in the DT
|
|
|
|
|
*/
|
|
|
|
|
if (hwid & ~MPIDR_HWID_BITMASK) {
|
2017-07-19 05:42:42 +08:00
|
|
|
pr_err("%pOF: invalid reg property\n", dn);
|
2015-05-13 21:12:47 +08:00
|
|
|
return INVALID_HWID;
|
|
|
|
|
}
|
|
|
|
|
return hwid;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Duplicate MPIDRs are a recipe for disaster. Scan all initialized
|
|
|
|
|
* entries and check for duplicates. If any is found just ignore the
|
|
|
|
|
* cpu. cpu_logical_map was initialized to INVALID_HWID to avoid
|
|
|
|
|
* matching valid MPIDR values.
|
|
|
|
|
*/
|
|
|
|
|
static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
for (i = 1; (i < cpu) && (i < NR_CPUS); i++)
|
|
|
|
|
if (cpu_logical_map(i) == hwid)
|
|
|
|
|
return true;
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-13 21:12:46 +08:00
|
|
|
/*
|
|
|
|
|
* Initialize cpu operations for a logical cpu and
|
|
|
|
|
* set it in the possible mask on success
|
|
|
|
|
*/
|
|
|
|
|
static int __init smp_cpu_setup(int cpu)
|
|
|
|
|
{
|
|
|
|
|
if (cpu_read_ops(cpu))
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
if (cpu_ops[cpu]->cpu_init(cpu))
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
set_cpu_possible(cpu, true);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-13 21:12:47 +08:00
|
|
|
static bool bootcpu_valid __initdata;
|
|
|
|
|
static unsigned int cpu_count = 1;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ACPI
|
2017-04-11 16:39:54 +08:00
|
|
|
static struct acpi_madt_generic_interrupt cpu_madt_gicc[NR_CPUS];
|
|
|
|
|
|
|
|
|
|
struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu)
|
|
|
|
|
{
|
|
|
|
|
return &cpu_madt_gicc[cpu];
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-13 21:12:47 +08:00
|
|
|
/*
|
|
|
|
|
* acpi_map_gic_cpu_interface - parse processor MADT entry
|
|
|
|
|
*
|
|
|
|
|
* Carry out sanity checks on MADT processor entry and initialize
|
|
|
|
|
* cpu_logical_map on success
|
|
|
|
|
*/
|
|
|
|
|
static void __init
|
|
|
|
|
acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
|
|
|
|
|
{
|
|
|
|
|
u64 hwid = processor->arm_mpidr;
|
|
|
|
|
|
2015-07-03 15:29:06 +08:00
|
|
|
if (!(processor->flags & ACPI_MADT_ENABLED)) {
|
|
|
|
|
pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
|
2015-05-13 21:12:47 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2015-07-03 15:29:06 +08:00
|
|
|
if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) {
|
|
|
|
|
pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid);
|
2015-05-13 21:12:47 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (is_mpidr_duplicate(cpu_count, hwid)) {
|
|
|
|
|
pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check if GICC structure of boot CPU is available in the MADT */
|
|
|
|
|
if (cpu_logical_map(0) == hwid) {
|
|
|
|
|
if (bootcpu_valid) {
|
|
|
|
|
pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n",
|
|
|
|
|
hwid);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
bootcpu_valid = true;
|
2017-04-11 16:39:54 +08:00
|
|
|
cpu_madt_gicc[0] = *processor;
|
2016-10-17 22:18:48 +08:00
|
|
|
early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid));
|
2015-05-13 21:12:47 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu_count >= NR_CPUS)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* map the logical cpu id to cpu MPIDR */
|
|
|
|
|
cpu_logical_map(cpu_count) = hwid;
|
|
|
|
|
|
2017-04-11 16:39:54 +08:00
|
|
|
cpu_madt_gicc[cpu_count] = *processor;
|
|
|
|
|
|
2016-01-26 19:10:38 +08:00
|
|
|
/*
|
|
|
|
|
* Set-up the ACPI parking protocol cpu entries
|
|
|
|
|
* while initializing the cpu_logical_map to
|
|
|
|
|
* avoid parsing MADT entries multiple times for
|
|
|
|
|
* nothing (ie a valid cpu_logical_map entry should
|
|
|
|
|
* contain a valid parking protocol data set to
|
|
|
|
|
* initialize the cpu if the parking protocol is
|
|
|
|
|
* the only available enable method).
|
|
|
|
|
*/
|
|
|
|
|
acpi_set_mailbox_entry(cpu_count, processor);
|
|
|
|
|
|
2016-05-25 06:35:44 +08:00
|
|
|
early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count, hwid));
|
|
|
|
|
|
2015-05-13 21:12:47 +08:00
|
|
|
cpu_count++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __init
|
|
|
|
|
acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,
|
|
|
|
|
const unsigned long end)
|
|
|
|
|
{
|
|
|
|
|
struct acpi_madt_generic_interrupt *processor;
|
|
|
|
|
|
|
|
|
|
processor = (struct acpi_madt_generic_interrupt *)header;
|
2015-07-07 07:16:48 +08:00
|
|
|
if (BAD_MADT_GICC_ENTRY(processor, end))
|
2015-05-13 21:12:47 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
acpi_table_print_madt_entry(header);
|
|
|
|
|
|
|
|
|
|
acpi_map_gic_cpu_interface(processor);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
#define acpi_table_parse_madt(...) do { } while (0)
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
|
2012-08-29 16:47:19 +08:00
|
|
|
* Enumerate the possible CPU set from the device tree and build the
|
|
|
|
|
* cpu logical map array containing MPIDR values related to logical
|
|
|
|
|
* cpus. Assumes that cpu_logical_map(0) has already been initialized.
|
2012-03-05 19:49:30 +08:00
|
|
|
*/
|
2015-11-12 20:04:42 +08:00
|
|
|
static void __init of_parse_and_init_cpus(void)
|
2012-03-05 19:49:30 +08:00
|
|
|
{
|
2017-02-02 07:01:05 +08:00
|
|
|
struct device_node *dn;
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2017-02-02 07:01:05 +08:00
|
|
|
for_each_node_by_type(dn, "cpu") {
|
2015-05-13 21:12:47 +08:00
|
|
|
u64 hwid = of_get_cpu_mpidr(dn);
|
2012-08-29 16:47:19 +08:00
|
|
|
|
2015-05-13 21:12:47 +08:00
|
|
|
if (hwid == INVALID_HWID)
|
2012-08-29 16:47:19 +08:00
|
|
|
goto next;
|
|
|
|
|
|
2015-05-13 21:12:47 +08:00
|
|
|
if (is_mpidr_duplicate(cpu_count, hwid)) {
|
2017-07-19 05:42:42 +08:00
|
|
|
pr_err("%pOF: duplicate cpu reg properties in the DT\n",
|
|
|
|
|
dn);
|
2012-08-29 16:47:19 +08:00
|
|
|
goto next;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The numbering scheme requires that the boot CPU
|
|
|
|
|
* must be assigned logical id 0. Record it so that
|
|
|
|
|
* the logical map built from DT is validated and can
|
|
|
|
|
* be used.
|
|
|
|
|
*/
|
|
|
|
|
if (hwid == cpu_logical_map(0)) {
|
|
|
|
|
if (bootcpu_valid) {
|
2017-07-19 05:42:42 +08:00
|
|
|
pr_err("%pOF: duplicate boot cpu reg property in DT\n",
|
|
|
|
|
dn);
|
2012-08-29 16:47:19 +08:00
|
|
|
goto next;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bootcpu_valid = true;
|
2016-09-01 14:55:04 +08:00
|
|
|
early_map_cpu_to_node(0, of_node_to_nid(dn));
|
2012-08-29 16:47:19 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* cpu_logical_map has already been
|
|
|
|
|
* initialized and the boot cpu doesn't need
|
|
|
|
|
* the enable-method so continue without
|
|
|
|
|
* incrementing cpu.
|
|
|
|
|
*/
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-13 21:12:47 +08:00
|
|
|
if (cpu_count >= NR_CPUS)
|
2012-03-05 19:49:30 +08:00
|
|
|
goto next;
|
|
|
|
|
|
2012-08-29 16:47:19 +08:00
|
|
|
pr_debug("cpu logical map 0x%llx\n", hwid);
|
2015-05-13 21:12:47 +08:00
|
|
|
cpu_logical_map(cpu_count) = hwid;
|
2016-04-09 06:50:27 +08:00
|
|
|
|
|
|
|
|
early_map_cpu_to_node(cpu_count, of_node_to_nid(dn));
|
2012-03-05 19:49:30 +08:00
|
|
|
next:
|
2015-05-13 21:12:47 +08:00
|
|
|
cpu_count++;
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
2015-05-13 21:12:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Enumerate the possible CPU set from the device tree or ACPI and build the
|
|
|
|
|
* cpu logical map array containing MPIDR values related to logical
|
|
|
|
|
* cpus. Assumes that cpu_logical_map(0) has already been initialized.
|
|
|
|
|
*/
|
|
|
|
|
void __init smp_init_cpus(void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (acpi_disabled)
|
|
|
|
|
of_parse_and_init_cpus();
|
|
|
|
|
else
|
|
|
|
|
/*
|
|
|
|
|
* do a walk of MADT to determine how many CPUs
|
|
|
|
|
* we have including disabled CPUs, and get information
|
|
|
|
|
* we need for SMP init
|
|
|
|
|
*/
|
|
|
|
|
acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
|
|
|
|
|
acpi_parse_gic_cpu_interface, 0);
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2016-08-09 10:30:49 +08:00
|
|
|
if (cpu_count > nr_cpu_ids)
|
2017-09-09 07:14:18 +08:00
|
|
|
pr_warn("Number of cores (%d) exceeds configured maximum of %u - clipping\n",
|
2016-08-09 10:30:49 +08:00
|
|
|
cpu_count, nr_cpu_ids);
|
2012-08-29 16:47:19 +08:00
|
|
|
|
|
|
|
|
if (!bootcpu_valid) {
|
2015-05-13 21:12:47 +08:00
|
|
|
pr_err("missing boot CPU MPIDR, not enabling secondaries\n");
|
2012-08-29 16:47:19 +08:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
2015-05-13 21:12:46 +08:00
|
|
|
* We need to set the cpu_logical_map entries before enabling
|
|
|
|
|
* the cpus so that cpu processor description entries (DT cpu nodes
|
|
|
|
|
* and ACPI MADT entries) can be retrieved by matching the cpu hwid
|
|
|
|
|
* with entries in cpu_logical_map while initializing the cpus.
|
|
|
|
|
* If the cpu set-up fails, invalidate the cpu_logical_map entry.
|
2012-08-29 16:47:19 +08:00
|
|
|
*/
|
2016-08-09 10:30:49 +08:00
|
|
|
for (i = 1; i < nr_cpu_ids; i++) {
|
2015-05-13 21:12:46 +08:00
|
|
|
if (cpu_logical_map(i) != INVALID_HWID) {
|
|
|
|
|
if (smp_cpu_setup(i))
|
|
|
|
|
cpu_logical_map(i) = INVALID_HWID;
|
|
|
|
|
}
|
|
|
|
|
}
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
|
|
|
{
|
2013-10-25 03:30:15 +08:00
|
|
|
int err;
|
2016-04-22 19:25:35 +08:00
|
|
|
unsigned int cpu;
|
arm64: Call numa_store_cpu_info() earlier.
The wq_numa_init() function makes a private CPU to node map by calling
cpu_to_node() early in the boot process, before the non-boot CPUs are
brought online. Since the default implementation of cpu_to_node()
returns zero for CPUs that have never been brought online, the
workqueue system's view is that *all* CPUs are on node zero.
When the unbound workqueue for a non-zero node is created, the
tsk_cpus_allowed() for the worker threads is the empty set because
there are, in the view of the workqueue system, no CPUs on non-zero
nodes. The code in try_to_wake_up() using this empty cpumask ends up
using the cpumask empty set value of NR_CPUS as an index into the
per-CPU area pointer array, and gets garbage as it is one past the end
of the array. This results in:
[ 0.881970] Unable to handle kernel paging request at virtual address fffffb1008b926a4
[ 1.970095] pgd = fffffc00094b0000
[ 1.973530] [fffffb1008b926a4] *pgd=0000000000000000, *pud=0000000000000000, *pmd=0000000000000000
[ 1.982610] Internal error: Oops: 96000004 [#1] SMP
[ 1.987541] Modules linked in:
[ 1.990631] CPU: 48 PID: 295 Comm: cpuhp/48 Tainted: G W 4.8.0-rc6-preempt-vol+ #9
[ 1.999435] Hardware name: Cavium ThunderX CN88XX board (DT)
[ 2.005159] task: fffffe0fe89cc300 task.stack: fffffe0fe8b8c000
[ 2.011158] PC is at try_to_wake_up+0x194/0x34c
[ 2.015737] LR is at try_to_wake_up+0x150/0x34c
[ 2.020318] pc : [<fffffc00080e7468>] lr : [<fffffc00080e7424>] pstate: 600000c5
[ 2.027803] sp : fffffe0fe8b8fb10
[ 2.031149] x29: fffffe0fe8b8fb10 x28: 0000000000000000
[ 2.036522] x27: fffffc0008c63bc8 x26: 0000000000001000
[ 2.041896] x25: fffffc0008c63c80 x24: fffffc0008bfb200
[ 2.047270] x23: 00000000000000c0 x22: 0000000000000004
[ 2.052642] x21: fffffe0fe89d25bc x20: 0000000000001000
[ 2.058014] x19: fffffe0fe89d1d00 x18: 0000000000000000
[ 2.063386] x17: 0000000000000000 x16: 0000000000000000
[ 2.068760] x15: 0000000000000018 x14: 0000000000000000
[ 2.074133] x13: 0000000000000000 x12: 0000000000000000
[ 2.079505] x11: 0000000000000000 x10: 0000000000000000
[ 2.084879] x9 : 0000000000000000 x8 : 0000000000000000
[ 2.090251] x7 : 0000000000000040 x6 : 0000000000000000
[ 2.095621] x5 : ffffffffffffffff x4 : 0000000000000000
[ 2.100991] x3 : 0000000000000000 x2 : 0000000000000000
[ 2.106364] x1 : fffffc0008be4c24 x0 : ffffff0ffffada80
[ 2.111737]
[ 2.113236] Process cpuhp/48 (pid: 295, stack limit = 0xfffffe0fe8b8c020)
[ 2.120102] Stack: (0xfffffe0fe8b8fb10 to 0xfffffe0fe8b90000)
[ 2.125914] fb00: fffffe0fe8b8fb80 fffffc00080e7648
.
.
.
[ 2.442859] Call trace:
[ 2.445327] Exception stack(0xfffffe0fe8b8f940 to 0xfffffe0fe8b8fa70)
[ 2.451843] f940: fffffe0fe89d1d00 0000040000000000 fffffe0fe8b8fb10 fffffc00080e7468
[ 2.459767] f960: fffffe0fe8b8f980 fffffc00080e4958 ffffff0ff91ab200 fffffc00080e4b64
[ 2.467690] f980: fffffe0fe8b8f9d0 fffffc00080e515c fffffe0fe8b8fa80 0000000000000000
[ 2.475614] f9a0: fffffe0fe8b8f9d0 fffffc00080e58e4 fffffe0fe8b8fa80 0000000000000000
[ 2.483540] f9c0: fffffe0fe8d10000 0000000000000040 fffffe0fe8b8fa50 fffffc00080e5ac4
[ 2.491465] f9e0: ffffff0ffffada80 fffffc0008be4c24 0000000000000000 0000000000000000
[ 2.499387] fa00: 0000000000000000 ffffffffffffffff 0000000000000000 0000000000000040
[ 2.507309] fa20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 2.515233] fa40: 0000000000000000 0000000000000000 0000000000000000 0000000000000018
[ 2.523156] fa60: 0000000000000000 0000000000000000
[ 2.528089] [<fffffc00080e7468>] try_to_wake_up+0x194/0x34c
[ 2.533723] [<fffffc00080e7648>] wake_up_process+0x28/0x34
[ 2.539275] [<fffffc00080d3764>] create_worker+0x110/0x19c
[ 2.544824] [<fffffc00080d69dc>] alloc_unbound_pwq+0x3cc/0x4b0
[ 2.550724] [<fffffc00080d6bcc>] wq_update_unbound_numa+0x10c/0x1e4
[ 2.557066] [<fffffc00080d7d78>] workqueue_online_cpu+0x220/0x28c
[ 2.563234] [<fffffc00080bd288>] cpuhp_invoke_callback+0x6c/0x168
[ 2.569398] [<fffffc00080bdf74>] cpuhp_up_callbacks+0x44/0xe4
[ 2.575210] [<fffffc00080be194>] cpuhp_thread_fun+0x13c/0x148
[ 2.581027] [<fffffc00080dfbac>] smpboot_thread_fn+0x19c/0x1a8
[ 2.586929] [<fffffc00080dbd64>] kthread+0xdc/0xf0
[ 2.591776] [<fffffc0008083380>] ret_from_fork+0x10/0x50
[ 2.597147] Code: b00057e1 91304021 91005021 b8626822 (b8606821)
[ 2.603464] ---[ end trace 58c0cd36b88802bc ]---
[ 2.608138] Kernel panic - not syncing: Fatal exception
Fix by moving call to numa_store_cpu_info() for all CPUs into
smp_prepare_cpus(), which happens before wq_numa_init(). Since
smp_store_cpu_info() now contains only a single function call,
simplify by removing the function and out-lining its contents.
Suggested-by: Robert Richter <rric@kernel.org>
Fixes: 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")
Cc: <stable@vger.kernel.org> # 4.7.x-
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Robert Richter <rrichter@cavium.com>
Tested-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-09-21 02:46:35 +08:00
|
|
|
unsigned int this_cpu;
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2014-03-04 15:51:17 +08:00
|
|
|
init_cpu_topology();
|
|
|
|
|
|
arm64: Call numa_store_cpu_info() earlier.
The wq_numa_init() function makes a private CPU to node map by calling
cpu_to_node() early in the boot process, before the non-boot CPUs are
brought online. Since the default implementation of cpu_to_node()
returns zero for CPUs that have never been brought online, the
workqueue system's view is that *all* CPUs are on node zero.
When the unbound workqueue for a non-zero node is created, the
tsk_cpus_allowed() for the worker threads is the empty set because
there are, in the view of the workqueue system, no CPUs on non-zero
nodes. The code in try_to_wake_up() using this empty cpumask ends up
using the cpumask empty set value of NR_CPUS as an index into the
per-CPU area pointer array, and gets garbage as it is one past the end
of the array. This results in:
[ 0.881970] Unable to handle kernel paging request at virtual address fffffb1008b926a4
[ 1.970095] pgd = fffffc00094b0000
[ 1.973530] [fffffb1008b926a4] *pgd=0000000000000000, *pud=0000000000000000, *pmd=0000000000000000
[ 1.982610] Internal error: Oops: 96000004 [#1] SMP
[ 1.987541] Modules linked in:
[ 1.990631] CPU: 48 PID: 295 Comm: cpuhp/48 Tainted: G W 4.8.0-rc6-preempt-vol+ #9
[ 1.999435] Hardware name: Cavium ThunderX CN88XX board (DT)
[ 2.005159] task: fffffe0fe89cc300 task.stack: fffffe0fe8b8c000
[ 2.011158] PC is at try_to_wake_up+0x194/0x34c
[ 2.015737] LR is at try_to_wake_up+0x150/0x34c
[ 2.020318] pc : [<fffffc00080e7468>] lr : [<fffffc00080e7424>] pstate: 600000c5
[ 2.027803] sp : fffffe0fe8b8fb10
[ 2.031149] x29: fffffe0fe8b8fb10 x28: 0000000000000000
[ 2.036522] x27: fffffc0008c63bc8 x26: 0000000000001000
[ 2.041896] x25: fffffc0008c63c80 x24: fffffc0008bfb200
[ 2.047270] x23: 00000000000000c0 x22: 0000000000000004
[ 2.052642] x21: fffffe0fe89d25bc x20: 0000000000001000
[ 2.058014] x19: fffffe0fe89d1d00 x18: 0000000000000000
[ 2.063386] x17: 0000000000000000 x16: 0000000000000000
[ 2.068760] x15: 0000000000000018 x14: 0000000000000000
[ 2.074133] x13: 0000000000000000 x12: 0000000000000000
[ 2.079505] x11: 0000000000000000 x10: 0000000000000000
[ 2.084879] x9 : 0000000000000000 x8 : 0000000000000000
[ 2.090251] x7 : 0000000000000040 x6 : 0000000000000000
[ 2.095621] x5 : ffffffffffffffff x4 : 0000000000000000
[ 2.100991] x3 : 0000000000000000 x2 : 0000000000000000
[ 2.106364] x1 : fffffc0008be4c24 x0 : ffffff0ffffada80
[ 2.111737]
[ 2.113236] Process cpuhp/48 (pid: 295, stack limit = 0xfffffe0fe8b8c020)
[ 2.120102] Stack: (0xfffffe0fe8b8fb10 to 0xfffffe0fe8b90000)
[ 2.125914] fb00: fffffe0fe8b8fb80 fffffc00080e7648
.
.
.
[ 2.442859] Call trace:
[ 2.445327] Exception stack(0xfffffe0fe8b8f940 to 0xfffffe0fe8b8fa70)
[ 2.451843] f940: fffffe0fe89d1d00 0000040000000000 fffffe0fe8b8fb10 fffffc00080e7468
[ 2.459767] f960: fffffe0fe8b8f980 fffffc00080e4958 ffffff0ff91ab200 fffffc00080e4b64
[ 2.467690] f980: fffffe0fe8b8f9d0 fffffc00080e515c fffffe0fe8b8fa80 0000000000000000
[ 2.475614] f9a0: fffffe0fe8b8f9d0 fffffc00080e58e4 fffffe0fe8b8fa80 0000000000000000
[ 2.483540] f9c0: fffffe0fe8d10000 0000000000000040 fffffe0fe8b8fa50 fffffc00080e5ac4
[ 2.491465] f9e0: ffffff0ffffada80 fffffc0008be4c24 0000000000000000 0000000000000000
[ 2.499387] fa00: 0000000000000000 ffffffffffffffff 0000000000000000 0000000000000040
[ 2.507309] fa20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 2.515233] fa40: 0000000000000000 0000000000000000 0000000000000000 0000000000000018
[ 2.523156] fa60: 0000000000000000 0000000000000000
[ 2.528089] [<fffffc00080e7468>] try_to_wake_up+0x194/0x34c
[ 2.533723] [<fffffc00080e7648>] wake_up_process+0x28/0x34
[ 2.539275] [<fffffc00080d3764>] create_worker+0x110/0x19c
[ 2.544824] [<fffffc00080d69dc>] alloc_unbound_pwq+0x3cc/0x4b0
[ 2.550724] [<fffffc00080d6bcc>] wq_update_unbound_numa+0x10c/0x1e4
[ 2.557066] [<fffffc00080d7d78>] workqueue_online_cpu+0x220/0x28c
[ 2.563234] [<fffffc00080bd288>] cpuhp_invoke_callback+0x6c/0x168
[ 2.569398] [<fffffc00080bdf74>] cpuhp_up_callbacks+0x44/0xe4
[ 2.575210] [<fffffc00080be194>] cpuhp_thread_fun+0x13c/0x148
[ 2.581027] [<fffffc00080dfbac>] smpboot_thread_fn+0x19c/0x1a8
[ 2.586929] [<fffffc00080dbd64>] kthread+0xdc/0xf0
[ 2.591776] [<fffffc0008083380>] ret_from_fork+0x10/0x50
[ 2.597147] Code: b00057e1 91304021 91005021 b8626822 (b8606821)
[ 2.603464] ---[ end trace 58c0cd36b88802bc ]---
[ 2.608138] Kernel panic - not syncing: Fatal exception
Fix by moving call to numa_store_cpu_info() for all CPUs into
smp_prepare_cpus(), which happens before wq_numa_init(). Since
smp_store_cpu_info() now contains only a single function call,
simplify by removing the function and out-lining its contents.
Suggested-by: Robert Richter <rric@kernel.org>
Fixes: 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")
Cc: <stable@vger.kernel.org> # 4.7.x-
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Robert Richter <rrichter@cavium.com>
Tested-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-09-21 02:46:35 +08:00
|
|
|
this_cpu = smp_processor_id();
|
|
|
|
|
store_cpu_topology(this_cpu);
|
|
|
|
|
numa_store_cpu_info(this_cpu);
|
2014-03-04 15:51:17 +08:00
|
|
|
|
2016-07-21 18:15:27 +08:00
|
|
|
/*
|
|
|
|
|
* If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
|
|
|
|
|
* secondary CPUs present.
|
|
|
|
|
*/
|
|
|
|
|
if (max_cpus == 0)
|
|
|
|
|
return;
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
|
|
|
|
|
* Initialise the present map (which describes the set of CPUs
|
|
|
|
|
* actually populated at the present time) and release the
|
|
|
|
|
* secondaries from the bootloader.
|
|
|
|
|
*/
|
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
|
|
|
|
arm64: make cpu number a percpu variable
In the absence of CONFIG_THREAD_INFO_IN_TASK, core code maintains
thread_info::cpu, and low-level architecture code can access this to
build raw_smp_processor_id(). With CONFIG_THREAD_INFO_IN_TASK, core code
maintains task_struct::cpu, which for reasons of hte header soup is not
accessible to low-level arch code.
Instead, we can maintain a percpu variable containing the cpu number.
For both the old and new implementation of raw_smp_processor_id(), we
read a syreg into a GPR, add an offset, and load the result. As the
offset is now larger, it may not be folded into the load, but otherwise
the assembly shouldn't change much.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-04 04:23:11 +08:00
|
|
|
per_cpu(cpu_number, cpu) = cpu;
|
|
|
|
|
|
2013-01-02 23:24:22 +08:00
|
|
|
if (cpu == smp_processor_id())
|
|
|
|
|
continue;
|
|
|
|
|
|
2013-10-25 03:30:15 +08:00
|
|
|
if (!cpu_ops[cpu])
|
2012-03-05 19:49:30 +08:00
|
|
|
continue;
|
|
|
|
|
|
2013-10-25 03:30:15 +08:00
|
|
|
err = cpu_ops[cpu]->cpu_prepare(cpu);
|
2013-01-02 23:24:22 +08:00
|
|
|
if (err)
|
|
|
|
|
continue;
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
set_cpu_present(cpu, true);
|
arm64: Call numa_store_cpu_info() earlier.
The wq_numa_init() function makes a private CPU to node map by calling
cpu_to_node() early in the boot process, before the non-boot CPUs are
brought online. Since the default implementation of cpu_to_node()
returns zero for CPUs that have never been brought online, the
workqueue system's view is that *all* CPUs are on node zero.
When the unbound workqueue for a non-zero node is created, the
tsk_cpus_allowed() for the worker threads is the empty set because
there are, in the view of the workqueue system, no CPUs on non-zero
nodes. The code in try_to_wake_up() using this empty cpumask ends up
using the cpumask empty set value of NR_CPUS as an index into the
per-CPU area pointer array, and gets garbage as it is one past the end
of the array. This results in:
[ 0.881970] Unable to handle kernel paging request at virtual address fffffb1008b926a4
[ 1.970095] pgd = fffffc00094b0000
[ 1.973530] [fffffb1008b926a4] *pgd=0000000000000000, *pud=0000000000000000, *pmd=0000000000000000
[ 1.982610] Internal error: Oops: 96000004 [#1] SMP
[ 1.987541] Modules linked in:
[ 1.990631] CPU: 48 PID: 295 Comm: cpuhp/48 Tainted: G W 4.8.0-rc6-preempt-vol+ #9
[ 1.999435] Hardware name: Cavium ThunderX CN88XX board (DT)
[ 2.005159] task: fffffe0fe89cc300 task.stack: fffffe0fe8b8c000
[ 2.011158] PC is at try_to_wake_up+0x194/0x34c
[ 2.015737] LR is at try_to_wake_up+0x150/0x34c
[ 2.020318] pc : [<fffffc00080e7468>] lr : [<fffffc00080e7424>] pstate: 600000c5
[ 2.027803] sp : fffffe0fe8b8fb10
[ 2.031149] x29: fffffe0fe8b8fb10 x28: 0000000000000000
[ 2.036522] x27: fffffc0008c63bc8 x26: 0000000000001000
[ 2.041896] x25: fffffc0008c63c80 x24: fffffc0008bfb200
[ 2.047270] x23: 00000000000000c0 x22: 0000000000000004
[ 2.052642] x21: fffffe0fe89d25bc x20: 0000000000001000
[ 2.058014] x19: fffffe0fe89d1d00 x18: 0000000000000000
[ 2.063386] x17: 0000000000000000 x16: 0000000000000000
[ 2.068760] x15: 0000000000000018 x14: 0000000000000000
[ 2.074133] x13: 0000000000000000 x12: 0000000000000000
[ 2.079505] x11: 0000000000000000 x10: 0000000000000000
[ 2.084879] x9 : 0000000000000000 x8 : 0000000000000000
[ 2.090251] x7 : 0000000000000040 x6 : 0000000000000000
[ 2.095621] x5 : ffffffffffffffff x4 : 0000000000000000
[ 2.100991] x3 : 0000000000000000 x2 : 0000000000000000
[ 2.106364] x1 : fffffc0008be4c24 x0 : ffffff0ffffada80
[ 2.111737]
[ 2.113236] Process cpuhp/48 (pid: 295, stack limit = 0xfffffe0fe8b8c020)
[ 2.120102] Stack: (0xfffffe0fe8b8fb10 to 0xfffffe0fe8b90000)
[ 2.125914] fb00: fffffe0fe8b8fb80 fffffc00080e7648
.
.
.
[ 2.442859] Call trace:
[ 2.445327] Exception stack(0xfffffe0fe8b8f940 to 0xfffffe0fe8b8fa70)
[ 2.451843] f940: fffffe0fe89d1d00 0000040000000000 fffffe0fe8b8fb10 fffffc00080e7468
[ 2.459767] f960: fffffe0fe8b8f980 fffffc00080e4958 ffffff0ff91ab200 fffffc00080e4b64
[ 2.467690] f980: fffffe0fe8b8f9d0 fffffc00080e515c fffffe0fe8b8fa80 0000000000000000
[ 2.475614] f9a0: fffffe0fe8b8f9d0 fffffc00080e58e4 fffffe0fe8b8fa80 0000000000000000
[ 2.483540] f9c0: fffffe0fe8d10000 0000000000000040 fffffe0fe8b8fa50 fffffc00080e5ac4
[ 2.491465] f9e0: ffffff0ffffada80 fffffc0008be4c24 0000000000000000 0000000000000000
[ 2.499387] fa00: 0000000000000000 ffffffffffffffff 0000000000000000 0000000000000040
[ 2.507309] fa20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 2.515233] fa40: 0000000000000000 0000000000000000 0000000000000000 0000000000000018
[ 2.523156] fa60: 0000000000000000 0000000000000000
[ 2.528089] [<fffffc00080e7468>] try_to_wake_up+0x194/0x34c
[ 2.533723] [<fffffc00080e7648>] wake_up_process+0x28/0x34
[ 2.539275] [<fffffc00080d3764>] create_worker+0x110/0x19c
[ 2.544824] [<fffffc00080d69dc>] alloc_unbound_pwq+0x3cc/0x4b0
[ 2.550724] [<fffffc00080d6bcc>] wq_update_unbound_numa+0x10c/0x1e4
[ 2.557066] [<fffffc00080d7d78>] workqueue_online_cpu+0x220/0x28c
[ 2.563234] [<fffffc00080bd288>] cpuhp_invoke_callback+0x6c/0x168
[ 2.569398] [<fffffc00080bdf74>] cpuhp_up_callbacks+0x44/0xe4
[ 2.575210] [<fffffc00080be194>] cpuhp_thread_fun+0x13c/0x148
[ 2.581027] [<fffffc00080dfbac>] smpboot_thread_fn+0x19c/0x1a8
[ 2.586929] [<fffffc00080dbd64>] kthread+0xdc/0xf0
[ 2.591776] [<fffffc0008083380>] ret_from_fork+0x10/0x50
[ 2.597147] Code: b00057e1 91304021 91005021 b8626822 (b8606821)
[ 2.603464] ---[ end trace 58c0cd36b88802bc ]---
[ 2.608138] Kernel panic - not syncing: Fatal exception
Fix by moving call to numa_store_cpu_info() for all CPUs into
smp_prepare_cpus(), which happens before wq_numa_init(). Since
smp_store_cpu_info() now contains only a single function call,
simplify by removing the function and out-lining its contents.
Suggested-by: Robert Richter <rric@kernel.org>
Fixes: 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")
Cc: <stable@vger.kernel.org> # 4.7.x-
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Robert Richter <rrichter@cavium.com>
Tested-by: Yisheng Xie <xieyisheng1@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-09-21 02:46:35 +08:00
|
|
|
numa_store_cpu_info(cpu);
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-08-17 00:48:05 +08:00
|
|
|
void (*__smp_cross_call)(const struct cpumask *, unsigned int);
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
|
|
|
|
|
{
|
2014-07-26 04:05:32 +08:00
|
|
|
__smp_cross_call = fn;
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
|
2014-07-26 04:05:32 +08:00
|
|
|
static const char *ipi_types[NR_IPI] __tracepoint_string = {
|
|
|
|
|
#define S(x,s) [x] = s
|
2012-03-05 19:49:30 +08:00
|
|
|
S(IPI_RESCHEDULE, "Rescheduling interrupts"),
|
|
|
|
|
S(IPI_CALL_FUNC, "Function call interrupts"),
|
|
|
|
|
S(IPI_CPU_STOP, "CPU stop interrupts"),
|
2017-04-03 10:24:36 +08:00
|
|
|
S(IPI_CPU_CRASH_STOP, "CPU stop (for crash dump) interrupts"),
|
2013-09-04 17:55:17 +08:00
|
|
|
S(IPI_TIMER, "Timer broadcast interrupts"),
|
2014-05-12 23:48:51 +08:00
|
|
|
S(IPI_IRQ_WORK, "IRQ work interrupts"),
|
2016-01-26 19:10:38 +08:00
|
|
|
S(IPI_WAKEUP, "CPU wake-up interrupts"),
|
2012-03-05 19:49:30 +08:00
|
|
|
};
|
|
|
|
|
|
2014-07-26 04:05:32 +08:00
|
|
|
static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
|
|
|
|
|
{
|
|
|
|
|
trace_ipi_raise(target, ipi_types[ipinr]);
|
|
|
|
|
__smp_cross_call(target, ipinr);
|
|
|
|
|
}
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
void show_ipi_list(struct seq_file *p, int prec)
|
|
|
|
|
{
|
|
|
|
|
unsigned int cpu, i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < NR_IPI; i++) {
|
2014-07-26 04:05:32 +08:00
|
|
|
seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
|
2012-03-05 19:49:30 +08:00
|
|
|
prec >= 4 ? " " : "");
|
2013-11-07 23:25:44 +08:00
|
|
|
for_each_online_cpu(cpu)
|
2012-03-05 19:49:30 +08:00
|
|
|
seq_printf(p, "%10u ",
|
|
|
|
|
__get_irq_stat(cpu, ipi_irqs[i]));
|
|
|
|
|
seq_printf(p, " %s\n", ipi_types[i]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
u64 smp_irq_stat_cpu(unsigned int cpu)
|
|
|
|
|
{
|
|
|
|
|
u64 sum = 0;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < NR_IPI; i++)
|
|
|
|
|
sum += __get_irq_stat(cpu, ipi_irqs[i]);
|
|
|
|
|
|
|
|
|
|
return sum;
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-26 04:05:32 +08:00
|
|
|
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
|
|
|
|
|
{
|
|
|
|
|
smp_cross_call(mask, IPI_CALL_FUNC);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void arch_send_call_function_single_ipi(int cpu)
|
|
|
|
|
{
|
2015-01-23 13:36:42 +08:00
|
|
|
smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC);
|
2014-07-26 04:05:32 +08:00
|
|
|
}
|
|
|
|
|
|
2016-01-26 19:10:38 +08:00
|
|
|
#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
|
|
|
|
|
void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
|
|
|
|
|
{
|
|
|
|
|
smp_cross_call(mask, IPI_WAKEUP);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-07-26 04:05:32 +08:00
|
|
|
#ifdef CONFIG_IRQ_WORK
|
|
|
|
|
void arch_irq_work_raise(void)
|
|
|
|
|
{
|
|
|
|
|
if (__smp_cross_call)
|
|
|
|
|
smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
|
|
|
|
|
* ipi_cpu_stop - handle IPI from smp_send_stop()
|
|
|
|
|
*/
|
|
|
|
|
static void ipi_cpu_stop(unsigned int cpu)
|
|
|
|
|
{
|
|
|
|
|
set_cpu_online(cpu, false);
|
|
|
|
|
|
2017-11-02 20:12:34 +08:00
|
|
|
local_daif_mask();
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
while (1)
|
|
|
|
|
cpu_relax();
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-03 10:24:36 +08:00
|
|
|
#ifdef CONFIG_KEXEC_CORE
|
|
|
|
|
static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
#ifdef CONFIG_KEXEC_CORE
|
|
|
|
|
crash_save_cpu(regs, cpu);
|
|
|
|
|
|
|
|
|
|
atomic_dec(&waiting_for_crash_ipi);
|
|
|
|
|
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
|
if (cpu_ops[cpu]->cpu_die)
|
|
|
|
|
cpu_ops[cpu]->cpu_die(cpu);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* just in case */
|
|
|
|
|
cpu_park_loop();
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
|
|
|
|
|
* Main handler for inter-processor interrupts
|
|
|
|
|
*/
|
|
|
|
|
void handle_IPI(int ipinr, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
unsigned int cpu = smp_processor_id();
|
|
|
|
|
struct pt_regs *old_regs = set_irq_regs(regs);
|
|
|
|
|
|
2014-07-26 04:05:32 +08:00
|
|
|
if ((unsigned)ipinr < NR_IPI) {
|
2015-06-25 04:14:18 +08:00
|
|
|
trace_ipi_entry_rcuidle(ipi_types[ipinr]);
|
2014-07-26 04:05:32 +08:00
|
|
|
__inc_irq_stat(cpu, ipi_irqs[ipinr]);
|
|
|
|
|
}
|
2012-03-05 19:49:30 +08:00
|
|
|
|
|
|
|
|
switch (ipinr) {
|
|
|
|
|
case IPI_RESCHEDULE:
|
|
|
|
|
scheduler_ipi();
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case IPI_CALL_FUNC:
|
|
|
|
|
irq_enter();
|
|
|
|
|
generic_smp_call_function_interrupt();
|
|
|
|
|
irq_exit();
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case IPI_CPU_STOP:
|
|
|
|
|
irq_enter();
|
|
|
|
|
ipi_cpu_stop(cpu);
|
|
|
|
|
irq_exit();
|
|
|
|
|
break;
|
|
|
|
|
|
2017-04-03 10:24:36 +08:00
|
|
|
case IPI_CPU_CRASH_STOP:
|
|
|
|
|
if (IS_ENABLED(CONFIG_KEXEC_CORE)) {
|
|
|
|
|
irq_enter();
|
|
|
|
|
ipi_cpu_crash_stop(cpu, regs);
|
|
|
|
|
|
|
|
|
|
unreachable();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2013-09-04 17:55:17 +08:00
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
|
|
|
case IPI_TIMER:
|
|
|
|
|
irq_enter();
|
|
|
|
|
tick_receive_broadcast();
|
|
|
|
|
irq_exit();
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-05-12 23:48:51 +08:00
|
|
|
#ifdef CONFIG_IRQ_WORK
|
|
|
|
|
case IPI_IRQ_WORK:
|
|
|
|
|
irq_enter();
|
|
|
|
|
irq_work_run();
|
|
|
|
|
irq_exit();
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-01-26 19:10:38 +08:00
|
|
|
#ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
|
|
|
|
|
case IPI_WAKEUP:
|
|
|
|
|
WARN_ONCE(!acpi_parking_protocol_valid(cpu),
|
|
|
|
|
"CPU%u: Wake-up IPI outside the ACPI parking protocol\n",
|
|
|
|
|
cpu);
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
default:
|
|
|
|
|
pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2014-07-26 04:05:32 +08:00
|
|
|
|
|
|
|
|
if ((unsigned)ipinr < NR_IPI)
|
2015-06-25 04:14:18 +08:00
|
|
|
trace_ipi_exit_rcuidle(ipi_types[ipinr]);
|
2012-03-05 19:49:30 +08:00
|
|
|
set_irq_regs(old_regs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void smp_send_reschedule(int cpu)
|
|
|
|
|
{
|
|
|
|
|
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-04 17:55:17 +08:00
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
|
|
|
void tick_broadcast(const struct cpumask *mask)
|
|
|
|
|
{
|
|
|
|
|
smp_cross_call(mask, IPI_TIMER);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
void smp_send_stop(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned long timeout;
|
|
|
|
|
|
|
|
|
|
if (num_online_cpus() > 1) {
|
|
|
|
|
cpumask_t mask;
|
|
|
|
|
|
|
|
|
|
cpumask_copy(&mask, cpu_online_mask);
|
2015-03-05 08:19:18 +08:00
|
|
|
cpumask_clear_cpu(smp_processor_id(), &mask);
|
2012-03-05 19:49:30 +08:00
|
|
|
|
2017-05-17 02:42:34 +08:00
|
|
|
if (system_state <= SYSTEM_RUNNING)
|
2016-04-18 15:43:33 +08:00
|
|
|
pr_crit("SMP: stopping secondary CPUs\n");
|
2012-03-05 19:49:30 +08:00
|
|
|
smp_cross_call(&mask, IPI_CPU_STOP);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Wait up to one second for other CPUs to stop */
|
|
|
|
|
timeout = USEC_PER_SEC;
|
|
|
|
|
while (num_online_cpus() > 1 && timeout--)
|
|
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
|
|
if (num_online_cpus() > 1)
|
2016-04-18 15:43:33 +08:00
|
|
|
pr_warning("SMP: failed to stop secondary CPUs %*pbl\n",
|
|
|
|
|
cpumask_pr_args(cpu_online_mask));
|
2012-03-05 19:49:30 +08:00
|
|
|
}
|
|
|
|
|
|
2017-04-03 10:24:36 +08:00
|
|
|
#ifdef CONFIG_KEXEC_CORE
|
2017-08-17 10:24:27 +08:00
|
|
|
void crash_smp_send_stop(void)
|
2017-04-03 10:24:36 +08:00
|
|
|
{
|
2017-08-17 10:24:27 +08:00
|
|
|
static int cpus_stopped;
|
2017-04-03 10:24:36 +08:00
|
|
|
cpumask_t mask;
|
|
|
|
|
unsigned long timeout;
|
|
|
|
|
|
2017-08-17 10:24:27 +08:00
|
|
|
/*
|
|
|
|
|
* This function can be called twice in panic path, but obviously
|
|
|
|
|
* we execute this only once.
|
|
|
|
|
*/
|
|
|
|
|
if (cpus_stopped)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
cpus_stopped = 1;
|
|
|
|
|
|
2017-04-03 10:24:36 +08:00
|
|
|
if (num_online_cpus() == 1)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
cpumask_copy(&mask, cpu_online_mask);
|
|
|
|
|
cpumask_clear_cpu(smp_processor_id(), &mask);
|
|
|
|
|
|
|
|
|
|
atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
|
|
|
|
|
|
|
|
|
|
pr_crit("SMP: stopping secondary CPUs\n");
|
|
|
|
|
smp_cross_call(&mask, IPI_CPU_CRASH_STOP);
|
|
|
|
|
|
|
|
|
|
/* Wait up to one second for other CPUs to stop */
|
|
|
|
|
timeout = USEC_PER_SEC;
|
|
|
|
|
while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
|
|
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
|
|
if (atomic_read(&waiting_for_crash_ipi) > 0)
|
|
|
|
|
pr_warning("SMP: failed to stop secondary CPUs %*pbl\n",
|
|
|
|
|
cpumask_pr_args(&mask));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool smp_crash_stop_failed(void)
|
|
|
|
|
{
|
|
|
|
|
return (atomic_read(&waiting_for_crash_ipi) > 0);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-03-05 19:49:30 +08:00
|
|
|
/*
|
|
|
|
|
* not supported here
|
|
|
|
|
*/
|
|
|
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
|
|
|
{
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
2016-06-22 17:06:12 +08:00
|
|
|
|
|
|
|
|
static bool have_cpu_die(void)
|
|
|
|
|
{
|
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
|
int any_cpu = raw_smp_processor_id();
|
|
|
|
|
|
2017-03-24 21:53:56 +08:00
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if (cpu_ops[any_cpu] && cpu_ops[any_cpu]->cpu_die)
|
2016-06-22 17:06:12 +08:00
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return true;
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|
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#endif
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return false;
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|
|
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}
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bool cpus_are_stuck_in_kernel(void)
|
|
|
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|
{
|
|
|
|
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bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die());
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|
|
|
|
|
|
|
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return !!cpus_stuck_in_kernel || smp_spin_tables;
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|
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|
}
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