License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2013-10-18 01:21:36 +08:00
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#ifndef __LINUX_GPIO_DRIVER_H
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#define __LINUX_GPIO_DRIVER_H
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2023-02-09 01:07:28 +08:00
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#include <linux/bits.h>
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2014-03-25 17:40:18 +08:00
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
|
2023-02-09 01:07:28 +08:00
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#include <linux/irqhandler.h>
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gpiolib: irqchip: use different lockdep class for each gpio irqchip
Since IRQ chip helpers were introduced drivers lose ability to
register separate lockdep classes for each registered GPIO IRQ
chip and the gpiolib now is using shared lockdep class for
all GPIO IRQ chips (gpiochip_irq_lock_class).
As result, lockdep will produce warning when there are min two
stacked GPIO chips and all of them are interrupt controllers.
HW configuration which generates lockdep warning (TI dra7-evm):
[SOC GPIO bankA.gpioX]
<- irq - [pcf875x.gpioY]
<- irq - DevZ.enable_irq_wake(pcf_gpioY_irq);
The issue was reported in [1] and discussed [2].
=============================================
[ INFO: possible recursive locking detected ]
4.2.0-rc6-00013-g5d050ed-dirty #55 Not tainted
---------------------------------------------
sh/63 is trying to acquire lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
but task is already holding lock:
(class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(class);
lock(class);
*** DEADLOCK ***
May be due to missing lock nesting notation
7 locks held by sh/63:
#0: (sb_writers#4){.+.+.+}, at: [<c016bbb8>] vfs_write+0x13c/0x164
#1: (&of->mutex){+.+.+.}, at: [<c01debf4>] kernfs_fop_write+0x4c/0x1a0
#2: (s_active#36){.+.+.+}, at: [<c01debfc>] kernfs_fop_write+0x54/0x1a0
#3: (pm_mutex){+.+.+.}, at: [<c009758c>] pm_suspend+0xec/0x4c4
#4: (&dev->mutex){......}, at: [<c03f77f8>] __device_suspend+0xd4/0x398
#5: (&gpio->lock){+.+.+.}, at: [<c009b940>] __irq_get_desc_lock+0x74/0x94
#6: (class){......}, at: [<c009b91c>] __irq_get_desc_lock+0x50/0x94
stack backtrace:
CPU: 0 PID: 63 Comm: sh Not tainted 4.2.0-rc6-00013-g5d050ed-dirty #55
Hardware name: Generic DRA74X (Flattened Device Tree)
[<c0016e24>] (unwind_backtrace) from [<c0013338>] (show_stack+0x10/0x14)
[<c0013338>] (show_stack) from [<c05f6b24>] (dump_stack+0x84/0x9c)
[<c05f6b24>] (dump_stack) from [<c00903f4>] (__lock_acquire+0x19c0/0x1e20)
[<c00903f4>] (__lock_acquire) from [<c0091098>] (lock_acquire+0xa8/0x128)
[<c0091098>] (lock_acquire) from [<c05fd61c>] (_raw_spin_lock_irqsave+0x38/0x4c)
[<c05fd61c>] (_raw_spin_lock_irqsave) from [<c009b91c>] (__irq_get_desc_lock+0x50/0x94)
[<c009b91c>] (__irq_get_desc_lock) from [<c009c4f4>] (irq_set_irq_wake+0x20/0xfc)
[<c009c4f4>] (irq_set_irq_wake) from [<c0393ac4>] (pcf857x_irq_set_wake+0x24/0x54)
[<c0393ac4>] (pcf857x_irq_set_wake) from [<c009c560>] (irq_set_irq_wake+0x8c/0xfc)
[<c009c560>] (irq_set_irq_wake) from [<c04a02ac>] (gpio_keys_suspend+0x70/0xd4)
[<c04a02ac>] (gpio_keys_suspend) from [<c03f6a00>] (dpm_run_callback+0x50/0x124)
[<c03f6a00>] (dpm_run_callback) from [<c03f7830>] (__device_suspend+0x10c/0x398)
[<c03f7830>] (__device_suspend) from [<c03f90f0>] (dpm_suspend+0x134/0x2f4)
[<c03f90f0>] (dpm_suspend) from [<c0096e20>] (suspend_devices_and_enter+0xa8/0x728)
[<c0096e20>] (suspend_devices_and_enter) from [<c00977cc>] (pm_suspend+0x32c/0x4c4)
[<c00977cc>] (pm_suspend) from [<c0096060>] (state_store+0x64/0xb8)
[<c0096060>] (state_store) from [<c01dec64>] (kernfs_fop_write+0xbc/0x1a0)
[<c01dec64>] (kernfs_fop_write) from [<c016b280>] (__vfs_write+0x20/0xd8)
[<c016b280>] (__vfs_write) from [<c016bb0c>] (vfs_write+0x90/0x164)
[<c016bb0c>] (vfs_write) from [<c016c330>] (SyS_write+0x44/0x9c)
[<c016c330>] (SyS_write) from [<c000f500>] (ret_fast_syscall+0x0/0x54)
Lets fix it by using separate lockdep class for each registered GPIO
IRQ Chip. This is done by wrapping gpiochip_irqchip_add call into macros.
The implementation of this patch inspired by solution done by Nicolas
Boichat for regmap [3]
[1] http://www.spinics.net/lists/linux-gpio/msg05844.html
[2] http://www.spinics.net/lists/linux-gpio/msg06021.html
[3] http://www.spinics.net/lists/arm-kernel/msg429834.html
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roger Quadros <rogerq@ti.com>
Reported-by: Roger Quadros <rogerq@ti.com>
Tested-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-17 20:35:23 +08:00
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#include <linux/lockdep.h>
|
2017-01-23 20:34:34 +08:00
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#include <linux/pinctrl/pinconf-generic.h>
|
2022-10-07 17:53:44 +08:00
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#include <linux/pinctrl/pinctrl.h>
|
2022-04-01 18:35:52 +08:00
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#include <linux/property.h>
|
2023-02-09 01:07:28 +08:00
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#include <linux/spinlock_types.h>
|
2022-04-01 18:35:52 +08:00
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#include <linux/types.h>
|
2013-10-18 01:21:36 +08:00
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|
2023-02-09 01:07:28 +08:00
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#ifdef CONFIG_GENERIC_MSI_IRQ
|
2022-07-08 02:23:09 +08:00
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#include <asm/msi.h>
|
2023-02-09 01:07:28 +08:00
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#endif
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2022-07-08 02:23:09 +08:00
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2023-02-09 01:07:28 +08:00
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struct device;
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struct irq_chip;
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struct irq_data;
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struct module;
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2013-11-25 17:34:24 +08:00
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struct of_phandle_args;
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2023-02-09 01:07:28 +08:00
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struct pinctrl_dev;
|
2013-10-28 22:06:23 +08:00
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struct seq_file;
|
2013-10-18 01:21:36 +08:00
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2019-08-08 20:32:37 +08:00
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struct gpio_chip;
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2023-02-09 01:07:28 +08:00
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struct gpio_desc;
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struct gpio_device;
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enum gpio_lookup_flags;
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enum gpiod_flags;
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2019-08-08 20:32:37 +08:00
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2022-07-08 02:23:09 +08:00
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union gpio_irq_fwspec {
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struct irq_fwspec fwspec;
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2022-11-11 21:54:40 +08:00
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#ifdef CONFIG_GENERIC_MSI_IRQ
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2022-07-08 02:23:09 +08:00
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msi_alloc_info_t msiinfo;
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#endif
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};
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2019-11-06 16:51:47 +08:00
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#define GPIO_LINE_DIRECTION_IN 1
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#define GPIO_LINE_DIRECTION_OUT 0
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2017-11-08 02:15:45 +08:00
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/**
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* struct gpio_irq_chip - GPIO interrupt controller
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*/
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struct gpio_irq_chip {
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2017-11-08 02:15:46 +08:00
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/**
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* @chip:
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*
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* GPIO IRQ chip implementation, provided by GPIO driver.
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*/
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struct irq_chip *chip;
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2017-11-08 02:15:47 +08:00
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/**
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* @domain:
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*
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* Interrupt translation domain; responsible for mapping between GPIO
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* hwirq number and Linux IRQ number.
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*/
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struct irq_domain *domain;
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2019-08-08 20:32:37 +08:00
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#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
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/**
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* @fwnode:
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*
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* Firmware node corresponding to this gpiochip/irqchip, necessary
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* for hierarchical irqdomain support.
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*/
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struct fwnode_handle *fwnode;
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/**
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* @parent_domain:
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*
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* If non-NULL, will be set as the parent of this GPIO interrupt
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* controller's IRQ domain to establish a hierarchical interrupt
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* domain. The presence of this will activate the hierarchical
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* interrupt support.
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*/
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struct irq_domain *parent_domain;
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/**
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* @child_to_parent_hwirq:
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*
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* This callback translates a child hardware IRQ offset to a parent
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* hardware IRQ offset on a hierarchical interrupt chip. The child
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* hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
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* ngpio field of struct gpio_chip) and the corresponding parent
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* hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
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* the driver. The driver can calculate this from an offset or using
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* a lookup table or whatever method is best for this chip. Return
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* 0 on successful translation in the driver.
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*
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* If some ranges of hardware IRQs do not have a corresponding parent
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* HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
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* @need_valid_mask to make these GPIO lines unavailable for
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* translation.
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*/
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2020-03-29 22:04:05 +08:00
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int (*child_to_parent_hwirq)(struct gpio_chip *gc,
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2019-08-08 20:32:37 +08:00
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unsigned int child_hwirq,
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unsigned int child_type,
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unsigned int *parent_hwirq,
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unsigned int *parent_type);
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/**
|
2020-01-14 16:28:19 +08:00
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* @populate_parent_alloc_arg :
|
2019-08-08 20:32:37 +08:00
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*
|
2020-01-14 16:28:19 +08:00
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* This optional callback allocates and populates the specific struct
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* for the parent's IRQ domain. If this is not specified, then
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2019-08-08 20:32:37 +08:00
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* &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
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* variant named &gpiochip_populate_parent_fwspec_fourcell is also
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* available.
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*/
|
2022-07-08 02:23:09 +08:00
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int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
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union gpio_irq_fwspec *fwspec,
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unsigned int parent_hwirq,
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unsigned int parent_type);
|
2019-08-08 20:32:37 +08:00
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/**
|
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* @child_offset_to_irq:
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*
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* This optional callback is used to translate the child's GPIO line
|
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* offset on the GPIO chip to an IRQ number for the GPIO to_irq()
|
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* callback. If this is not specified, then a default callback will be
|
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* provided that returns the line offset.
|
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*/
|
2020-03-29 22:04:05 +08:00
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unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
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2019-08-08 20:32:37 +08:00
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unsigned int pin);
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/**
|
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* @child_irq_domain_ops:
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*
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* The IRQ domain operations that will be used for this GPIO IRQ
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* chip. If no operations are provided, then default callbacks will
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* be populated to setup the IRQ hierarchy. Some drivers need to
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* supply their own translate function.
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*/
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struct irq_domain_ops child_irq_domain_ops;
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#endif
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2017-11-08 02:15:48 +08:00
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/**
|
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* @handler:
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*
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* The IRQ handler to use (often a predefined IRQ core function) for
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* GPIO IRQs, provided by GPIO driver.
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*/
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irq_flow_handler_t handler;
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|
2017-11-08 02:15:49 +08:00
|
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/**
|
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* @default_type:
|
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*
|
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* Default IRQ triggering type applied during GPIO driver
|
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* initialization, provided by GPIO driver.
|
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*/
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unsigned int default_type;
|
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|
2017-11-08 02:15:53 +08:00
|
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/**
|
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* @lock_key:
|
|
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|
*
|
2018-09-04 03:55:30 +08:00
|
|
|
* Per GPIO IRQ chip lockdep class for IRQ lock.
|
2017-11-08 02:15:53 +08:00
|
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*/
|
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struct lock_class_key *lock_key;
|
2018-09-04 03:55:30 +08:00
|
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/**
|
|
|
|
* @request_key:
|
|
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|
*
|
|
|
|
* Per GPIO IRQ chip lockdep class for IRQ request.
|
|
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|
*/
|
2017-12-03 01:11:04 +08:00
|
|
|
struct lock_class_key *request_key;
|
2017-11-08 02:15:53 +08:00
|
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|
2017-11-08 02:15:45 +08:00
|
|
|
/**
|
|
|
|
* @parent_handler:
|
|
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|
*
|
|
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|
* The interrupt handler for the GPIO chip's parent interrupts, may be
|
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|
* NULL if the parent interrupts are nested rather than cascaded.
|
|
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|
*/
|
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|
|
irq_flow_handler_t parent_handler;
|
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|
|
2021-10-27 01:58:11 +08:00
|
|
|
union {
|
2022-06-06 12:44:24 +08:00
|
|
|
/**
|
|
|
|
* @parent_handler_data:
|
|
|
|
*
|
|
|
|
* If @per_parent_data is false, @parent_handler_data is a
|
|
|
|
* single pointer used as the data associated with every
|
|
|
|
* parent interrupt.
|
|
|
|
*/
|
2021-10-27 01:58:11 +08:00
|
|
|
void *parent_handler_data;
|
2022-06-06 12:44:24 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @parent_handler_data_array:
|
|
|
|
*
|
|
|
|
* If @per_parent_data is true, @parent_handler_data_array is
|
|
|
|
* an array of @num_parents pointers, and is used to associate
|
|
|
|
* different data for each parent. This cannot be NULL if
|
|
|
|
* @per_parent_data is true.
|
|
|
|
*/
|
2021-10-27 01:58:11 +08:00
|
|
|
void **parent_handler_data_array;
|
|
|
|
};
|
2017-11-08 02:15:50 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @num_parents:
|
|
|
|
*
|
|
|
|
* The number of interrupt parents of a GPIO chip.
|
|
|
|
*/
|
|
|
|
unsigned int num_parents;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @parents:
|
|
|
|
*
|
|
|
|
* A list of interrupt parents of a GPIO chip. This is owned by the
|
|
|
|
* driver, so the core will only reference this list, not modify it.
|
|
|
|
*/
|
|
|
|
unsigned int *parents;
|
2017-11-08 02:15:51 +08:00
|
|
|
|
2017-11-08 02:15:54 +08:00
|
|
|
/**
|
|
|
|
* @map:
|
|
|
|
*
|
|
|
|
* A list of interrupt parents for each line of a GPIO chip.
|
|
|
|
*/
|
|
|
|
unsigned int *map;
|
|
|
|
|
2017-11-08 02:15:51 +08:00
|
|
|
/**
|
2017-11-08 02:15:57 +08:00
|
|
|
* @threaded:
|
2017-11-08 02:15:51 +08:00
|
|
|
*
|
2017-11-08 02:15:57 +08:00
|
|
|
* True if set the interrupt handling uses nested threads.
|
2017-11-08 02:15:51 +08:00
|
|
|
*/
|
2017-11-08 02:15:57 +08:00
|
|
|
bool threaded;
|
2017-11-08 02:15:52 +08:00
|
|
|
|
2021-10-27 01:58:11 +08:00
|
|
|
/**
|
|
|
|
* @per_parent_data:
|
|
|
|
*
|
|
|
|
* True if parent_handler_data_array describes a @num_parents
|
|
|
|
* sized array to be used as parent data.
|
|
|
|
*/
|
|
|
|
bool per_parent_data;
|
|
|
|
|
2022-03-21 21:32:41 +08:00
|
|
|
/**
|
|
|
|
* @initialized:
|
|
|
|
*
|
|
|
|
* Flag to track GPIO chip irq member's initialization.
|
|
|
|
* This flag will make sure GPIO chip irq members are not used
|
|
|
|
* before they are initialized.
|
|
|
|
*/
|
|
|
|
bool initialized;
|
|
|
|
|
2023-06-19 16:56:07 +08:00
|
|
|
/**
|
|
|
|
* @domain_is_allocated_externally:
|
|
|
|
*
|
|
|
|
* True it the irq_domain was allocated outside of gpiolib, in which
|
|
|
|
* case gpiolib won't free the irq_domain itself.
|
|
|
|
*/
|
|
|
|
bool domain_is_allocated_externally;
|
|
|
|
|
2019-10-09 22:34:44 +08:00
|
|
|
/**
|
|
|
|
* @init_hw: optional routine to initialize hardware before
|
|
|
|
* an IRQ chip will be added. This is quite useful when
|
|
|
|
* a particular driver wants to clear IRQ related registers
|
|
|
|
* in order to avoid undesired events.
|
|
|
|
*/
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*init_hw)(struct gpio_chip *gc);
|
2019-10-09 22:34:44 +08:00
|
|
|
|
2017-11-08 02:15:52 +08:00
|
|
|
/**
|
2019-09-04 22:01:04 +08:00
|
|
|
* @init_valid_mask: optional routine to initialize @valid_mask, to be
|
|
|
|
* used if not all GPIO lines are valid interrupts. Sometimes some
|
|
|
|
* lines just cannot fire interrupts, and this routine, when defined,
|
|
|
|
* is passed a bitmap in "valid_mask" and it will have ngpios
|
|
|
|
* bits from 0..(ngpios-1) set to "1" as in valid. The callback can
|
|
|
|
* then directly set some bits to "0" if they cannot be used for
|
|
|
|
* interrupts.
|
|
|
|
*/
|
2020-03-29 22:04:05 +08:00
|
|
|
void (*init_valid_mask)(struct gpio_chip *gc,
|
2019-09-04 22:01:04 +08:00
|
|
|
unsigned long *valid_mask,
|
|
|
|
unsigned int ngpios);
|
2017-11-08 02:15:52 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @valid_mask:
|
|
|
|
*
|
2021-03-24 06:19:05 +08:00
|
|
|
* If not %NULL, holds bitmask of GPIOs which are valid to be included
|
2017-11-08 02:15:52 +08:00
|
|
|
* in IRQ domain of the chip.
|
|
|
|
*/
|
|
|
|
unsigned long *valid_mask;
|
2017-11-08 02:15:58 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @first:
|
|
|
|
*
|
|
|
|
* Required for static IRQ allocation. If set, irq_domain_add_simple()
|
|
|
|
* will allocate and map all IRQs during initialization.
|
|
|
|
*/
|
|
|
|
unsigned int first;
|
2018-09-08 17:23:17 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @irq_enable:
|
|
|
|
*
|
|
|
|
* Store old irq_chip irq_enable callback
|
|
|
|
*/
|
|
|
|
void (*irq_enable)(struct irq_data *data);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @irq_disable:
|
|
|
|
*
|
|
|
|
* Store old irq_chip irq_disable callback
|
|
|
|
*/
|
|
|
|
void (*irq_disable)(struct irq_data *data);
|
2020-05-24 01:11:10 +08:00
|
|
|
/**
|
|
|
|
* @irq_unmask:
|
|
|
|
*
|
|
|
|
* Store old irq_chip irq_unmask callback
|
|
|
|
*/
|
|
|
|
void (*irq_unmask)(struct irq_data *data);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @irq_mask:
|
|
|
|
*
|
|
|
|
* Store old irq_chip irq_mask callback
|
|
|
|
*/
|
|
|
|
void (*irq_mask)(struct irq_data *data);
|
2017-11-08 02:15:45 +08:00
|
|
|
};
|
|
|
|
|
2013-10-18 01:21:36 +08:00
|
|
|
/**
|
|
|
|
* struct gpio_chip - abstract a GPIO controller
|
2016-02-12 21:48:23 +08:00
|
|
|
* @label: a functional name for the GPIO device, such as a part
|
|
|
|
* number or the name of the SoC IP-block implementing it.
|
2015-10-20 17:10:38 +08:00
|
|
|
* @gpiodev: the internal state holder, opaque struct
|
2015-11-04 16:56:26 +08:00
|
|
|
* @parent: optional parent device providing the GPIOs
|
2021-12-13 18:16:41 +08:00
|
|
|
* @fwnode: optional fwnode providing this controller's properties
|
2013-10-18 01:21:36 +08:00
|
|
|
* @owner: helps prevent removal of modules exporting active GPIOs
|
|
|
|
* @request: optional hook for chip-specific activation, such as
|
|
|
|
* enabling module power and clock; may sleep
|
|
|
|
* @free: optional hook for chip-specific deactivation, such as
|
|
|
|
* disabling module power and clock; may sleep
|
|
|
|
* @get_direction: returns direction for signal "offset", 0=out, 1=in,
|
2020-04-29 08:23:27 +08:00
|
|
|
* (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
|
|
|
|
* or negative error. It is recommended to always implement this
|
|
|
|
* function, even on input-only or output-only gpio chips.
|
2013-10-18 01:21:36 +08:00
|
|
|
* @direction_input: configures signal "offset" as input, or returns error
|
2018-09-25 15:54:14 +08:00
|
|
|
* This can be omitted on input-only or output-only gpio chips.
|
2013-10-18 01:21:36 +08:00
|
|
|
* @direction_output: configures signal "offset" as output, or returns error
|
2018-09-25 15:54:14 +08:00
|
|
|
* This can be omitted on input-only or output-only gpio chips.
|
2015-12-22 22:37:28 +08:00
|
|
|
* @get: returns value for signal "offset", 0=low, 1=high, or negative error
|
2017-10-12 18:40:10 +08:00
|
|
|
* @get_multiple: reads values for multiple signals defined by "mask" and
|
|
|
|
* stores them in "bits", returns 0 on success or negative error
|
2013-10-18 01:21:36 +08:00
|
|
|
* @set: assigns output value for signal "offset"
|
2014-11-05 00:12:06 +08:00
|
|
|
* @set_multiple: assigns output values for multiple signals defined by "mask"
|
2017-01-23 20:34:34 +08:00
|
|
|
* @set_config: optional hook for all kinds of settings. Uses the same
|
|
|
|
* packed config format as generic pinconf.
|
2023-01-12 22:17:43 +08:00
|
|
|
* @to_irq: optional hook supporting non-static gpiod_to_irq() mappings;
|
2013-10-18 01:21:36 +08:00
|
|
|
* implementation may not sleep
|
|
|
|
* @dbg_show: optional routine to show contents in debugfs; default code
|
|
|
|
* will be used when this is omitted, but custom code can show extra
|
|
|
|
* state (such as pullup/pulldown configuration).
|
2019-07-01 22:26:50 +08:00
|
|
|
* @init_valid_mask: optional routine to initialize @valid_mask, to be used if
|
|
|
|
* not all GPIOs are valid.
|
2019-11-05 00:09:39 +08:00
|
|
|
* @add_pin_ranges: optional routine to initialize pin ranges, to be used when
|
|
|
|
* requires special mapping of the pins that provides GPIO functionality.
|
|
|
|
* It is called after adding GPIO chip and before adding IRQ chip.
|
2022-04-23 04:52:16 +08:00
|
|
|
* @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
|
|
|
|
* enable hardware timestamp.
|
|
|
|
* @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
|
|
|
|
* disable hardware timestamp.
|
2015-05-13 19:03:21 +08:00
|
|
|
* @base: identifies the first GPIO number handled by this chip;
|
|
|
|
* or, if negative during registration, requests dynamic ID allocation.
|
|
|
|
* DEPRECATION: providing anything non-negative and nailing the base
|
2015-06-15 19:31:33 +08:00
|
|
|
* offset of GPIO chips is deprecated. Please pass -1 as base to
|
2015-05-13 19:03:21 +08:00
|
|
|
* let gpiolib select the chip base in all possible cases. We want to
|
|
|
|
* get rid of the static GPIO number space in the long run.
|
2013-10-18 01:21:36 +08:00
|
|
|
* @ngpio: the number of GPIOs handled by this controller; the last GPIO
|
|
|
|
* handled is (base + ngpio - 1).
|
2021-07-28 12:12:51 +08:00
|
|
|
* @offset: when multiple gpio chips belong to the same device this
|
|
|
|
* can be used as offset within the device so friendly names can
|
|
|
|
* be properly assigned.
|
2013-10-18 01:21:36 +08:00
|
|
|
* @names: if set, must be an array of strings to use as alternative
|
|
|
|
* names for the GPIOs in this chip. Any entry in the array
|
|
|
|
* may be NULL if there is no alias for the GPIO, however the
|
|
|
|
* array must be @ngpio entries long. A name can include a single printk
|
|
|
|
* format specifier for an unsigned int. It is substituted by the actual
|
|
|
|
* number of the gpio.
|
2013-12-04 21:42:46 +08:00
|
|
|
* @can_sleep: flag must be set iff get()/set() methods sleep, as they
|
2014-04-09 19:34:39 +08:00
|
|
|
* must while accessing GPIO expander chips over I2C or SPI. This
|
|
|
|
* implies that if the chip supports IRQs, these IRQs need to be threaded
|
|
|
|
* as the chip access may sleep when e.g. reading out the IRQ status
|
|
|
|
* registers.
|
2015-12-04 21:02:58 +08:00
|
|
|
* @read_reg: reader function for generic GPIO
|
|
|
|
* @write_reg: writer function for generic GPIO
|
2017-10-20 22:31:27 +08:00
|
|
|
* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
|
|
|
|
* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
|
|
|
|
* generic GPIO core. It is for internal housekeeping only.
|
2015-12-04 21:02:58 +08:00
|
|
|
* @reg_dat: data (in) register for generic GPIO
|
|
|
|
* @reg_set: output set register (out=high) for generic GPIO
|
2016-10-05 04:15:42 +08:00
|
|
|
* @reg_clr: output clear register (out=low) for generic GPIO
|
2019-02-22 18:14:44 +08:00
|
|
|
* @reg_dir_out: direction out setting register for generic GPIO
|
|
|
|
* @reg_dir_in: direction in setting register for generic GPIO
|
|
|
|
* @bgpio_dir_unreadable: indicates that the direction register(s) cannot
|
|
|
|
* be read and we need to rely on out internal state tracking.
|
2015-12-04 21:02:58 +08:00
|
|
|
* @bgpio_bits: number of register bits used for a generic GPIO i.e.
|
|
|
|
* <register width> * 8
|
|
|
|
* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
|
|
|
|
* shadowed and real data registers writes together.
|
|
|
|
* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
|
|
|
|
* safely.
|
|
|
|
* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
|
2019-02-22 18:14:44 +08:00
|
|
|
* direction safely. A "1" in this word means the line is set as
|
|
|
|
* output.
|
2013-10-18 01:21:36 +08:00
|
|
|
*
|
|
|
|
* A gpio_chip can help platforms abstract various sources of GPIOs so
|
2021-03-24 06:19:05 +08:00
|
|
|
* they can all be accessed through a common programming interface.
|
2013-10-18 01:21:36 +08:00
|
|
|
* Example sources would be SOC controllers, FPGAs, multifunction
|
|
|
|
* chips, dedicated GPIO expanders, and so on.
|
|
|
|
*
|
|
|
|
* Each chip controls a number of signals, identified in method calls
|
|
|
|
* by "offset" values in the range 0..(@ngpio - 1). When those signals
|
|
|
|
* are referenced through calls like gpio_get_value(gpio), the offset
|
|
|
|
* is calculated by subtracting @base from the gpio number.
|
|
|
|
*/
|
|
|
|
struct gpio_chip {
|
|
|
|
const char *label;
|
2015-10-20 17:10:38 +08:00
|
|
|
struct gpio_device *gpiodev;
|
2015-11-04 16:56:26 +08:00
|
|
|
struct device *parent;
|
2021-12-13 18:16:41 +08:00
|
|
|
struct fwnode_handle *fwnode;
|
2013-10-18 01:21:36 +08:00
|
|
|
struct module *owner;
|
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*request)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset);
|
2020-03-29 22:04:05 +08:00
|
|
|
void (*free)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset);
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*get_direction)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset);
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*direction_input)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset);
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*direction_output)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset, int value);
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*get)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset);
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*get_multiple)(struct gpio_chip *gc,
|
2017-10-12 18:40:10 +08:00
|
|
|
unsigned long *mask,
|
|
|
|
unsigned long *bits);
|
2020-03-29 22:04:05 +08:00
|
|
|
void (*set)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset, int value);
|
2020-03-29 22:04:05 +08:00
|
|
|
void (*set_multiple)(struct gpio_chip *gc,
|
2014-11-05 00:12:06 +08:00
|
|
|
unsigned long *mask,
|
|
|
|
unsigned long *bits);
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*set_config)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset,
|
2017-01-23 20:34:34 +08:00
|
|
|
unsigned long config);
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*to_irq)(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset);
|
2013-10-18 01:21:36 +08:00
|
|
|
|
|
|
|
void (*dbg_show)(struct seq_file *s,
|
2020-03-29 22:04:05 +08:00
|
|
|
struct gpio_chip *gc);
|
2018-10-05 14:52:58 +08:00
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*init_valid_mask)(struct gpio_chip *gc,
|
2019-08-19 16:49:04 +08:00
|
|
|
unsigned long *valid_mask,
|
|
|
|
unsigned int ngpios);
|
2018-10-05 14:52:58 +08:00
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*add_pin_ranges)(struct gpio_chip *gc);
|
2019-11-05 00:09:39 +08:00
|
|
|
|
2022-04-23 04:52:16 +08:00
|
|
|
int (*en_hw_timestamp)(struct gpio_chip *gc,
|
|
|
|
u32 offset,
|
|
|
|
unsigned long flags);
|
|
|
|
int (*dis_hw_timestamp)(struct gpio_chip *gc,
|
|
|
|
u32 offset,
|
|
|
|
unsigned long flags);
|
2013-10-18 01:21:36 +08:00
|
|
|
int base;
|
|
|
|
u16 ngpio;
|
2021-07-28 12:12:51 +08:00
|
|
|
u16 offset;
|
2013-10-18 01:21:36 +08:00
|
|
|
const char *const *names;
|
2013-12-04 21:42:46 +08:00
|
|
|
bool can_sleep;
|
2013-10-18 01:21:36 +08:00
|
|
|
|
2015-12-04 21:02:58 +08:00
|
|
|
#if IS_ENABLED(CONFIG_GPIO_GENERIC)
|
|
|
|
unsigned long (*read_reg)(void __iomem *reg);
|
|
|
|
void (*write_reg)(void __iomem *reg, unsigned long data);
|
2017-10-20 22:31:27 +08:00
|
|
|
bool be_bits;
|
2015-12-04 21:02:58 +08:00
|
|
|
void __iomem *reg_dat;
|
|
|
|
void __iomem *reg_set;
|
|
|
|
void __iomem *reg_clr;
|
2019-02-22 18:14:44 +08:00
|
|
|
void __iomem *reg_dir_out;
|
|
|
|
void __iomem *reg_dir_in;
|
|
|
|
bool bgpio_dir_unreadable;
|
2015-12-04 21:02:58 +08:00
|
|
|
int bgpio_bits;
|
2022-04-19 09:28:10 +08:00
|
|
|
raw_spinlock_t bgpio_lock;
|
2015-12-04 21:02:58 +08:00
|
|
|
unsigned long bgpio_data;
|
|
|
|
unsigned long bgpio_dir;
|
2019-06-18 00:45:05 +08:00
|
|
|
#endif /* CONFIG_GPIO_GENERIC */
|
2015-12-04 21:02:58 +08:00
|
|
|
|
2014-03-25 17:40:18 +08:00
|
|
|
#ifdef CONFIG_GPIOLIB_IRQCHIP
|
|
|
|
/*
|
2014-09-05 19:09:25 +08:00
|
|
|
* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
|
2014-03-25 17:40:18 +08:00
|
|
|
* to handle IRQs for most practical cases.
|
|
|
|
*/
|
2017-11-08 02:15:45 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @irq:
|
|
|
|
*
|
|
|
|
* Integrates interrupt chip functionality with the GPIO chip. Can be
|
|
|
|
* used to handle IRQs for most practical cases.
|
|
|
|
*/
|
|
|
|
struct gpio_irq_chip irq;
|
2019-06-18 00:45:05 +08:00
|
|
|
#endif /* CONFIG_GPIOLIB_IRQCHIP */
|
2014-03-25 17:40:18 +08:00
|
|
|
|
2018-03-24 00:34:52 +08:00
|
|
|
/**
|
|
|
|
* @valid_mask:
|
|
|
|
*
|
2021-03-24 06:19:05 +08:00
|
|
|
* If not %NULL, holds bitmask of GPIOs which are valid to be used
|
2018-03-24 00:34:52 +08:00
|
|
|
* from the chip.
|
|
|
|
*/
|
|
|
|
unsigned long *valid_mask;
|
|
|
|
|
2013-10-18 01:21:36 +08:00
|
|
|
#if defined(CONFIG_OF_GPIO)
|
|
|
|
/*
|
2021-03-24 06:19:05 +08:00
|
|
|
* If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
|
|
|
|
* the device tree automatically may have an OF translation
|
2013-10-18 01:21:36 +08:00
|
|
|
*/
|
2017-07-24 22:57:23 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @of_gpio_n_cells:
|
|
|
|
*
|
|
|
|
* Number of cells used to form the GPIO specifier.
|
|
|
|
*/
|
2017-07-24 22:57:28 +08:00
|
|
|
unsigned int of_gpio_n_cells;
|
2017-07-24 22:57:23 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* @of_xlate:
|
|
|
|
*
|
|
|
|
* Callback to translate a device tree GPIO specifier into a chip-
|
|
|
|
* relative GPIO number and flags.
|
|
|
|
*/
|
2013-10-18 01:21:36 +08:00
|
|
|
int (*of_xlate)(struct gpio_chip *gc,
|
|
|
|
const struct of_phandle_args *gpiospec, u32 *flags);
|
2019-06-18 00:45:05 +08:00
|
|
|
#endif /* CONFIG_OF_GPIO */
|
2013-10-18 01:21:36 +08:00
|
|
|
};
|
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
extern const char *gpiochip_is_requested(struct gpio_chip *gc,
|
2020-04-29 08:23:28 +08:00
|
|
|
unsigned int offset);
|
2013-10-18 01:21:36 +08:00
|
|
|
|
2020-06-15 23:05:41 +08:00
|
|
|
/**
|
|
|
|
* for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
|
|
|
|
* @chip: the chip to query
|
|
|
|
* @i: loop variable
|
|
|
|
* @base: first GPIO in the range
|
|
|
|
* @size: amount of GPIOs to check starting from @base
|
|
|
|
* @label: label of current GPIO
|
|
|
|
*/
|
|
|
|
#define for_each_requested_gpio_in_range(chip, i, base, size, label) \
|
|
|
|
for (i = 0; i < size; i++) \
|
|
|
|
if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
|
|
|
|
|
|
|
|
/* Iterates over all requested GPIO of the given @chip */
|
|
|
|
#define for_each_requested_gpio(chip, i, label) \
|
|
|
|
for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
|
|
|
|
|
2013-10-18 01:21:36 +08:00
|
|
|
/* add/remove chips */
|
2020-03-29 22:04:05 +08:00
|
|
|
extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
2017-12-03 01:11:04 +08:00
|
|
|
struct lock_class_key *lock_key,
|
|
|
|
struct lock_class_key *request_key);
|
2017-11-08 02:15:59 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* gpiochip_add_data() - register a gpio_chip
|
2020-07-23 17:58:28 +08:00
|
|
|
* @gc: the chip to register, with gc->base initialized
|
2017-11-08 02:15:59 +08:00
|
|
|
* @data: driver-private data associated with this chip
|
|
|
|
*
|
|
|
|
* Context: potentially before irqs will work
|
|
|
|
*
|
|
|
|
* When gpiochip_add_data() is called very early during boot, so that GPIOs
|
2020-07-23 17:58:28 +08:00
|
|
|
* can be freely used, the gc->parent device must be registered before
|
2017-11-08 02:15:59 +08:00
|
|
|
* the gpio framework's arch_initcall(). Otherwise sysfs initialization
|
|
|
|
* for GPIOs will fail rudely.
|
|
|
|
*
|
|
|
|
* gpiochip_add_data() must only be called after gpiolib initialization,
|
2021-03-24 06:19:05 +08:00
|
|
|
* i.e. after core_initcall().
|
2017-11-08 02:15:59 +08:00
|
|
|
*
|
2020-07-23 17:58:28 +08:00
|
|
|
* If gc->base is negative, this requests dynamic assignment of
|
2017-11-08 02:15:59 +08:00
|
|
|
* a range of valid GPIOs.
|
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* A negative errno if the chip can't be registered, such as because the
|
2020-07-23 17:58:28 +08:00
|
|
|
* gc->base is invalid or already associated with a different chip.
|
2017-11-08 02:15:59 +08:00
|
|
|
* Otherwise it returns zero as a success code.
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_LOCKDEP
|
2020-03-29 22:04:05 +08:00
|
|
|
#define gpiochip_add_data(gc, data) ({ \
|
2017-12-03 01:11:04 +08:00
|
|
|
static struct lock_class_key lock_key; \
|
|
|
|
static struct lock_class_key request_key; \
|
2020-03-29 22:04:05 +08:00
|
|
|
gpiochip_add_data_with_key(gc, data, &lock_key, \
|
2017-12-03 01:11:04 +08:00
|
|
|
&request_key); \
|
2017-11-08 02:15:59 +08:00
|
|
|
})
|
2020-07-31 20:38:36 +08:00
|
|
|
#define devm_gpiochip_add_data(dev, gc, data) ({ \
|
|
|
|
static struct lock_class_key lock_key; \
|
|
|
|
static struct lock_class_key request_key; \
|
|
|
|
devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
|
|
|
|
&request_key); \
|
|
|
|
})
|
2017-11-08 02:15:59 +08:00
|
|
|
#else
|
2020-03-29 22:04:05 +08:00
|
|
|
#define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
|
2020-07-31 20:38:36 +08:00
|
|
|
#define devm_gpiochip_add_data(dev, gc, data) \
|
|
|
|
devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
|
2019-06-18 00:45:05 +08:00
|
|
|
#endif /* CONFIG_LOCKDEP */
|
2017-11-08 02:15:59 +08:00
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
static inline int gpiochip_add(struct gpio_chip *gc)
|
2015-12-03 22:14:13 +08:00
|
|
|
{
|
2020-03-29 22:04:05 +08:00
|
|
|
return gpiochip_add_data(gc, NULL);
|
2015-12-03 22:14:13 +08:00
|
|
|
}
|
2020-03-29 22:04:05 +08:00
|
|
|
extern void gpiochip_remove(struct gpio_chip *gc);
|
2020-07-31 20:38:36 +08:00
|
|
|
extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
|
|
|
|
struct lock_class_key *lock_key,
|
|
|
|
struct lock_class_key *request_key);
|
2016-02-15 19:02:09 +08:00
|
|
|
|
2013-10-18 01:21:36 +08:00
|
|
|
extern struct gpio_chip *gpiochip_find(void *data,
|
2020-03-29 22:04:05 +08:00
|
|
|
int (*match)(struct gpio_chip *gc, void *data));
|
2013-10-18 01:21:36 +08:00
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
|
2013-10-18 01:21:36 +08:00
|
|
|
|
2022-04-19 22:18:38 +08:00
|
|
|
/* irq_data versions of the above */
|
|
|
|
int gpiochip_irq_reqres(struct irq_data *data);
|
|
|
|
void gpiochip_irq_relres(struct irq_data *data);
|
|
|
|
|
2022-04-19 22:18:39 +08:00
|
|
|
/* Paste this in your irq_chip structure */
|
|
|
|
#define GPIOCHIP_IRQ_RESOURCE_HELPERS \
|
|
|
|
.irq_request_resources = gpiochip_irq_reqres, \
|
|
|
|
.irq_release_resources = gpiochip_irq_relres
|
|
|
|
|
|
|
|
static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
|
|
|
|
const struct irq_chip *chip)
|
|
|
|
{
|
|
|
|
/* Yes, dropping const is ugly, but it isn't like we have a choice */
|
|
|
|
girq->chip = (struct irq_chip *)chip;
|
|
|
|
}
|
|
|
|
|
2016-02-16 22:41:42 +08:00
|
|
|
/* Line status inquiry for drivers */
|
2020-03-29 22:04:05 +08:00
|
|
|
bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
|
2016-02-16 22:41:42 +08:00
|
|
|
|
2017-05-23 22:47:29 +08:00
|
|
|
/* Sleep persistence inquiry for drivers */
|
2020-03-29 22:04:05 +08:00
|
|
|
bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
|
2017-05-23 22:47:29 +08:00
|
|
|
|
2015-12-03 22:14:13 +08:00
|
|
|
/* get driver data */
|
2020-03-29 22:04:05 +08:00
|
|
|
void *gpiochip_get_data(struct gpio_chip *gc);
|
2015-12-03 22:14:13 +08:00
|
|
|
|
2015-12-04 21:02:58 +08:00
|
|
|
struct bgpio_pdata {
|
|
|
|
const char *label;
|
|
|
|
int base;
|
|
|
|
int ngpio;
|
|
|
|
};
|
|
|
|
|
2019-08-08 20:32:37 +08:00
|
|
|
#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
2022-07-08 02:23:09 +08:00
|
|
|
int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
|
|
|
|
union gpio_irq_fwspec *gfwspec,
|
|
|
|
unsigned int parent_hwirq,
|
|
|
|
unsigned int parent_type);
|
|
|
|
int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
|
|
|
|
union gpio_irq_fwspec *gfwspec,
|
2019-08-08 20:32:37 +08:00
|
|
|
unsigned int parent_hwirq,
|
|
|
|
unsigned int parent_type);
|
|
|
|
|
|
|
|
#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
|
|
|
|
|
2015-12-04 21:02:58 +08:00
|
|
|
int bgpio_init(struct gpio_chip *gc, struct device *dev,
|
|
|
|
unsigned long sz, void __iomem *dat, void __iomem *set,
|
|
|
|
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
|
|
|
|
unsigned long flags);
|
|
|
|
|
|
|
|
#define BGPIOF_BIG_ENDIAN BIT(0)
|
|
|
|
#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
|
|
|
|
#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
|
|
|
|
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
|
|
|
|
#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
|
|
|
|
#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
|
2020-03-15 20:13:37 +08:00
|
|
|
#define BGPIOF_NO_SET_ON_INPUT BIT(6)
|
2015-12-04 21:02:58 +08:00
|
|
|
|
2017-11-08 02:15:55 +08:00
|
|
|
int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
|
|
|
|
irq_hw_number_t hwirq);
|
|
|
|
void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
|
|
|
|
|
2019-01-20 04:42:42 +08:00
|
|
|
int gpiochip_irq_domain_activate(struct irq_domain *domain,
|
|
|
|
struct irq_data *data, bool reserve);
|
|
|
|
void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
|
|
|
|
struct irq_data *data);
|
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
|
2018-01-10 09:58:46 +08:00
|
|
|
unsigned int offset);
|
|
|
|
|
2021-03-24 16:19:02 +08:00
|
|
|
#ifdef CONFIG_GPIOLIB_IRQCHIP
|
2020-05-28 22:58:43 +08:00
|
|
|
int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
|
|
|
|
struct irq_domain *domain);
|
2021-03-24 16:19:02 +08:00
|
|
|
#else
|
2023-02-09 01:07:28 +08:00
|
|
|
|
|
|
|
#include <asm/bug.h>
|
|
|
|
#include <asm/errno.h>
|
|
|
|
|
2021-03-24 16:19:02 +08:00
|
|
|
static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
|
|
|
|
struct irq_domain *domain)
|
|
|
|
{
|
|
|
|
WARN_ON(1);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
#endif
|
2020-05-28 22:58:43 +08:00
|
|
|
|
2020-04-29 08:23:28 +08:00
|
|
|
int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
|
2017-01-23 20:34:34 +08:00
|
|
|
unsigned long config);
|
2015-10-11 23:34:15 +08:00
|
|
|
|
2015-03-18 08:56:17 +08:00
|
|
|
/**
|
|
|
|
* struct gpio_pin_range - pin range controlled by a gpio chip
|
2017-07-24 22:57:22 +08:00
|
|
|
* @node: list for maintaining set of pin ranges, used internally
|
2015-03-18 08:56:17 +08:00
|
|
|
* @pctldev: pinctrl device which handles corresponding pins
|
|
|
|
* @range: actual range of pins controlled by a gpio controller
|
|
|
|
*/
|
|
|
|
struct gpio_pin_range {
|
|
|
|
struct list_head node;
|
|
|
|
struct pinctrl_dev *pctldev;
|
|
|
|
struct pinctrl_gpio_range range;
|
|
|
|
};
|
|
|
|
|
2019-07-30 13:43:47 +08:00
|
|
|
#ifdef CONFIG_PINCTRL
|
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
|
2015-03-18 08:56:17 +08:00
|
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
|
|
unsigned int npins);
|
2020-03-29 22:04:05 +08:00
|
|
|
int gpiochip_add_pingroup_range(struct gpio_chip *gc,
|
2015-03-18 08:56:17 +08:00
|
|
|
struct pinctrl_dev *pctldev,
|
|
|
|
unsigned int gpio_offset, const char *pin_group);
|
2020-03-29 22:04:05 +08:00
|
|
|
void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
|
2015-03-18 08:56:17 +08:00
|
|
|
|
2019-06-18 00:45:05 +08:00
|
|
|
#else /* ! CONFIG_PINCTRL */
|
2015-03-18 08:56:17 +08:00
|
|
|
|
|
|
|
static inline int
|
2020-03-29 22:04:05 +08:00
|
|
|
gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
|
2015-03-18 08:56:17 +08:00
|
|
|
unsigned int gpio_offset, unsigned int pin_offset,
|
|
|
|
unsigned int npins)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static inline int
|
2020-03-29 22:04:05 +08:00
|
|
|
gpiochip_add_pingroup_range(struct gpio_chip *gc,
|
2015-03-18 08:56:17 +08:00
|
|
|
struct pinctrl_dev *pctldev,
|
|
|
|
unsigned int gpio_offset, const char *pin_group)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
2020-03-29 22:04:05 +08:00
|
|
|
gpiochip_remove_pin_ranges(struct gpio_chip *gc)
|
2015-03-18 08:56:17 +08:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_PINCTRL */
|
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
|
2019-12-24 20:06:59 +08:00
|
|
|
unsigned int hwnum,
|
2018-09-04 19:31:45 +08:00
|
|
|
const char *label,
|
2019-04-26 20:40:18 +08:00
|
|
|
enum gpio_lookup_flags lflags,
|
|
|
|
enum gpiod_flags dflags);
|
2014-07-22 23:01:01 +08:00
|
|
|
void gpiochip_free_own_desc(struct gpio_desc *desc);
|
|
|
|
|
2019-09-05 17:20:25 +08:00
|
|
|
#ifdef CONFIG_GPIOLIB
|
|
|
|
|
2019-08-22 11:18:17 +08:00
|
|
|
/* lock/unlock as IRQ */
|
2020-03-29 22:04:05 +08:00
|
|
|
int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
|
|
|
|
void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
|
2019-08-22 11:18:17 +08:00
|
|
|
|
2019-07-30 13:43:47 +08:00
|
|
|
|
|
|
|
struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
|
|
|
|
|
2014-02-09 16:43:54 +08:00
|
|
|
#else /* CONFIG_GPIOLIB */
|
|
|
|
|
2023-02-09 01:07:28 +08:00
|
|
|
#include <linux/err.h>
|
|
|
|
|
|
|
|
#include <asm/bug.h>
|
|
|
|
|
2014-02-09 16:43:54 +08:00
|
|
|
static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
|
|
|
|
{
|
|
|
|
/* GPIO can never have been requested */
|
|
|
|
WARN_ON(1);
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
}
|
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
|
2019-08-22 11:18:17 +08:00
|
|
|
unsigned int offset)
|
|
|
|
{
|
|
|
|
WARN_ON(1);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-03-29 22:04:05 +08:00
|
|
|
static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
|
2019-08-22 11:18:17 +08:00
|
|
|
unsigned int offset)
|
|
|
|
{
|
|
|
|
WARN_ON(1);
|
|
|
|
}
|
2014-02-09 16:43:54 +08:00
|
|
|
#endif /* CONFIG_GPIOLIB */
|
|
|
|
|
2022-04-01 18:35:52 +08:00
|
|
|
#define for_each_gpiochip_node(dev, child) \
|
|
|
|
device_for_each_child_node(dev, child) \
|
|
|
|
if (!fwnode_property_present(child, "gpio-controller")) {} else
|
|
|
|
|
2022-04-01 18:35:53 +08:00
|
|
|
static inline unsigned int gpiochip_node_count(struct device *dev)
|
|
|
|
{
|
|
|
|
struct fwnode_handle *child;
|
|
|
|
unsigned int count = 0;
|
|
|
|
|
|
|
|
for_each_gpiochip_node(dev, child)
|
|
|
|
count++;
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2022-04-15 02:42:48 +08:00
|
|
|
static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
|
|
|
|
{
|
|
|
|
struct fwnode_handle *fwnode;
|
|
|
|
|
|
|
|
for_each_gpiochip_node(dev, fwnode)
|
|
|
|
return fwnode;
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2019-07-30 13:43:47 +08:00
|
|
|
#endif /* __LINUX_GPIO_DRIVER_H */
|