2014-12-09 00:09:10 +08:00
/*
* Copyright © 2014 Intel Corporation
*
* Permission is hereby granted , free of charge , to any person obtaining a
* copy of this software and associated documentation files ( the " Software " ) ,
* to deal in the Software without restriction , including without limitation
* the rights to use , copy , modify , merge , publish , distribute , sublicense ,
* and / or sell copies of the Software , and to permit persons to whom the
* Software is furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice ( including the next
* paragraph ) shall be included in all copies or substantial portions of the
* Software .
*
* THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER
* LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING
* FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE .
*/
2014-12-08 22:46:31 +08:00
/**
* DOC : Frame Buffer Compression ( FBC )
*
* FBC tries to save memory bandwidth ( and so power consumption ) by
* compressing the amount of memory used by the display . It is total
* transparent to user space and completely handled in the kernel .
2014-12-09 00:09:10 +08:00
*
* The benefits of FBC are mostly visible with solid backgrounds and
2014-12-08 22:46:31 +08:00
* variation - less patterns . It comes from keeping the memory footprint small
* and having fewer memory pages opened and accessed for refreshing the display .
2014-12-09 00:09:10 +08:00
*
2014-12-08 22:46:31 +08:00
* i915 is responsible to reserve stolen memory for FBC and configure its
* offset on proper registers . The hardware takes care of all
* compress / decompress . However there are many known cases where we have to
* forcibly disable it to allow proper screen updates .
2014-12-09 00:09:10 +08:00
*/
2019-01-18 05:03:34 +08:00
# include <drm/drm_fourcc.h>
2014-12-08 22:46:31 +08:00
# include "intel_drv.h"
# include "i915_drv.h"
2015-09-23 23:52:27 +08:00
static inline bool fbc_supported ( struct drm_i915_private * dev_priv )
{
2016-01-30 04:57:39 +08:00
return HAS_FBC ( dev_priv ) ;
2015-09-23 23:52:27 +08:00
}
2016-01-19 21:35:48 +08:00
static inline bool no_fbc_on_multiple_pipes ( struct drm_i915_private * dev_priv )
{
2016-11-12 00:57:41 +08:00
return INTEL_GEN ( dev_priv ) < = 3 ;
2016-01-19 21:35:48 +08:00
}
2015-09-15 02:20:03 +08:00
/*
* In some platforms where the CRTC ' s x : 0 / y : 0 coordinates doesn ' t match the
* frontbuffer ' s x : 0 / y : 0 coordinates we lie to the hardware about the plane ' s
* origin so the x and y offsets can actually fit the registers . As a
* consequence , the fence doesn ' t really start exactly at the display plane
* address we program because it starts at the real start of the buffer , so we
* have to take this into consideration here .
*/
2017-10-18 04:08:11 +08:00
static unsigned int get_crtc_fence_y_offset ( struct intel_fbc * fbc )
2015-09-15 02:20:03 +08:00
{
2017-10-18 04:08:11 +08:00
return fbc - > state_cache . plane . y - fbc - > state_cache . plane . adjusted_y ;
2015-09-15 02:20:03 +08:00
}
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
/*
* For SKL + , the plane source size used by the hardware is based on the value we
* write to the PLANE_SIZE register . For BDW - , the hardware looks at the value
* we wrote to PIPESRC .
*/
2016-01-19 21:35:42 +08:00
static void intel_fbc_get_plane_source_size ( struct intel_fbc_state_cache * cache ,
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
int * width , int * height )
{
if ( width )
2017-04-01 02:00:56 +08:00
* width = cache - > plane . src_w ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
if ( height )
2017-04-01 02:00:56 +08:00
* height = cache - > plane . src_h ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
}
2016-01-19 21:35:42 +08:00
static int intel_fbc_calculate_cfb_size ( struct drm_i915_private * dev_priv ,
struct intel_fbc_state_cache * cache )
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
{
int lines ;
2016-01-19 21:35:42 +08:00
intel_fbc_get_plane_source_size ( cache , NULL , & lines ) ;
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 7 ) )
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
lines = min ( lines , 2048 ) ;
2016-10-21 23:55:45 +08:00
else if ( INTEL_GEN ( dev_priv ) > = 8 )
lines = min ( lines , 2560 ) ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
/* Hardware needs the full buffer stride, not just the active area. */
2016-01-19 21:35:42 +08:00
return lines * cache - > fb . stride ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
}
2015-10-15 04:45:36 +08:00
static void i8xx_fbc_deactivate ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
u32 fbc_ctl ;
/* Disable compression */
fbc_ctl = I915_READ ( FBC_CONTROL ) ;
if ( ( fbc_ctl & FBC_CTL_EN ) = = 0 )
return ;
fbc_ctl & = ~ FBC_CTL_EN ;
I915_WRITE ( FBC_CONTROL , fbc_ctl ) ;
/* Wait for compressing bit to clear */
2016-06-30 22:33:21 +08:00
if ( intel_wait_for_register ( dev_priv ,
FBC_STATUS , FBC_STAT_COMPRESSING , 0 ,
10 ) ) {
2014-12-09 00:09:10 +08:00
DRM_DEBUG_KMS ( " FBC idle timed out \n " ) ;
return ;
}
}
2015-12-24 04:28:11 +08:00
static void i8xx_fbc_activate ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
2015-12-24 04:28:11 +08:00
struct intel_fbc_reg_params * params = & dev_priv - > fbc . params ;
2014-12-09 00:09:10 +08:00
int cfb_pitch ;
int i ;
u32 fbc_ctl ;
2015-02-05 18:04:27 +08:00
/* Note: fbc.threshold == 1 for i8xx */
2015-12-24 04:28:11 +08:00
cfb_pitch = params - > cfb_size / FBC_LL_SIZE ;
if ( params - > fb . stride < cfb_pitch )
cfb_pitch = params - > fb . stride ;
2014-12-09 00:09:10 +08:00
/* FBC_CTL wants 32B or 64B units */
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 2 ) )
2014-12-09 00:09:10 +08:00
cfb_pitch = ( cfb_pitch / 32 ) - 1 ;
else
cfb_pitch = ( cfb_pitch / 64 ) - 1 ;
/* Clear old tags */
for ( i = 0 ; i < ( FBC_LL_SIZE / 32 ) + 1 ; i + + )
2015-09-19 01:03:18 +08:00
I915_WRITE ( FBC_TAG ( i ) , 0 ) ;
2014-12-09 00:09:10 +08:00
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 4 ) ) {
2014-12-09 00:09:10 +08:00
u32 fbc_ctl2 ;
/* Set it up... */
fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE ;
2017-11-18 03:19:10 +08:00
fbc_ctl2 | = FBC_CTL_PLANE ( params - > crtc . i9xx_plane ) ;
2014-12-09 00:09:10 +08:00
I915_WRITE ( FBC_CONTROL2 , fbc_ctl2 ) ;
2015-12-24 04:28:11 +08:00
I915_WRITE ( FBC_FENCE_OFF , params - > crtc . fence_y_offset ) ;
2014-12-09 00:09:10 +08:00
}
/* enable it... */
fbc_ctl = I915_READ ( FBC_CONTROL ) ;
fbc_ctl & = 0x3fff < < FBC_CTL_INTERVAL_SHIFT ;
fbc_ctl | = FBC_CTL_EN | FBC_CTL_PERIODIC ;
2015-07-08 02:26:04 +08:00
if ( IS_I945GM ( dev_priv ) )
2014-12-09 00:09:10 +08:00
fbc_ctl | = FBC_CTL_C3_IDLE ; /* 945 needs special SR handling */
fbc_ctl | = ( cfb_pitch & 0xff ) < < FBC_CTL_STRIDE_SHIFT ;
2017-01-16 23:21:27 +08:00
fbc_ctl | = params - > vma - > fence - > id ;
2014-12-09 00:09:10 +08:00
I915_WRITE ( FBC_CONTROL , fbc_ctl ) ;
}
2015-10-15 04:45:36 +08:00
static bool i8xx_fbc_is_active ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
return I915_READ ( FBC_CONTROL ) & FBC_CTL_EN ;
}
2015-12-24 04:28:11 +08:00
static void g4x_fbc_activate ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
2015-12-24 04:28:11 +08:00
struct intel_fbc_reg_params * params = & dev_priv - > fbc . params ;
2014-12-09 00:09:10 +08:00
u32 dpfc_ctl ;
2017-11-18 03:19:10 +08:00
dpfc_ctl = DPFC_CTL_PLANE ( params - > crtc . i9xx_plane ) | DPFC_SR_EN ;
2016-11-19 03:53:04 +08:00
if ( params - > fb . format - > cpp [ 0 ] = = 2 )
2014-12-09 00:09:10 +08:00
dpfc_ctl | = DPFC_CTL_LIMIT_2X ;
else
dpfc_ctl | = DPFC_CTL_LIMIT_1X ;
2018-02-20 21:42:08 +08:00
if ( params - > flags & PLANE_HAS_FENCE ) {
2017-01-16 23:21:27 +08:00
dpfc_ctl | = DPFC_CTL_FENCE_EN | params - > vma - > fence - > id ;
2016-08-19 23:54:24 +08:00
I915_WRITE ( DPFC_FENCE_YOFF , params - > crtc . fence_y_offset ) ;
} else {
I915_WRITE ( DPFC_FENCE_YOFF , 0 ) ;
}
2014-12-09 00:09:10 +08:00
/* enable it... */
I915_WRITE ( DPFC_CONTROL , dpfc_ctl | DPFC_CTL_EN ) ;
}
2015-10-15 04:45:36 +08:00
static void g4x_fbc_deactivate ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
u32 dpfc_ctl ;
/* Disable compression */
dpfc_ctl = I915_READ ( DPFC_CONTROL ) ;
if ( dpfc_ctl & DPFC_CTL_EN ) {
dpfc_ctl & = ~ DPFC_CTL_EN ;
I915_WRITE ( DPFC_CONTROL , dpfc_ctl ) ;
}
}
2015-10-15 04:45:36 +08:00
static bool g4x_fbc_is_active ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
return I915_READ ( DPFC_CONTROL ) & DPFC_CTL_EN ;
}
2015-11-05 03:10:45 +08:00
/* This function forces a CFB recompression through the nuke operation. */
static void intel_fbc_recompress ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
2015-02-14 03:23:46 +08:00
I915_WRITE ( MSG_FBC_REND_STATE , FBC_REND_NUKE ) ;
POSTING_READ ( MSG_FBC_REND_STATE ) ;
2014-12-09 00:09:10 +08:00
}
2015-12-24 04:28:11 +08:00
static void ilk_fbc_activate ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
2015-12-24 04:28:11 +08:00
struct intel_fbc_reg_params * params = & dev_priv - > fbc . params ;
2014-12-09 00:09:10 +08:00
u32 dpfc_ctl ;
2015-06-30 21:53:05 +08:00
int threshold = dev_priv - > fbc . threshold ;
2014-12-09 00:09:10 +08:00
2017-11-18 03:19:10 +08:00
dpfc_ctl = DPFC_CTL_PLANE ( params - > crtc . i9xx_plane ) ;
2016-11-19 03:53:04 +08:00
if ( params - > fb . format - > cpp [ 0 ] = = 2 )
2015-06-30 21:53:05 +08:00
threshold + + ;
2014-12-09 00:09:10 +08:00
2015-06-30 21:53:05 +08:00
switch ( threshold ) {
2014-12-09 00:09:10 +08:00
case 4 :
case 3 :
dpfc_ctl | = DPFC_CTL_LIMIT_4X ;
break ;
case 2 :
dpfc_ctl | = DPFC_CTL_LIMIT_2X ;
break ;
case 1 :
dpfc_ctl | = DPFC_CTL_LIMIT_1X ;
break ;
}
2016-08-19 23:54:24 +08:00
2018-02-20 21:42:08 +08:00
if ( params - > flags & PLANE_HAS_FENCE ) {
2016-08-19 23:54:24 +08:00
dpfc_ctl | = DPFC_CTL_FENCE_EN ;
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 5 ) )
2017-01-16 23:21:27 +08:00
dpfc_ctl | = params - > vma - > fence - > id ;
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 6 ) ) {
2016-08-19 23:54:24 +08:00
I915_WRITE ( SNB_DPFC_CTL_SA ,
2017-01-16 23:21:27 +08:00
SNB_CPU_FENCE_ENABLE |
params - > vma - > fence - > id ) ;
2016-08-19 23:54:24 +08:00
I915_WRITE ( DPFC_CPU_FENCE_OFFSET ,
params - > crtc . fence_y_offset ) ;
}
} else {
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 6 ) ) {
2016-08-19 23:54:24 +08:00
I915_WRITE ( SNB_DPFC_CTL_SA , 0 ) ;
I915_WRITE ( DPFC_CPU_FENCE_OFFSET , 0 ) ;
}
}
2014-12-09 00:09:10 +08:00
2015-12-24 04:28:11 +08:00
I915_WRITE ( ILK_DPFC_FENCE_YOFF , params - > crtc . fence_y_offset ) ;
2017-01-16 23:21:27 +08:00
I915_WRITE ( ILK_FBC_RT_BASE ,
i915_ggtt_offset ( params - > vma ) | ILK_FBC_RT_VALID ) ;
2014-12-09 00:09:10 +08:00
/* enable it... */
I915_WRITE ( ILK_DPFC_CONTROL , dpfc_ctl | DPFC_CTL_EN ) ;
2015-11-05 03:10:45 +08:00
intel_fbc_recompress ( dev_priv ) ;
2014-12-09 00:09:10 +08:00
}
2015-10-15 04:45:36 +08:00
static void ilk_fbc_deactivate ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
u32 dpfc_ctl ;
/* Disable compression */
dpfc_ctl = I915_READ ( ILK_DPFC_CONTROL ) ;
if ( dpfc_ctl & DPFC_CTL_EN ) {
dpfc_ctl & = ~ DPFC_CTL_EN ;
I915_WRITE ( ILK_DPFC_CONTROL , dpfc_ctl ) ;
}
}
2015-10-15 04:45:36 +08:00
static bool ilk_fbc_is_active ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
return I915_READ ( ILK_DPFC_CONTROL ) & DPFC_CTL_EN ;
}
2015-12-24 04:28:11 +08:00
static void gen7_fbc_activate ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
2015-12-24 04:28:11 +08:00
struct intel_fbc_reg_params * params = & dev_priv - > fbc . params ;
2014-12-09 00:09:10 +08:00
u32 dpfc_ctl ;
2015-06-30 21:53:05 +08:00
int threshold = dev_priv - > fbc . threshold ;
2014-12-09 00:09:10 +08:00
2017-08-11 02:30:33 +08:00
/* Display WA #0529: skl, kbl, bxt. */
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 9 ) & & ! IS_GEMINILAKE ( dev_priv ) ) {
2017-08-11 02:30:33 +08:00
u32 val = I915_READ ( CHICKEN_MISC_4 ) ;
val & = ~ ( FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK ) ;
if ( i915_gem_object_get_tiling ( params - > vma - > obj ) ! =
I915_TILING_X )
val | = FBC_STRIDE_OVERRIDE | params - > gen9_wa_cfb_stride ;
I915_WRITE ( CHICKEN_MISC_4 , val ) ;
}
2015-06-13 01:36:21 +08:00
dpfc_ctl = 0 ;
2015-07-08 02:26:04 +08:00
if ( IS_IVYBRIDGE ( dev_priv ) )
2017-11-18 03:19:10 +08:00
dpfc_ctl | = IVB_DPFC_CTL_PLANE ( params - > crtc . i9xx_plane ) ;
2015-06-13 01:36:21 +08:00
2016-11-19 03:53:04 +08:00
if ( params - > fb . format - > cpp [ 0 ] = = 2 )
2015-06-30 21:53:05 +08:00
threshold + + ;
2014-12-09 00:09:10 +08:00
2015-06-30 21:53:05 +08:00
switch ( threshold ) {
2014-12-09 00:09:10 +08:00
case 4 :
case 3 :
dpfc_ctl | = DPFC_CTL_LIMIT_4X ;
break ;
case 2 :
dpfc_ctl | = DPFC_CTL_LIMIT_2X ;
break ;
case 1 :
dpfc_ctl | = DPFC_CTL_LIMIT_1X ;
break ;
}
2018-02-20 21:42:08 +08:00
if ( params - > flags & PLANE_HAS_FENCE ) {
2016-08-19 23:54:24 +08:00
dpfc_ctl | = IVB_DPFC_CTL_FENCE_EN ;
I915_WRITE ( SNB_DPFC_CTL_SA ,
2017-01-16 23:21:27 +08:00
SNB_CPU_FENCE_ENABLE |
params - > vma - > fence - > id ) ;
2016-08-19 23:54:24 +08:00
I915_WRITE ( DPFC_CPU_FENCE_OFFSET , params - > crtc . fence_y_offset ) ;
} else {
I915_WRITE ( SNB_DPFC_CTL_SA , 0 ) ;
I915_WRITE ( DPFC_CPU_FENCE_OFFSET , 0 ) ;
}
2014-12-09 00:09:10 +08:00
if ( dev_priv - > fbc . false_color )
dpfc_ctl | = FBC_CTL_FALSE_COLOR ;
2015-07-08 02:26:04 +08:00
if ( IS_IVYBRIDGE ( dev_priv ) ) {
2014-12-09 00:09:10 +08:00
/* WaFbcAsynchFlipDisableFbcQueue:ivb */
I915_WRITE ( ILK_DISPLAY_CHICKEN1 ,
I915_READ ( ILK_DISPLAY_CHICKEN1 ) |
ILK_FBCQ_DIS ) ;
2015-09-15 02:20:01 +08:00
} else if ( IS_HASWELL ( dev_priv ) | | IS_BROADWELL ( dev_priv ) ) {
2014-12-09 00:09:10 +08:00
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
2015-12-24 04:28:11 +08:00
I915_WRITE ( CHICKEN_PIPESL_1 ( params - > crtc . pipe ) ,
I915_READ ( CHICKEN_PIPESL_1 ( params - > crtc . pipe ) ) |
2014-12-09 00:09:10 +08:00
HSW_FBCQ_DIS ) ;
}
2015-09-15 02:20:00 +08:00
I915_WRITE ( ILK_DPFC_CONTROL , dpfc_ctl | DPFC_CTL_EN ) ;
2015-11-05 03:10:45 +08:00
intel_fbc_recompress ( dev_priv ) ;
2014-12-09 00:09:10 +08:00
}
2016-01-30 04:57:39 +08:00
static bool intel_fbc_hw_is_active ( struct drm_i915_private * dev_priv )
{
2016-11-12 00:57:41 +08:00
if ( INTEL_GEN ( dev_priv ) > = 5 )
2016-01-30 04:57:39 +08:00
return ilk_fbc_is_active ( dev_priv ) ;
else if ( IS_GM45 ( dev_priv ) )
return g4x_fbc_is_active ( dev_priv ) ;
else
return i8xx_fbc_is_active ( dev_priv ) ;
}
static void intel_fbc_hw_activate ( struct drm_i915_private * dev_priv )
{
2016-01-30 04:57:40 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
fbc - > active = true ;
2016-11-12 00:57:41 +08:00
if ( INTEL_GEN ( dev_priv ) > = 7 )
2016-01-30 04:57:39 +08:00
gen7_fbc_activate ( dev_priv ) ;
2016-11-12 00:57:41 +08:00
else if ( INTEL_GEN ( dev_priv ) > = 5 )
2016-01-30 04:57:39 +08:00
ilk_fbc_activate ( dev_priv ) ;
else if ( IS_GM45 ( dev_priv ) )
g4x_fbc_activate ( dev_priv ) ;
else
i8xx_fbc_activate ( dev_priv ) ;
}
static void intel_fbc_hw_deactivate ( struct drm_i915_private * dev_priv )
{
2016-01-30 04:57:40 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
fbc - > active = false ;
2016-11-12 00:57:41 +08:00
if ( INTEL_GEN ( dev_priv ) > = 5 )
2016-01-30 04:57:39 +08:00
ilk_fbc_deactivate ( dev_priv ) ;
else if ( IS_GM45 ( dev_priv ) )
g4x_fbc_deactivate ( dev_priv ) ;
else
i8xx_fbc_deactivate ( dev_priv ) ;
}
2014-12-08 22:46:31 +08:00
/**
2015-10-15 04:45:36 +08:00
* intel_fbc_is_active - Is FBC active ?
2015-07-08 02:26:04 +08:00
* @ dev_priv : i915 device instance
2014-12-08 22:46:31 +08:00
*
* This function is used to verify the current state of FBC .
2016-06-02 05:40:36 +08:00
*
2014-12-08 22:46:31 +08:00
* FIXME : This should be tracked in the plane config eventually
2016-06-02 05:40:36 +08:00
* instead of queried at runtime for most callers .
2014-12-08 22:46:31 +08:00
*/
2015-10-15 04:45:36 +08:00
bool intel_fbc_is_active ( struct drm_i915_private * dev_priv )
2014-12-09 00:09:10 +08:00
{
2015-10-15 04:45:36 +08:00
return dev_priv - > fbc . active ;
2014-12-09 00:09:10 +08:00
}
2018-01-26 06:41:22 +08:00
static void intel_fbc_deactivate ( struct drm_i915_private * dev_priv ,
const char * reason )
2015-07-03 06:25:10 +08:00
{
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
WARN_ON ( ! mutex_is_locked ( & fbc - > lock ) ) ;
2015-07-03 06:25:10 +08:00
2016-01-12 03:44:36 +08:00
if ( fbc - > active )
2016-01-30 04:57:39 +08:00
intel_fbc_hw_deactivate ( dev_priv ) ;
2018-01-26 06:41:22 +08:00
fbc - > no_fbc_reason = reason ;
2015-10-14 06:13:25 +08:00
}
2016-06-14 20:24:20 +08:00
static bool multiple_pipes_ok ( struct intel_crtc * crtc ,
struct intel_plane_state * plane_state )
2015-07-08 02:26:07 +08:00
{
2016-06-14 20:24:20 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-19 21:35:48 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
enum pipe pipe = crtc - > pipe ;
2015-07-08 02:26:07 +08:00
2016-01-19 21:35:48 +08:00
/* Don't even bother tracking anything we don't need. */
if ( ! no_fbc_on_multiple_pipes ( dev_priv ) )
2015-07-08 02:26:07 +08:00
return true ;
2016-07-27 00:06:59 +08:00
if ( plane_state - > base . visible )
2016-01-19 21:35:48 +08:00
fbc - > visible_pipes_mask | = ( 1 < < pipe ) ;
else
fbc - > visible_pipes_mask & = ~ ( 1 < < pipe ) ;
2015-07-08 02:26:07 +08:00
2016-01-19 21:35:48 +08:00
return ( fbc - > visible_pipes_mask & ~ ( 1 < < pipe ) ) ! = 0 ;
2015-07-08 02:26:07 +08:00
}
2015-07-08 02:26:04 +08:00
static int find_compression_threshold ( struct drm_i915_private * dev_priv ,
2015-07-03 06:25:08 +08:00
struct drm_mm_node * node ,
int size ,
int fb_cpp )
{
int compression_threshold = 1 ;
int ret ;
2015-09-15 02:19:57 +08:00
u64 end ;
/* The FBC hardware for BDW/SKL doesn't have access to the stolen
* reserved range size , so it always assumes the maximum ( 8 mb ) is used .
* If we enable FBC using a CFB on that memory range we ' ll get FIFO
* underruns , even if that range is not reserved by the BIOS . */
2017-01-24 02:32:37 +08:00
if ( IS_BROADWELL ( dev_priv ) | | IS_GEN9_BC ( dev_priv ) )
2017-12-11 23:18:18 +08:00
end = resource_size ( & dev_priv - > dsm ) - 8 * 1024 * 1024 ;
2015-09-15 02:19:57 +08:00
else
2016-12-15 21:23:55 +08:00
end = U64_MAX ;
2015-07-03 06:25:08 +08:00
/* HACK: This code depends on what we will do in *_enable_fbc. If that
* code changes , this code needs to change as well .
*
* The enable_fbc code will attempt to use one of our 2 compression
* thresholds , therefore , in that case , we only have 1 resort .
*/
/* Try to over-allocate to reduce reallocations and fragmentation. */
2015-09-15 02:19:57 +08:00
ret = i915_gem_stolen_insert_node_in_range ( dev_priv , node , size < < = 1 ,
4096 , 0 , end ) ;
2015-07-03 06:25:08 +08:00
if ( ret = = 0 )
return compression_threshold ;
again :
/* HW's ability to limit the CFB is 1:4 */
if ( compression_threshold > 4 | |
( fb_cpp = = 2 & & compression_threshold = = 2 ) )
return 0 ;
2015-09-15 02:19:57 +08:00
ret = i915_gem_stolen_insert_node_in_range ( dev_priv , node , size > > = 1 ,
4096 , 0 , end ) ;
2016-11-12 00:57:41 +08:00
if ( ret & & INTEL_GEN ( dev_priv ) < = 4 ) {
2015-07-03 06:25:08 +08:00
return 0 ;
} else if ( ret ) {
compression_threshold < < = 1 ;
goto again ;
} else {
return compression_threshold ;
}
}
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
static int intel_fbc_alloc_cfb ( struct intel_crtc * crtc )
2015-07-03 06:25:08 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-07-03 06:25:08 +08:00
struct drm_mm_node * uninitialized_var ( compressed_llb ) ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
int size , fb_cpp , ret ;
2016-01-12 03:44:36 +08:00
WARN_ON ( drm_mm_node_allocated ( & fbc - > compressed_fb ) ) ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
2016-01-19 21:35:42 +08:00
size = intel_fbc_calculate_cfb_size ( dev_priv , & fbc - > state_cache ) ;
2016-11-19 03:53:04 +08:00
fb_cpp = fbc - > state_cache . fb . format - > cpp [ 0 ] ;
2015-07-03 06:25:08 +08:00
2016-01-12 03:44:36 +08:00
ret = find_compression_threshold ( dev_priv , & fbc - > compressed_fb ,
2015-07-03 06:25:08 +08:00
size , fb_cpp ) ;
if ( ! ret )
goto err_llb ;
else if ( ret > 1 ) {
DRM_INFO ( " Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. \n " ) ;
}
2016-01-12 03:44:36 +08:00
fbc - > threshold = ret ;
2015-07-03 06:25:08 +08:00
2016-11-12 00:57:41 +08:00
if ( INTEL_GEN ( dev_priv ) > = 5 )
2016-01-12 03:44:36 +08:00
I915_WRITE ( ILK_DPFC_CB_BASE , fbc - > compressed_fb . start ) ;
2015-07-08 02:26:04 +08:00
else if ( IS_GM45 ( dev_priv ) ) {
2016-01-12 03:44:36 +08:00
I915_WRITE ( DPFC_CB_BASE , fbc - > compressed_fb . start ) ;
2015-07-03 06:25:08 +08:00
} else {
compressed_llb = kzalloc ( sizeof ( * compressed_llb ) , GFP_KERNEL ) ;
if ( ! compressed_llb )
goto err_fb ;
ret = i915_gem_stolen_insert_node ( dev_priv , compressed_llb ,
4096 , 4096 ) ;
if ( ret )
goto err_fb ;
2016-01-12 03:44:36 +08:00
fbc - > compressed_llb = compressed_llb ;
2015-07-03 06:25:08 +08:00
2017-12-11 23:18:18 +08:00
GEM_BUG_ON ( range_overflows_t ( u64 , dev_priv - > dsm . start ,
fbc - > compressed_fb . start ,
U32_MAX ) ) ;
GEM_BUG_ON ( range_overflows_t ( u64 , dev_priv - > dsm . start ,
fbc - > compressed_llb - > start ,
U32_MAX ) ) ;
2015-07-03 06:25:08 +08:00
I915_WRITE ( FBC_CFB_BASE ,
2017-12-11 23:18:18 +08:00
dev_priv - > dsm . start + fbc - > compressed_fb . start ) ;
2015-07-03 06:25:08 +08:00
I915_WRITE ( FBC_LL_BASE ,
2017-12-11 23:18:18 +08:00
dev_priv - > dsm . start + compressed_llb - > start ) ;
2015-07-03 06:25:08 +08:00
}
2015-09-15 02:19:58 +08:00
DRM_DEBUG_KMS ( " reserved %llu bytes of contiguous stolen space for FBC, threshold: %d \n " ,
2016-01-12 03:44:36 +08:00
fbc - > compressed_fb . size , fbc - > threshold ) ;
2015-07-03 06:25:08 +08:00
return 0 ;
err_fb :
kfree ( compressed_llb ) ;
2016-01-12 03:44:36 +08:00
i915_gem_stolen_remove_node ( dev_priv , & fbc - > compressed_fb ) ;
2015-07-03 06:25:08 +08:00
err_llb :
2017-02-23 20:20:37 +08:00
if ( drm_mm_initialized ( & dev_priv - > mm . stolen ) )
pr_info_once ( " drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this. \n " , size ) ;
2015-07-03 06:25:08 +08:00
return - ENOSPC ;
}
2015-07-08 02:26:04 +08:00
static void __intel_fbc_cleanup_cfb ( struct drm_i915_private * dev_priv )
2015-07-03 06:25:08 +08:00
{
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
if ( drm_mm_node_allocated ( & fbc - > compressed_fb ) )
i915_gem_stolen_remove_node ( dev_priv , & fbc - > compressed_fb ) ;
if ( fbc - > compressed_llb ) {
i915_gem_stolen_remove_node ( dev_priv , fbc - > compressed_llb ) ;
kfree ( fbc - > compressed_llb ) ;
2015-07-03 06:25:08 +08:00
}
}
2015-07-08 02:26:04 +08:00
void intel_fbc_cleanup_cfb ( struct drm_i915_private * dev_priv )
2015-07-03 06:25:10 +08:00
{
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-09-23 23:52:27 +08:00
if ( ! fbc_supported ( dev_priv ) )
2015-07-04 02:40:54 +08:00
return ;
2016-01-12 03:44:36 +08:00
mutex_lock ( & fbc - > lock ) ;
2015-07-08 02:26:04 +08:00
__intel_fbc_cleanup_cfb ( dev_priv ) ;
2016-01-12 03:44:36 +08:00
mutex_unlock ( & fbc - > lock ) ;
2015-07-03 06:25:10 +08:00
}
2015-09-15 02:19:56 +08:00
static bool stride_is_valid ( struct drm_i915_private * dev_priv ,
unsigned int stride )
{
2018-01-16 23:53:31 +08:00
/* This should have been caught earlier. */
if ( WARN_ON_ONCE ( ( stride & ( 64 - 1 ) ) ! = 0 ) )
return false ;
2015-09-15 02:19:56 +08:00
/* Below are the additional FBC restrictions. */
2018-01-16 23:53:31 +08:00
if ( stride < 512 )
return false ;
2015-09-15 02:19:56 +08:00
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 2 ) | | IS_GEN ( dev_priv , 3 ) )
2015-09-15 02:19:56 +08:00
return stride = = 4096 | | stride = = 8192 ;
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 4 ) & & ! IS_G4X ( dev_priv ) & & stride < 2048 )
2015-09-15 02:19:56 +08:00
return false ;
if ( stride > 16384 )
return false ;
return true ;
}
2016-01-19 21:35:42 +08:00
static bool pixel_format_is_valid ( struct drm_i915_private * dev_priv ,
2019-01-16 17:15:19 +08:00
u32 pixel_format )
2015-09-22 06:48:06 +08:00
{
2016-01-19 21:35:42 +08:00
switch ( pixel_format ) {
2015-09-22 06:48:06 +08:00
case DRM_FORMAT_XRGB8888 :
case DRM_FORMAT_XBGR8888 :
return true ;
case DRM_FORMAT_XRGB1555 :
case DRM_FORMAT_RGB565 :
/* 16bpp not supported on gen2 */
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 2 ) )
2015-09-22 06:48:06 +08:00
return false ;
/* WaFbcOnly1to1Ratio:ctg */
if ( IS_G4X ( dev_priv ) )
return false ;
return true ;
default :
return false ;
}
}
2015-10-02 06:57:12 +08:00
/*
* For some reason , the hardware tracking starts looking at whatever we
* programmed as the display plane base address register . It does not look at
* the X and Y offset registers . That ' s why we look at the crtc - > adjusted { x , y }
* variables instead of just looking at the pipe / plane size .
*/
static bool intel_fbc_hw_tracking_covers_screen ( struct intel_crtc * crtc )
2015-09-23 23:52:24 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-19 21:35:42 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-10-02 06:57:12 +08:00
unsigned int effective_w , effective_h , max_w , max_h ;
2015-09-23 23:52:24 +08:00
2018-12-05 08:48:23 +08:00
if ( INTEL_GEN ( dev_priv ) > = 10 | | IS_GEMINILAKE ( dev_priv ) ) {
max_w = 5120 ;
max_h = 4096 ;
} else if ( INTEL_GEN ( dev_priv ) > = 8 | | IS_HASWELL ( dev_priv ) ) {
2015-09-23 23:52:24 +08:00
max_w = 4096 ;
max_h = 4096 ;
2016-11-12 00:57:41 +08:00
} else if ( IS_G4X ( dev_priv ) | | INTEL_GEN ( dev_priv ) > = 5 ) {
2015-09-23 23:52:24 +08:00
max_w = 4096 ;
max_h = 2048 ;
} else {
max_w = 2048 ;
max_h = 1536 ;
}
2016-01-19 21:35:42 +08:00
intel_fbc_get_plane_source_size ( & fbc - > state_cache , & effective_w ,
& effective_h ) ;
2017-10-18 04:08:07 +08:00
effective_w + = fbc - > state_cache . plane . adjusted_x ;
effective_h + = fbc - > state_cache . plane . adjusted_y ;
2015-10-02 06:57:12 +08:00
return effective_w < = max_w & & effective_h < = max_h ;
2015-09-23 23:52:24 +08:00
}
2016-06-14 20:24:20 +08:00
static void intel_fbc_update_state_cache ( struct intel_crtc * crtc ,
struct intel_crtc_state * crtc_state ,
struct intel_plane_state * plane_state )
2014-12-09 00:09:10 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2016-01-19 21:35:42 +08:00
struct intel_fbc_state_cache * cache = & fbc - > state_cache ;
struct drm_framebuffer * fb = plane_state - > base . fb ;
2017-01-16 23:21:27 +08:00
cache - > vma = NULL ;
2018-02-20 21:42:08 +08:00
cache - > flags = 0 ;
2014-12-09 00:09:10 +08:00
2016-01-19 21:35:42 +08:00
cache - > crtc . mode_flags = crtc_state - > base . adjusted_mode . flags ;
if ( IS_HASWELL ( dev_priv ) | | IS_BROADWELL ( dev_priv ) )
2017-01-27 03:50:31 +08:00
cache - > crtc . hsw_bdw_pixel_rate = crtc_state - > pixel_rate ;
2016-01-19 21:35:42 +08:00
cache - > plane . rotation = plane_state - > base . rotation ;
2017-04-01 02:00:56 +08:00
/*
* Src coordinates are already rotated by 270 degrees for
* the 90 / 270 degree plane rotation cases ( to match the
* GTT mapping ) , hence no need to account for rotation here .
*/
2016-07-27 00:06:59 +08:00
cache - > plane . src_w = drm_rect_width ( & plane_state - > base . src ) > > 16 ;
cache - > plane . src_h = drm_rect_height ( & plane_state - > base . src ) > > 16 ;
cache - > plane . visible = plane_state - > base . visible ;
2018-09-07 23:24:04 +08:00
cache - > plane . adjusted_x = plane_state - > color_plane [ 0 ] . x ;
cache - > plane . adjusted_y = plane_state - > color_plane [ 0 ] . y ;
2017-10-18 04:08:11 +08:00
cache - > plane . y = plane_state - > base . src . y1 > > 16 ;
2016-01-19 21:35:42 +08:00
2018-08-15 18:34:05 +08:00
cache - > plane . pixel_blend_mode = plane_state - > base . pixel_blend_mode ;
2016-01-19 21:35:42 +08:00
if ( ! cache - > plane . visible )
return ;
2014-12-09 00:09:10 +08:00
2016-11-19 03:53:04 +08:00
cache - > fb . format = fb - > format ;
2016-01-19 21:35:42 +08:00
cache - > fb . stride = fb - > pitches [ 0 ] ;
2017-01-16 23:21:27 +08:00
cache - > vma = plane_state - > vma ;
2018-02-20 21:42:08 +08:00
cache - > flags = plane_state - > flags ;
if ( WARN_ON ( cache - > flags & PLANE_HAS_FENCE & & ! cache - > vma - > fence ) )
cache - > flags & = ~ PLANE_HAS_FENCE ;
2016-01-19 21:35:42 +08:00
}
static bool intel_fbc_can_activate ( struct intel_crtc * crtc )
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-19 21:35:42 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
struct intel_fbc_state_cache * cache = & fbc - > state_cache ;
2016-09-13 21:38:57 +08:00
/* We don't need to use a state cache here since this information is
* global for all CRTC .
*/
if ( fbc - > underrun_detected ) {
fbc - > no_fbc_reason = " underrun detected " ;
return false ;
}
2017-01-16 23:21:27 +08:00
if ( ! cache - > vma ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " primary plane not visible " ;
2016-01-19 21:35:35 +08:00
return false ;
}
2014-12-09 00:09:10 +08:00
2017-11-15 02:32:58 +08:00
if ( cache - > crtc . mode_flags & DRM_MODE_FLAG_INTERLACE ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " incompatible mode " ;
2016-01-19 21:35:35 +08:00
return false ;
2014-12-09 00:09:10 +08:00
}
2015-11-05 03:10:49 +08:00
if ( ! intel_fbc_hw_tracking_covers_screen ( crtc ) ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " mode too large for compression " ;
2016-01-19 21:35:35 +08:00
return false ;
2014-12-09 00:09:10 +08:00
}
2015-09-23 23:52:24 +08:00
2014-12-09 00:09:10 +08:00
/* The use of a CPU fence is mandatory in order to detect writes
* by the CPU to the scanout and trigger updates to the FBC .
2016-08-19 00:17:06 +08:00
*
* Note that is possible for a tiled surface to be unmappable ( and
* so have no fence associated with it ) due to aperture constaints
* at the time of pinning .
2018-02-22 00:02:35 +08:00
*
* FIXME with 90 / 270 degree rotation we should use the fence on
* the normal GTT view ( the rotated view doesn ' t even have a
* fence ) . Would need changes to the FBC fence Y offset as well .
* For now this will effecively disable FBC with 90 / 270 degree
* rotation .
2014-12-09 00:09:10 +08:00
*/
2018-02-20 21:42:08 +08:00
if ( ! ( cache - > flags & PLANE_HAS_FENCE ) ) {
2016-08-25 02:00:53 +08:00
fbc - > no_fbc_reason = " framebuffer not tiled or fenced " ;
return false ;
2014-12-09 00:09:10 +08:00
}
2016-11-12 00:57:41 +08:00
if ( INTEL_GEN ( dev_priv ) < = 4 & & ! IS_G4X ( dev_priv ) & &
2017-05-20 04:50:17 +08:00
cache - > plane . rotation ! = DRM_MODE_ROTATE_0 ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " rotation unsupported " ;
2016-01-19 21:35:35 +08:00
return false ;
2014-12-09 00:09:10 +08:00
}
2016-01-19 21:35:42 +08:00
if ( ! stride_is_valid ( dev_priv , cache - > fb . stride ) ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " framebuffer stride not supported " ;
2016-01-19 21:35:35 +08:00
return false ;
2015-09-15 02:19:56 +08:00
}
2016-11-19 03:53:04 +08:00
if ( ! pixel_format_is_valid ( dev_priv , cache - > fb . format - > format ) ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " pixel format is invalid " ;
2016-01-19 21:35:35 +08:00
return false ;
2015-09-22 06:48:06 +08:00
}
2018-08-15 18:34:05 +08:00
if ( cache - > plane . pixel_blend_mode ! = DRM_MODE_BLEND_PIXEL_NONE & &
cache - > fb . format - > has_alpha ) {
fbc - > no_fbc_reason = " per-pixel alpha blending is incompatible with FBC " ;
return false ;
}
2015-09-15 02:19:59 +08:00
/* WaFbcExceedCdClockThreshold:hsw,bdw */
if ( ( IS_HASWELL ( dev_priv ) | | IS_BROADWELL ( dev_priv ) ) & &
2017-02-08 02:33:45 +08:00
cache - > crtc . hsw_bdw_pixel_rate > = dev_priv - > cdclk . hw . cdclk * 95 / 100 ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " pixel rate is too big " ;
2016-01-19 21:35:35 +08:00
return false ;
2015-09-15 02:19:59 +08:00
}
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
/* It is possible for the required CFB size change without a
* crtc - > disable + crtc - > enable since it is possible to change the
* stride without triggering a full modeset . Since we try to
* over - allocate the CFB , there ' s a chance we may keep FBC enabled even
* if this happens , but if we exceed the current CFB size we ' ll have to
* disable FBC . Notice that it would be possible to disable FBC , wait
* for a frame , free the stolen node , then try to reenable FBC in case
* we didn ' t get any invalidate / deactivate calls , but this would require
* a lot of tracking just for a specific case . If we conclude it ' s an
* important case , we can implement it later . */
2016-01-19 21:35:42 +08:00
if ( intel_fbc_calculate_cfb_size ( dev_priv , & fbc - > state_cache ) >
2016-01-12 03:44:36 +08:00
fbc - > compressed_fb . size * fbc - > threshold ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " CFB requirements changed " ;
2016-01-19 21:35:35 +08:00
return false ;
}
2018-03-01 21:44:57 +08:00
/*
* Work around a problem on GEN9 + HW , where enabling FBC on a plane
* having a Y offset that isn ' t divisible by 4 causes FIFO underrun
* and screen flicker .
*/
2018-12-13 02:10:42 +08:00
if ( IS_GEN_RANGE ( dev_priv , 9 , 10 ) & &
2018-03-01 21:44:57 +08:00
( fbc - > state_cache . plane . adjusted_y & 3 ) ) {
fbc - > no_fbc_reason = " plane Y offset is misaligned " ;
return false ;
}
2016-01-19 21:35:35 +08:00
return true ;
}
2016-11-12 00:57:37 +08:00
static bool intel_fbc_can_enable ( struct drm_i915_private * dev_priv )
2016-01-19 21:35:36 +08:00
{
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2016-01-19 21:35:36 +08:00
2016-05-06 22:40:21 +08:00
if ( intel_vgpu_active ( dev_priv ) ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " VGPU is active " ;
2016-01-19 21:35:36 +08:00
return false ;
}
2017-09-20 03:38:44 +08:00
if ( ! i915_modparams . enable_fbc ) {
2016-04-14 03:01:09 +08:00
fbc - > no_fbc_reason = " disabled per module param or by default " ;
2016-01-19 21:35:36 +08:00
return false ;
}
2016-09-13 21:38:57 +08:00
if ( fbc - > underrun_detected ) {
fbc - > no_fbc_reason = " underrun detected " ;
return false ;
}
2016-11-12 00:57:37 +08:00
return true ;
}
2015-12-24 04:28:11 +08:00
static void intel_fbc_get_reg_params ( struct intel_crtc * crtc ,
struct intel_fbc_reg_params * params )
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-19 21:35:42 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
struct intel_fbc_state_cache * cache = & fbc - > state_cache ;
2015-12-24 04:28:11 +08:00
/* Since all our fields are integer types, use memset here so the
* comparison function can rely on memcmp because the padding will be
* zero . */
memset ( params , 0 , sizeof ( * params ) ) ;
2017-01-16 23:21:27 +08:00
params - > vma = cache - > vma ;
2018-02-20 21:42:08 +08:00
params - > flags = cache - > flags ;
2017-01-16 23:21:27 +08:00
2015-12-24 04:28:11 +08:00
params - > crtc . pipe = crtc - > pipe ;
2017-11-18 03:19:15 +08:00
params - > crtc . i9xx_plane = to_intel_plane ( crtc - > base . primary ) - > i9xx_plane ;
2017-10-18 04:08:11 +08:00
params - > crtc . fence_y_offset = get_crtc_fence_y_offset ( fbc ) ;
2015-12-24 04:28:11 +08:00
2016-11-19 03:53:04 +08:00
params - > fb . format = cache - > fb . format ;
2016-01-19 21:35:42 +08:00
params - > fb . stride = cache - > fb . stride ;
2015-12-24 04:28:11 +08:00
2016-01-19 21:35:42 +08:00
params - > cfb_size = intel_fbc_calculate_cfb_size ( dev_priv , cache ) ;
2017-08-11 02:30:33 +08:00
drm/i915: replace IS_GEN<N> with IS_GEN(..., N)
Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
gen_mask to do the comparison. Now callers can pass then gen as a parameter,
so we don't require one macro for each gen.
The following spatch was used to convert the users of these macros:
@@
expression e;
@@
(
- IS_GEN2(e)
+ IS_GEN(e, 2)
|
- IS_GEN3(e)
+ IS_GEN(e, 3)
|
- IS_GEN4(e)
+ IS_GEN(e, 4)
|
- IS_GEN5(e)
+ IS_GEN(e, 5)
|
- IS_GEN6(e)
+ IS_GEN(e, 6)
|
- IS_GEN7(e)
+ IS_GEN(e, 7)
|
- IS_GEN8(e)
+ IS_GEN(e, 8)
|
- IS_GEN9(e)
+ IS_GEN(e, 9)
|
- IS_GEN10(e)
+ IS_GEN(e, 10)
|
- IS_GEN11(e)
+ IS_GEN(e, 11)
)
v2: use IS_GEN rather than GT_GEN and compare to info.gen rather than
using the bitmask
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212181044.15886-2-lucas.demarchi@intel.com
2018-12-13 02:10:43 +08:00
if ( IS_GEN ( dev_priv , 9 ) & & ! IS_GEMINILAKE ( dev_priv ) )
2017-08-11 02:30:33 +08:00
params - > gen9_wa_cfb_stride = DIV_ROUND_UP ( cache - > plane . src_w ,
32 * fbc - > threshold ) * 8 ;
2015-12-24 04:28:11 +08:00
}
2016-06-14 20:24:20 +08:00
void intel_fbc_pre_update ( struct intel_crtc * crtc ,
struct intel_crtc_state * crtc_state ,
struct intel_plane_state * plane_state )
2016-01-19 21:35:35 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2018-01-26 06:41:22 +08:00
const char * reason = " update pending " ;
2016-01-19 21:35:35 +08:00
2016-01-19 21:35:44 +08:00
if ( ! fbc_supported ( dev_priv ) )
return ;
mutex_lock ( & fbc - > lock ) ;
2016-01-19 21:35:35 +08:00
2016-06-14 20:24:20 +08:00
if ( ! multiple_pipes_ok ( crtc , plane_state ) ) {
2018-01-26 06:41:22 +08:00
reason = " more than one pipe active " ;
2016-01-19 21:35:43 +08:00
goto deactivate ;
2014-12-09 00:09:10 +08:00
}
2016-01-12 03:44:36 +08:00
if ( ! fbc - > enabled | | fbc - > crtc ! = crtc )
2016-01-19 21:35:44 +08:00
goto unlock ;
2016-01-19 21:35:35 +08:00
2016-06-14 20:24:20 +08:00
intel_fbc_update_state_cache ( crtc , crtc_state , plane_state ) ;
2018-06-26 00:37:57 +08:00
fbc - > flip_pending = true ;
2016-01-19 21:35:42 +08:00
2016-01-19 21:35:43 +08:00
deactivate :
2018-01-26 06:41:22 +08:00
intel_fbc_deactivate ( dev_priv , reason ) ;
2016-01-19 21:35:44 +08:00
unlock :
mutex_unlock ( & fbc - > lock ) ;
2016-01-19 21:35:43 +08:00
}
2018-03-05 20:36:08 +08:00
/**
* __intel_fbc_disable - disable FBC
* @ dev_priv : i915 device instance
*
* This is the low level function that actually disables FBC . Callers should
* grab the FBC lock .
*/
static void __intel_fbc_disable ( struct drm_i915_private * dev_priv )
{
struct intel_fbc * fbc = & dev_priv - > fbc ;
struct intel_crtc * crtc = fbc - > crtc ;
WARN_ON ( ! mutex_is_locked ( & fbc - > lock ) ) ;
WARN_ON ( ! fbc - > enabled ) ;
WARN_ON ( fbc - > active ) ;
DRM_DEBUG_KMS ( " Disabling FBC on pipe %c \n " , pipe_name ( crtc - > pipe ) ) ;
__intel_fbc_cleanup_cfb ( dev_priv ) ;
fbc - > enabled = false ;
fbc - > crtc = NULL ;
}
2016-01-19 21:35:44 +08:00
static void __intel_fbc_post_update ( struct intel_crtc * crtc )
2016-01-19 21:35:43 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-19 21:35:43 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
WARN_ON ( ! mutex_is_locked ( & fbc - > lock ) ) ;
if ( ! fbc - > enabled | | fbc - > crtc ! = crtc )
return ;
2018-06-26 00:37:57 +08:00
fbc - > flip_pending = false ;
WARN_ON ( fbc - > active ) ;
2018-03-05 20:36:08 +08:00
if ( ! i915_modparams . enable_fbc ) {
intel_fbc_deactivate ( dev_priv , " disabled at runtime per module param " ) ;
__intel_fbc_disable ( dev_priv ) ;
return ;
}
2016-01-12 03:44:36 +08:00
intel_fbc_get_reg_params ( crtc , & fbc - > params ) ;
2015-12-24 04:28:11 +08:00
2018-06-26 00:37:57 +08:00
if ( ! intel_fbc_can_activate ( crtc ) )
2014-12-09 00:09:10 +08:00
return ;
2018-06-26 00:37:57 +08:00
if ( ! fbc - > busy_bits ) {
intel_fbc_deactivate ( dev_priv , " FBC enabled (active or scheduled) " ) ;
2018-06-26 00:37:58 +08:00
intel_fbc_hw_activate ( dev_priv ) ;
2018-06-26 00:37:57 +08:00
} else
intel_fbc_deactivate ( dev_priv , " frontbuffer write " ) ;
2015-07-03 06:25:10 +08:00
}
2016-01-19 21:35:44 +08:00
void intel_fbc_post_update ( struct intel_crtc * crtc )
2015-07-03 06:25:10 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-10-14 06:13:25 +08:00
2015-09-23 23:52:27 +08:00
if ( ! fbc_supported ( dev_priv ) )
2015-07-04 02:40:54 +08:00
return ;
2016-01-12 03:44:36 +08:00
mutex_lock ( & fbc - > lock ) ;
2016-01-19 21:35:44 +08:00
__intel_fbc_post_update ( crtc ) ;
2016-01-12 03:44:36 +08:00
mutex_unlock ( & fbc - > lock ) ;
2014-12-09 00:09:10 +08:00
}
2016-01-19 21:35:40 +08:00
static unsigned int intel_fbc_get_frontbuffer_bit ( struct intel_fbc * fbc )
{
if ( fbc - > enabled )
return to_intel_plane ( fbc - > crtc - > base . primary ) - > frontbuffer_bit ;
else
return fbc - > possible_framebuffer_bits ;
}
2015-02-14 03:23:46 +08:00
void intel_fbc_invalidate ( struct drm_i915_private * dev_priv ,
unsigned int frontbuffer_bits ,
enum fb_op_origin origin )
{
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-02-14 03:23:46 +08:00
2015-09-23 23:52:27 +08:00
if ( ! fbc_supported ( dev_priv ) )
2015-07-04 02:40:54 +08:00
return ;
2016-01-19 21:35:39 +08:00
if ( origin = = ORIGIN_GTT | | origin = = ORIGIN_FLIP )
2015-02-14 03:23:46 +08:00
return ;
2016-01-12 03:44:36 +08:00
mutex_lock ( & fbc - > lock ) ;
2015-07-03 06:25:10 +08:00
2016-01-19 21:35:40 +08:00
fbc - > busy_bits | = intel_fbc_get_frontbuffer_bit ( fbc ) & frontbuffer_bits ;
2015-02-14 03:23:46 +08:00
2016-01-19 21:35:53 +08:00
if ( fbc - > enabled & & fbc - > busy_bits )
2018-01-26 06:41:22 +08:00
intel_fbc_deactivate ( dev_priv , " frontbuffer write " ) ;
2015-07-03 06:25:10 +08:00
2016-01-12 03:44:36 +08:00
mutex_unlock ( & fbc - > lock ) ;
2015-02-14 03:23:46 +08:00
}
void intel_fbc_flush ( struct drm_i915_private * dev_priv ,
2015-07-15 03:29:10 +08:00
unsigned int frontbuffer_bits , enum fb_op_origin origin )
2015-02-14 03:23:46 +08:00
{
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-09-23 23:52:27 +08:00
if ( ! fbc_supported ( dev_priv ) )
2015-07-04 02:40:54 +08:00
return ;
2016-01-12 03:44:36 +08:00
mutex_lock ( & fbc - > lock ) ;
2015-02-14 03:23:46 +08:00
2016-01-12 03:44:36 +08:00
fbc - > busy_bits & = ~ frontbuffer_bits ;
2015-02-14 03:23:46 +08:00
2016-04-05 05:17:15 +08:00
if ( origin = = ORIGIN_GTT | | origin = = ORIGIN_FLIP )
goto out ;
2016-01-19 21:35:40 +08:00
if ( ! fbc - > busy_bits & & fbc - > enabled & &
( frontbuffer_bits & intel_fbc_get_frontbuffer_bit ( fbc ) ) ) {
2016-01-19 21:35:39 +08:00
if ( fbc - > active )
2015-11-12 00:46:22 +08:00
intel_fbc_recompress ( dev_priv ) ;
2018-06-26 00:37:57 +08:00
else if ( ! fbc - > flip_pending )
2016-01-19 21:35:44 +08:00
__intel_fbc_post_update ( fbc - > crtc ) ;
2015-07-15 03:29:10 +08:00
}
2015-07-03 06:25:10 +08:00
2016-04-05 05:17:15 +08:00
out :
2016-01-12 03:44:36 +08:00
mutex_unlock ( & fbc - > lock ) ;
2015-02-14 03:23:46 +08:00
}
2016-01-19 21:35:50 +08:00
/**
* intel_fbc_choose_crtc - select a CRTC to enable FBC on
* @ dev_priv : i915 device instance
* @ state : the atomic state structure
*
* This function looks at the proposed state for CRTCs and planes , then chooses
* which pipe is going to have FBC by setting intel_crtc_state - > enable_fbc to
* true .
*
* Later , intel_fbc_enable is going to look for state - > enable_fbc and then maybe
* enable FBC for the chosen CRTC . If it does , it will set dev_priv - > fbc . crtc .
*/
void intel_fbc_choose_crtc ( struct drm_i915_private * dev_priv ,
2017-11-18 03:19:14 +08:00
struct intel_atomic_state * state )
2016-01-19 21:35:50 +08:00
{
struct intel_fbc * fbc = & dev_priv - > fbc ;
2017-11-18 03:19:14 +08:00
struct intel_plane * plane ;
struct intel_plane_state * plane_state ;
2016-11-12 00:57:39 +08:00
bool crtc_chosen = false ;
2016-11-12 00:57:36 +08:00
int i ;
2016-01-19 21:35:50 +08:00
mutex_lock ( & fbc - > lock ) ;
2016-11-12 00:57:39 +08:00
/* Does this atomic commit involve the CRTC currently tied to FBC? */
if ( fbc - > crtc & &
2017-11-18 03:19:14 +08:00
! intel_atomic_get_new_crtc_state ( state , fbc - > crtc ) )
2016-01-19 21:35:50 +08:00
goto out ;
2016-11-12 00:57:37 +08:00
if ( ! intel_fbc_can_enable ( dev_priv ) )
goto out ;
2016-01-19 21:35:50 +08:00
/* Simply choose the first CRTC that is compatible and has a visible
* plane . We could go for fancier schemes such as checking the plane
* size , but this would just affect the few platforms that don ' t tie FBC
* to pipe or plane A . */
2017-11-18 03:19:14 +08:00
for_each_new_intel_plane_in_state ( state , plane , plane_state , i ) {
struct intel_crtc_state * crtc_state ;
struct intel_crtc * crtc = to_intel_crtc ( plane_state - > base . crtc ) ;
2016-01-19 21:35:50 +08:00
2018-02-22 01:31:01 +08:00
if ( ! plane - > has_fbc )
2016-01-19 21:35:50 +08:00
continue ;
2018-02-22 01:31:01 +08:00
if ( ! plane_state - > base . visible )
2016-11-12 00:57:35 +08:00
continue ;
2017-11-18 03:19:14 +08:00
crtc_state = intel_atomic_get_new_crtc_state ( state , crtc ) ;
2016-01-19 21:35:50 +08:00
2017-11-18 03:19:14 +08:00
crtc_state - > enable_fbc = true ;
2016-11-12 00:57:38 +08:00
crtc_chosen = true ;
2016-11-12 00:57:36 +08:00
break ;
2016-01-19 21:35:50 +08:00
}
2016-11-12 00:57:38 +08:00
if ( ! crtc_chosen )
fbc - > no_fbc_reason = " no suitable CRTC for FBC " ;
2016-01-19 21:35:50 +08:00
out :
mutex_unlock ( & fbc - > lock ) ;
}
2015-10-15 21:44:46 +08:00
/**
* intel_fbc_enable : tries to enable FBC on the CRTC
* @ crtc : the CRTC
2016-07-16 03:48:07 +08:00
* @ crtc_state : corresponding & drm_crtc_state for @ crtc
* @ plane_state : corresponding & drm_plane_state for the primary plane of @ crtc
2015-10-15 21:44:46 +08:00
*
2016-01-19 21:35:50 +08:00
* This function checks if the given CRTC was chosen for FBC , then enables it if
2016-01-19 21:35:52 +08:00
* possible . Notice that it doesn ' t activate FBC . It is valid to call
* intel_fbc_enable multiple times for the same pipe without an
* intel_fbc_disable in the middle , as long as it is deactivated .
2015-10-15 21:44:46 +08:00
*/
2016-06-14 20:24:20 +08:00
void intel_fbc_enable ( struct intel_crtc * crtc ,
struct intel_crtc_state * crtc_state ,
struct intel_plane_state * plane_state )
2015-10-15 21:44:46 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-10-15 21:44:46 +08:00
if ( ! fbc_supported ( dev_priv ) )
return ;
2016-01-12 03:44:36 +08:00
mutex_lock ( & fbc - > lock ) ;
2015-10-15 21:44:46 +08:00
2016-01-12 03:44:36 +08:00
if ( fbc - > enabled ) {
2016-01-19 21:35:52 +08:00
WARN_ON ( fbc - > crtc = = NULL ) ;
if ( fbc - > crtc = = crtc ) {
2016-06-14 20:24:20 +08:00
WARN_ON ( ! crtc_state - > enable_fbc ) ;
2016-01-19 21:35:52 +08:00
WARN_ON ( fbc - > active ) ;
}
2015-10-15 21:44:46 +08:00
goto out ;
}
2016-06-14 20:24:20 +08:00
if ( ! crtc_state - > enable_fbc )
2016-01-19 21:35:50 +08:00
goto out ;
2016-01-12 03:44:36 +08:00
WARN_ON ( fbc - > active ) ;
WARN_ON ( fbc - > crtc ! = NULL ) ;
2015-10-15 21:44:46 +08:00
2016-06-14 20:24:20 +08:00
intel_fbc_update_state_cache ( crtc , crtc_state , plane_state ) ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
if ( intel_fbc_alloc_cfb ( crtc ) ) {
drm/i915/fbc: don't print no_fbc_reason to dmesg
Our dmesg messages started being misleading after we converted to the
enable+activate model: we always print "Disabling FBC", even when
we're just deactivating it. So, for example, when I boot my machine
and do "dmesg | grep -i fbc", I see:
[drm:intel_fbc_enable] Enabling FBC on pipe A
[drm:set_no_fbc_reason] Disabling FBC: framebuffer not tiled or fenced
but then, if I read the debugfs file, I will see:
$ sudo cat i915_fbc_status
FBC enabled
Compressing: yes
so we can conclude that dmesg is misleading, since FBC is actually
enabled. What happened is that we deactivated FBC due to fbcon not
being tiled, but when we silently reactivated it when the display
manager started. We don't print activation messages since there may be
way too many of these operations per second during normal desktop
usage.
One possible solution would be to change set_no_fbc_reason to
correctly differentiate between disable and deactivation, but we
removed support from printing activation/deactivation messages in the
past because they were too frequent. So instead of doing this, let's
just not print anything on dmesg, and leave the debugfs file if the
user needs to investigate something. We already print when we enable
and disable FBC anyway on a given pipe, so this should already help
triaging bugs.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453210558-7875-22-git-send-email-paulo.r.zanoni@intel.com
2016-01-19 21:35:54 +08:00
fbc - > no_fbc_reason = " not enough stolen memory " ;
drm/i915: alloc/free the FBC CFB during enable/disable
One of the problems with the current code is that it frees the CFB and
releases its drm_mm node as soon as we flip FBC's enable bit. This is
bad because after we disable FBC the hardware may still use the CFB
for the rest of the frame, so in theory we should only release the
drm_mm node one frame after we disable FBC. Otherwise, a stolen memory
allocation done right after an FBC disable may result in either
corrupted memory for the new owner of that memory region or corrupted
screen/underruns in case the new owner changes it while the hardware
is still reading it. This case is not exactly easy to reproduce since
we currently don't do a lot of stolen memory allocations, but I see
patches on the mailing list trying to expose stolen memory to user
space, so races will be possible.
I thought about three different approaches to solve this, and they all
have downsides.
The first approach would be to simply use multiple drm_mm nodes and
freeing the unused ones only after a frame has passed. The problem
with this approach is that since stolen memory is rather small,
there's a risk we just won't be able to allocate a new CFB from stolen
if the previous one was not freed yet. This could happen in case we
quickly disable FBC from pipe A and decide to enable it on pipe B, or
just if we change pipe A's fb stride while FBC is enabled.
The second approach would be similar to the first one, but maintaining
a single drm_mm node and keeping track of when it can be reused. This
would remove the disadvantage of not having enough space for two
nodes, but would create the new problem where we may not be able to
enable FBC at the point intel_fbc_update() is called, so we would have
to add more code to retry updating FBC after the time has passed. And
that can quickly get too complex since we can get invalidate, flush,
disable and other calls in the middle of the wait.
Both solutions above - and also the current code - have the problem
that we unnecessarily free+realloc FBC during invalidate+flush
operations even if the CFB size doesn't change.
The third option would be to move the allocation/deallocation to
enable/disable. This makes sure that the pipe is always disabled when
we allocate/deallocate the CFB, so there's no risk that the FBC
hardware may read or write to the memory right after it is freed from
drm_mm. The downside is that it is possible for user space to change
the buffer stride without triggering a disable/enable - only
deactivate/activate -, so we'll have to handle this case somehow - see
igt's kms_frontbuffer_tracking test, fbc-stridechange subtest. It
could be possible to implement a way to free+alloc the CFB during said
stride change, but it would involve a lot of book-keeping - exactly as
mentioned above - just for on case, so for now I'll keep it simple and
just deactivate FBC. Besides, we may not even need to disable FBC
since we do CFB over-allocation.
Note from Chris: "Starting a fullscreen client that covers a single
monitor in a multi-monitor setup will trigger a change in stride on
one of the CRTCs (the monitors will be flipped independently).". It
shouldn't be a huge problem if we lose FBC on multi-monitor setups
since these setups already have problems reaching deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/
2015-10-16 01:19:21 +08:00
goto out ;
}
2015-10-15 21:44:46 +08:00
DRM_DEBUG_KMS ( " Enabling FBC on pipe %c \n " , pipe_name ( crtc - > pipe ) ) ;
2016-01-12 03:44:36 +08:00
fbc - > no_fbc_reason = " FBC enabled but not active yet \n " ;
2015-10-15 21:44:46 +08:00
2016-01-12 03:44:36 +08:00
fbc - > enabled = true ;
fbc - > crtc = crtc ;
2015-10-15 21:44:46 +08:00
out :
2016-01-12 03:44:36 +08:00
mutex_unlock ( & fbc - > lock ) ;
2015-10-15 21:44:46 +08:00
}
/**
2016-01-19 21:35:46 +08:00
* intel_fbc_disable - disable FBC if it ' s associated with crtc
2015-10-15 21:44:46 +08:00
* @ crtc : the CRTC
*
* This function disables FBC if it ' s associated with the provided CRTC .
*/
2016-01-19 21:35:46 +08:00
void intel_fbc_disable ( struct intel_crtc * crtc )
2015-10-15 21:44:46 +08:00
{
2016-07-04 18:34:36 +08:00
struct drm_i915_private * dev_priv = to_i915 ( crtc - > base . dev ) ;
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-10-15 21:44:46 +08:00
if ( ! fbc_supported ( dev_priv ) )
return ;
2016-01-12 03:44:36 +08:00
mutex_lock ( & fbc - > lock ) ;
2016-07-05 17:28:34 +08:00
if ( fbc - > crtc = = crtc )
2015-10-15 21:44:46 +08:00
__intel_fbc_disable ( dev_priv ) ;
2016-01-12 03:44:36 +08:00
mutex_unlock ( & fbc - > lock ) ;
2015-10-15 21:44:46 +08:00
}
/**
2016-01-19 21:35:46 +08:00
* intel_fbc_global_disable - globally disable FBC
2015-10-15 21:44:46 +08:00
* @ dev_priv : i915 device instance
*
* This function disables FBC regardless of which CRTC is associated with it .
*/
2016-01-19 21:35:46 +08:00
void intel_fbc_global_disable ( struct drm_i915_private * dev_priv )
2015-10-15 21:44:46 +08:00
{
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-10-15 21:44:46 +08:00
if ( ! fbc_supported ( dev_priv ) )
return ;
2016-01-12 03:44:36 +08:00
mutex_lock ( & fbc - > lock ) ;
2018-03-05 20:36:08 +08:00
if ( fbc - > enabled ) {
WARN_ON ( fbc - > crtc - > active ) ;
2015-10-15 21:44:46 +08:00
__intel_fbc_disable ( dev_priv ) ;
2018-03-05 20:36:08 +08:00
}
2016-01-12 03:44:36 +08:00
mutex_unlock ( & fbc - > lock ) ;
2015-10-15 21:44:46 +08:00
}
2016-09-13 21:38:57 +08:00
static void intel_fbc_underrun_work_fn ( struct work_struct * work )
{
struct drm_i915_private * dev_priv =
container_of ( work , struct drm_i915_private , fbc . underrun_work ) ;
struct intel_fbc * fbc = & dev_priv - > fbc ;
mutex_lock ( & fbc - > lock ) ;
/* Maybe we were scheduled twice. */
2017-08-11 15:23:27 +08:00
if ( fbc - > underrun_detected | | ! fbc - > enabled )
2016-09-13 21:38:57 +08:00
goto out ;
DRM_DEBUG_KMS ( " Disabling FBC due to FIFO underrun. \n " ) ;
fbc - > underrun_detected = true ;
2018-01-26 06:41:22 +08:00
intel_fbc_deactivate ( dev_priv , " FIFO underrun " ) ;
2016-09-13 21:38:57 +08:00
out :
mutex_unlock ( & fbc - > lock ) ;
}
2018-03-28 18:05:26 +08:00
/*
* intel_fbc_reset_underrun - reset FBC fifo underrun status .
* @ dev_priv : i915 device instance
*
* See intel_fbc_handle_fifo_underrun_irq ( ) . For automated testing we
* want to re - enable FBC after an underrun to increase test coverage .
*/
int intel_fbc_reset_underrun ( struct drm_i915_private * dev_priv )
{
int ret ;
cancel_work_sync ( & dev_priv - > fbc . underrun_work ) ;
ret = mutex_lock_interruptible ( & dev_priv - > fbc . lock ) ;
if ( ret )
return ret ;
if ( dev_priv - > fbc . underrun_detected ) {
DRM_DEBUG_KMS ( " Re-allowing FBC after fifo underrun \n " ) ;
dev_priv - > fbc . no_fbc_reason = " FIFO underrun cleared " ;
}
dev_priv - > fbc . underrun_detected = false ;
mutex_unlock ( & dev_priv - > fbc . lock ) ;
return 0 ;
}
2016-09-13 21:38:57 +08:00
/**
* intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
* @ dev_priv : i915 device instance
*
* Without FBC , most underruns are harmless and don ' t really cause too many
* problems , except for an annoying message on dmesg . With FBC , underruns can
* become black screens or even worse , especially when paired with bad
* watermarks . So in order for us to be on the safe side , completely disable FBC
* in case we ever detect a FIFO underrun on any pipe . An underrun on any pipe
* already suggests that watermarks may be bad , so try to be as safe as
* possible .
*
* This function is called from the IRQ handler .
*/
void intel_fbc_handle_fifo_underrun_irq ( struct drm_i915_private * dev_priv )
{
struct intel_fbc * fbc = & dev_priv - > fbc ;
if ( ! fbc_supported ( dev_priv ) )
return ;
/* There's no guarantee that underrun_detected won't be set to true
* right after this check and before the work is scheduled , but that ' s
* not a problem since we ' ll check it again under the work function
* while FBC is locked . This check here is just to prevent us from
* unnecessarily scheduling the work , and it relies on the fact that we
* never switch underrun_detect back to false after it ' s true . */
if ( READ_ONCE ( fbc - > underrun_detected ) )
return ;
schedule_work ( & fbc - > underrun_work ) ;
}
2016-01-19 21:35:48 +08:00
/**
* intel_fbc_init_pipe_state - initialize FBC ' s CRTC visibility tracking
* @ dev_priv : i915 device instance
*
* The FBC code needs to track CRTC visibility since the older platforms can ' t
* have FBC enabled while multiple pipes are used . This function does the
* initial setup at driver load to make sure FBC is matching the real hardware .
*/
void intel_fbc_init_pipe_state ( struct drm_i915_private * dev_priv )
{
struct intel_crtc * crtc ;
/* Don't even bother tracking anything if we don't need. */
if ( ! no_fbc_on_multiple_pipes ( dev_priv ) )
return ;
2016-07-05 17:40:23 +08:00
for_each_intel_crtc ( & dev_priv - > drm , crtc )
2016-11-01 04:37:02 +08:00
if ( intel_crtc_active ( crtc ) & &
2017-01-12 17:43:45 +08:00
crtc - > base . primary - > state - > visible )
2016-01-19 21:35:48 +08:00
dev_priv - > fbc . visible_pipes_mask | = ( 1 < < crtc - > pipe ) ;
}
2016-04-14 03:01:09 +08:00
/*
* The DDX driver changes its behavior depending on the value it reads from
* i915 . enable_fbc , so sanitize it by translating the default value into either
* 0 or 1 in order to allow it to know what ' s going on .
*
* Notice that this is done at driver initialization and we still allow user
* space to change the value during runtime without sanitizing it again . IGT
* relies on being able to change i915 . enable_fbc at runtime .
*/
static int intel_sanitize_fbc_option ( struct drm_i915_private * dev_priv )
{
2017-09-20 03:38:44 +08:00
if ( i915_modparams . enable_fbc > = 0 )
return ! ! i915_modparams . enable_fbc ;
2016-04-14 03:01:09 +08:00
2016-08-04 15:43:53 +08:00
if ( ! HAS_FBC ( dev_priv ) )
return 0 ;
2016-12-23 20:23:58 +08:00
if ( IS_BROADWELL ( dev_priv ) | | INTEL_GEN ( dev_priv ) > = 9 )
2016-04-14 03:01:09 +08:00
return 1 ;
return 0 ;
}
2016-08-04 15:43:53 +08:00
static bool need_fbc_vtd_wa ( struct drm_i915_private * dev_priv )
{
/* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
2017-05-25 20:16:12 +08:00
if ( intel_vtd_active ( ) & &
2016-08-04 15:43:53 +08:00
( IS_SKYLAKE ( dev_priv ) | | IS_BROXTON ( dev_priv ) ) ) {
DRM_INFO ( " Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled \n " ) ;
return true ;
}
return false ;
}
2014-12-08 22:46:31 +08:00
/**
* intel_fbc_init - Initialize FBC
* @ dev_priv : the i915 device
*
* This function might be called during PM init process .
*/
2014-12-09 00:09:10 +08:00
void intel_fbc_init ( struct drm_i915_private * dev_priv )
{
2016-01-12 03:44:36 +08:00
struct intel_fbc * fbc = & dev_priv - > fbc ;
2015-02-14 03:23:46 +08:00
2016-09-13 21:38:57 +08:00
INIT_WORK ( & fbc - > underrun_work , intel_fbc_underrun_work_fn ) ;
2016-01-12 03:44:36 +08:00
mutex_init ( & fbc - > lock ) ;
fbc - > enabled = false ;
fbc - > active = false ;
2015-07-03 06:25:10 +08:00
2016-08-04 15:43:53 +08:00
if ( need_fbc_vtd_wa ( dev_priv ) )
2018-12-01 07:20:48 +08:00
mkwrite_device_info ( dev_priv ) - > display . has_fbc = false ;
2016-08-04 15:43:53 +08:00
2017-09-20 03:38:44 +08:00
i915_modparams . enable_fbc = intel_sanitize_fbc_option ( dev_priv ) ;
DRM_DEBUG_KMS ( " Sanitized enable_fbc value: %d \n " ,
i915_modparams . enable_fbc ) ;
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if ( ! HAS_FBC ( dev_priv ) ) {
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fbc - > no_fbc_reason = " unsupported by this chipset " ;
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return ;
}
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/* This value was pulled out of someone's hat */
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if ( INTEL_GEN ( dev_priv ) < = 4 & & ! IS_GM45 ( dev_priv ) )
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I915_WRITE ( FBC_CONTROL , 500 < < FBC_CTL_INTERVAL_SHIFT ) ;
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/* We still don't have any sort of hardware state readout for FBC, so
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* deactivate it in case the BIOS activated it to make sure software
* matches the hardware state . */
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if ( intel_fbc_hw_is_active ( dev_priv ) )
intel_fbc_hw_deactivate ( dev_priv ) ;
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}