2013-04-10 03:58:38 +08:00
|
|
|
asflags-y += -march=armv7-a
|
|
|
|
|
2010-01-22 08:53:02 +08:00
|
|
|
obj-y += io.o
|
2011-05-02 06:26:51 +08:00
|
|
|
obj-y += irq.o
|
2012-10-31 17:41:17 +08:00
|
|
|
obj-y += pm.o
|
2013-01-04 17:32:22 +08:00
|
|
|
obj-y += reset.o
|
|
|
|
obj-y += reset-handler.o
|
2013-01-25 14:38:32 +08:00
|
|
|
obj-y += sleep.o
|
2013-02-14 01:15:50 +08:00
|
|
|
obj-y += tegra.o
|
2012-02-24 00:21:52 +08:00
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|
|
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
2012-10-08 08:23:57 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
|
2013-08-12 17:40:05 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
|
2012-10-31 17:41:15 +08:00
|
|
|
ifeq ($(CONFIG_CPU_IDLE),y)
|
|
|
|
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
|
|
|
|
endif
|
|
|
|
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
|
ARM: tegra: add LP1 suspend support for Tegra30
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 17:40:04 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
|
2012-10-31 17:41:15 +08:00
|
|
|
ifeq ($(CONFIG_CPU_IDLE),y)
|
|
|
|
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
|
|
|
|
endif
|
2015-05-20 00:06:44 +08:00
|
|
|
obj-$(CONFIG_SMP) += platsmp.o
|
2010-02-22 09:46:23 +08:00
|
|
|
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
2010-02-11 09:13:07 +08:00
|
|
|
|
2013-05-20 18:39:29 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
|
ARM: tegra: add LP1 suspend support for Tegra114
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored. Then jumping to "tegra_resume" that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan <byan@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 17:40:06 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
|
2013-01-21 17:49:06 +08:00
|
|
|
ifeq ($(CONFIG_CPU_IDLE),y)
|
|
|
|
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
|
|
|
|
endif
|
2013-10-11 17:57:30 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o
|
2013-10-11 17:58:38 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o
|
2013-10-11 17:57:32 +08:00
|
|
|
ifeq ($(CONFIG_CPU_IDLE),y)
|
|
|
|
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o
|
|
|
|
endif
|
2012-05-22 05:07:19 +08:00
|
|
|
|
2012-08-04 05:09:04 +08:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
|