2005-06-24 13:01:20 +08:00
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/*
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* arch/xtensa/lib/hal/memcopy.S -- Core HAL library functions
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* xthal_memcpy and xthal_bcopy
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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2012-10-16 12:41:19 +08:00
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* Copyright (C) 2002 - 2012 Tensilica Inc.
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2005-06-24 13:01:20 +08:00
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*/
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2017-12-10 13:22:37 +08:00
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#include <linux/linkage.h>
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2017-12-10 13:21:35 +08:00
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#include <asm/asmmacro.h>
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2019-01-02 11:41:55 +08:00
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#include <asm/core.h>
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2005-06-24 13:01:20 +08:00
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/*
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* void *memcpy(void *dst, const void *src, size_t len);
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*
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* This function is intended to do the same thing as the standard
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2012-10-16 12:41:19 +08:00
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* library function memcpy() for most cases.
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2005-06-24 13:01:20 +08:00
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* However, where the source and/or destination references
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* an instruction RAM or ROM or a data RAM or ROM, that
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* source and/or destination will always be accessed with
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* 32-bit load and store instructions (as required for these
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* types of devices).
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*
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* !!!!!!! XTFIXME:
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* !!!!!!! Handling of IRAM/IROM has not yet
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* !!!!!!! been implemented.
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*
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* The (general case) algorithm is as follows:
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* If destination is unaligned, align it by conditionally
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* copying 1 and 2 bytes.
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* If source is aligned,
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* do 16 bytes with a loop, and then finish up with
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* 8, 4, 2, and 1 byte copies conditional on the length;
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* else (if source is unaligned),
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* do the same, but use SRC to align the source data.
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* This code tries to use fall-through branches for the common
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* case of aligned source and destination and multiple
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* of 4 (or 8) length.
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*
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* Register use:
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* a0/ return address
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* a1/ stack pointer
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* a2/ return value
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* a3/ src
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* a4/ length
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* a5/ dst
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* a6/ tmp
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* a7/ tmp
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* a8/ tmp
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* a9/ tmp
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* a10/ tmp
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* a11/ tmp
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*/
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.text
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/*
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* Byte by byte copy
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*/
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.align 4
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.byte 0 # 1 mod 4 alignment for LOOPNEZ
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# (0 mod 4 alignment for LBEG)
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.Lbytecopy:
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#if XCHAL_HAVE_LOOPS
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loopnez a4, .Lbytecopydone
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#else /* !XCHAL_HAVE_LOOPS */
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beqz a4, .Lbytecopydone
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add a7, a3, a4 # a7 = end address for source
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lnextbyte:
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l8ui a6, a3, 0
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addi a3, a3, 1
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s8i a6, a5, 0
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addi a5, a5, 1
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#if !XCHAL_HAVE_LOOPS
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2012-10-16 12:41:19 +08:00
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bne a3, a7, .Lnextbyte # continue loop if $a3:src != $a7:src_end
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2005-06-24 13:01:20 +08:00
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#endif /* !XCHAL_HAVE_LOOPS */
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.Lbytecopydone:
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2019-05-13 11:28:25 +08:00
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abi_ret_default
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2005-06-24 13:01:20 +08:00
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/*
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* Destination is unaligned
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*/
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.align 4
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.Ldst1mod2: # dst is only byte aligned
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_bltui a4, 7, .Lbytecopy # do short copies byte by byte
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# copy 1 byte
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l8ui a6, a3, 0
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addi a3, a3, 1
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addi a4, a4, -1
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s8i a6, a5, 0
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addi a5, a5, 1
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_bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then
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# return to main algorithm
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.Ldst2mod4: # dst 16-bit aligned
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# copy 2 bytes
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_bltui a4, 6, .Lbytecopy # do short copies byte by byte
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l8ui a6, a3, 0
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l8ui a7, a3, 1
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addi a3, a3, 2
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addi a4, a4, -2
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s8i a6, a5, 0
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s8i a7, a5, 1
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addi a5, a5, 2
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j .Ldstaligned # dst is now aligned, return to main algorithm
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2017-12-04 05:28:52 +08:00
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ENTRY(__memcpy)
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WEAK(memcpy)
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2005-06-24 13:01:20 +08:00
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2019-05-13 11:28:25 +08:00
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abi_entry_default
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2005-06-24 13:01:20 +08:00
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# a2/ dst, a3/ src, a4/ len
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mov a5, a2 # copy dst so that a2 is return value
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.Lcommon:
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_bbsi.l a2, 0, .Ldst1mod2 # if dst is 1 mod 2
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_bbsi.l a2, 1, .Ldst2mod4 # if dst is 2 mod 4
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.Ldstaligned: # return here from .Ldst?mod? once dst is aligned
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srli a7, a4, 4 # number of loop iterations with 16B
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# per iteration
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movi a8, 3 # if source is not aligned,
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_bany a3, a8, .Lsrcunaligned # then use shifting copy
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/*
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* Destination and source are word-aligned, use word copy.
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*/
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# copy 16 bytes per iteration for word-aligned dst and word-aligned src
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#if XCHAL_HAVE_LOOPS
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loopnez a7, .Loop1done
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#else /* !XCHAL_HAVE_LOOPS */
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beqz a7, .Loop1done
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slli a8, a7, 4
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add a8, a8, a3 # a8 = end of last 16B source chunk
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop1:
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l32i a6, a3, 0
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l32i a7, a3, 4
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s32i a6, a5, 0
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l32i a6, a3, 8
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s32i a7, a5, 4
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l32i a7, a3, 12
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s32i a6, a5, 8
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addi a3, a3, 16
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s32i a7, a5, 12
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addi a5, a5, 16
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#if !XCHAL_HAVE_LOOPS
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2012-10-16 12:41:19 +08:00
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bne a3, a8, .Loop1 # continue loop if a3:src != a8:src_end
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2005-06-24 13:01:20 +08:00
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop1done:
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bbci.l a4, 3, .L2
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# copy 8 bytes
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l32i a6, a3, 0
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l32i a7, a3, 4
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addi a3, a3, 8
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s32i a6, a5, 0
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s32i a7, a5, 4
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addi a5, a5, 8
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.L2:
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bbsi.l a4, 2, .L3
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bbsi.l a4, 1, .L4
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bbsi.l a4, 0, .L5
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2019-05-13 11:28:25 +08:00
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abi_ret_default
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2005-06-24 13:01:20 +08:00
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.L3:
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# copy 4 bytes
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l32i a6, a3, 0
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addi a3, a3, 4
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s32i a6, a5, 0
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addi a5, a5, 4
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bbsi.l a4, 1, .L4
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bbsi.l a4, 0, .L5
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2019-05-13 11:28:25 +08:00
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abi_ret_default
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2005-06-24 13:01:20 +08:00
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.L4:
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# copy 2 bytes
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l16ui a6, a3, 0
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addi a3, a3, 2
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s16i a6, a5, 0
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addi a5, a5, 2
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bbsi.l a4, 0, .L5
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2019-05-13 11:28:25 +08:00
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abi_ret_default
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2005-06-24 13:01:20 +08:00
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.L5:
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# copy 1 byte
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l8ui a6, a3, 0
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s8i a6, a5, 0
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2019-05-13 11:28:25 +08:00
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abi_ret_default
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2005-06-24 13:01:20 +08:00
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/*
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* Destination is aligned, Source is unaligned
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*/
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.align 4
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.Lsrcunaligned:
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_beqz a4, .Ldone # avoid loading anything for zero-length copies
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# copy 16 bytes per iteration for word-aligned dst and unaligned src
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2017-12-10 13:21:35 +08:00
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__ssa8 a3 # set shift amount from byte offset
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2012-11-29 08:53:51 +08:00
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/* set to 1 when running on ISS (simulator) with the
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lint or ferret client, or 0 to save a few cycles */
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#define SIM_CHECKS_ALIGNMENT 1
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2005-06-24 13:01:20 +08:00
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
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and a11, a3, a8 # save unalignment offset for below
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sub a3, a3, a11 # align a3
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#endif
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l32i a6, a3, 0 # load first word
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#if XCHAL_HAVE_LOOPS
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loopnez a7, .Loop2done
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#else /* !XCHAL_HAVE_LOOPS */
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beqz a7, .Loop2done
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slli a10, a7, 4
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add a10, a10, a3 # a10 = end of last 16B source chunk
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop2:
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l32i a7, a3, 4
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l32i a8, a3, 8
|
2017-12-10 13:21:35 +08:00
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__src_b a6, a6, a7
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2005-06-24 13:01:20 +08:00
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s32i a6, a5, 0
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l32i a9, a3, 12
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2017-12-10 13:21:35 +08:00
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__src_b a7, a7, a8
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2005-06-24 13:01:20 +08:00
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s32i a7, a5, 4
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l32i a6, a3, 16
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2017-12-10 13:21:35 +08:00
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__src_b a8, a8, a9
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2005-06-24 13:01:20 +08:00
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s32i a8, a5, 8
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addi a3, a3, 16
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2017-12-10 13:21:35 +08:00
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__src_b a9, a9, a6
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2005-06-24 13:01:20 +08:00
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s32i a9, a5, 12
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addi a5, a5, 16
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#if !XCHAL_HAVE_LOOPS
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2012-10-16 12:41:19 +08:00
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bne a3, a10, .Loop2 # continue loop if a3:src != a10:src_end
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2005-06-24 13:01:20 +08:00
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#endif /* !XCHAL_HAVE_LOOPS */
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.Loop2done:
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bbci.l a4, 3, .L12
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# copy 8 bytes
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l32i a7, a3, 4
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l32i a8, a3, 8
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2017-12-10 13:21:35 +08:00
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__src_b a6, a6, a7
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2005-06-24 13:01:20 +08:00
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s32i a6, a5, 0
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addi a3, a3, 8
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2017-12-10 13:21:35 +08:00
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__src_b a7, a7, a8
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2005-06-24 13:01:20 +08:00
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s32i a7, a5, 4
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addi a5, a5, 8
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mov a6, a8
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.L12:
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bbci.l a4, 2, .L13
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# copy 4 bytes
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l32i a7, a3, 4
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addi a3, a3, 4
|
2017-12-10 13:21:35 +08:00
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__src_b a6, a6, a7
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2005-06-24 13:01:20 +08:00
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s32i a6, a5, 0
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addi a5, a5, 4
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mov a6, a7
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.L13:
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
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add a3, a3, a11 # readjust a3 with correct misalignment
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#endif
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bbsi.l a4, 1, .L14
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bbsi.l a4, 0, .L15
|
2019-05-13 11:28:25 +08:00
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.Ldone: abi_ret_default
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2005-06-24 13:01:20 +08:00
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.L14:
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# copy 2 bytes
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l8ui a6, a3, 0
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l8ui a7, a3, 1
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addi a3, a3, 2
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s8i a6, a5, 0
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s8i a7, a5, 1
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addi a5, a5, 2
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bbsi.l a4, 0, .L15
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2005-06-24 13:01:20 +08:00
|
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.L15:
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# copy 1 byte
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l8ui a6, a3, 0
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s8i a6, a5, 0
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
|
2017-12-04 05:28:52 +08:00
|
|
|
ENDPROC(__memcpy)
|
2012-10-16 12:41:19 +08:00
|
|
|
|
|
|
|
/*
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|
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* void bcopy(const void *src, void *dest, size_t n);
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|
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*/
|
2017-12-10 13:22:37 +08:00
|
|
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|
|
ENTRY(bcopy)
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|
2019-05-13 11:28:25 +08:00
|
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|
abi_entry_default
|
2012-10-16 12:41:19 +08:00
|
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|
# a2=src, a3=dst, a4=len
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mov a5, a3
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mov a3, a2
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mov a2, a5
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|
j .Lmovecommon # go to common code for memmove+bcopy
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|
2017-12-10 13:22:37 +08:00
|
|
|
ENDPROC(bcopy)
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|
|
|
2012-10-16 12:41:19 +08:00
|
|
|
/*
|
|
|
|
* void *memmove(void *dst, const void *src, size_t len);
|
|
|
|
*
|
|
|
|
* This function is intended to do the same thing as the standard
|
|
|
|
* library function memmove() for most cases.
|
|
|
|
* However, where the source and/or destination references
|
|
|
|
* an instruction RAM or ROM or a data RAM or ROM, that
|
|
|
|
* source and/or destination will always be accessed with
|
|
|
|
* 32-bit load and store instructions (as required for these
|
|
|
|
* types of devices).
|
|
|
|
*
|
|
|
|
* !!!!!!! XTFIXME:
|
|
|
|
* !!!!!!! Handling of IRAM/IROM has not yet
|
|
|
|
* !!!!!!! been implemented.
|
|
|
|
*
|
|
|
|
* The (general case) algorithm is as follows:
|
|
|
|
* If end of source doesn't overlap destination then use memcpy.
|
|
|
|
* Otherwise do memcpy backwards.
|
|
|
|
*
|
|
|
|
* Register use:
|
|
|
|
* a0/ return address
|
|
|
|
* a1/ stack pointer
|
|
|
|
* a2/ return value
|
|
|
|
* a3/ src
|
|
|
|
* a4/ length
|
|
|
|
* a5/ dst
|
|
|
|
* a6/ tmp
|
|
|
|
* a7/ tmp
|
|
|
|
* a8/ tmp
|
|
|
|
* a9/ tmp
|
|
|
|
* a10/ tmp
|
|
|
|
* a11/ tmp
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Byte by byte copy
|
|
|
|
*/
|
|
|
|
.align 4
|
|
|
|
.byte 0 # 1 mod 4 alignment for LOOPNEZ
|
|
|
|
# (0 mod 4 alignment for LBEG)
|
|
|
|
.Lbackbytecopy:
|
|
|
|
#if XCHAL_HAVE_LOOPS
|
|
|
|
loopnez a4, .Lbackbytecopydone
|
|
|
|
#else /* !XCHAL_HAVE_LOOPS */
|
|
|
|
beqz a4, .Lbackbytecopydone
|
|
|
|
sub a7, a3, a4 # a7 = start address for source
|
|
|
|
#endif /* !XCHAL_HAVE_LOOPS */
|
|
|
|
.Lbacknextbyte:
|
|
|
|
addi a3, a3, -1
|
|
|
|
l8ui a6, a3, 0
|
|
|
|
addi a5, a5, -1
|
|
|
|
s8i a6, a5, 0
|
|
|
|
#if !XCHAL_HAVE_LOOPS
|
|
|
|
bne a3, a7, .Lbacknextbyte # continue loop if
|
|
|
|
# $a3:src != $a7:src_start
|
|
|
|
#endif /* !XCHAL_HAVE_LOOPS */
|
|
|
|
.Lbackbytecopydone:
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Destination is unaligned
|
|
|
|
*/
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
.Lbackdst1mod2: # dst is only byte aligned
|
|
|
|
_bltui a4, 7, .Lbackbytecopy # do short copies byte by byte
|
|
|
|
|
|
|
|
# copy 1 byte
|
|
|
|
addi a3, a3, -1
|
|
|
|
l8ui a6, a3, 0
|
|
|
|
addi a5, a5, -1
|
|
|
|
s8i a6, a5, 0
|
|
|
|
addi a4, a4, -1
|
|
|
|
_bbci.l a5, 1, .Lbackdstaligned # if dst is now aligned, then
|
|
|
|
# return to main algorithm
|
|
|
|
.Lbackdst2mod4: # dst 16-bit aligned
|
|
|
|
# copy 2 bytes
|
|
|
|
_bltui a4, 6, .Lbackbytecopy # do short copies byte by byte
|
|
|
|
addi a3, a3, -2
|
|
|
|
l8ui a6, a3, 0
|
|
|
|
l8ui a7, a3, 1
|
|
|
|
addi a5, a5, -2
|
|
|
|
s8i a6, a5, 0
|
|
|
|
s8i a7, a5, 1
|
|
|
|
addi a4, a4, -2
|
|
|
|
j .Lbackdstaligned # dst is now aligned,
|
|
|
|
# return to main algorithm
|
|
|
|
|
2017-12-04 05:28:52 +08:00
|
|
|
ENTRY(__memmove)
|
|
|
|
WEAK(memmove)
|
2012-10-16 12:41:19 +08:00
|
|
|
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_entry_default
|
2012-10-16 12:41:19 +08:00
|
|
|
# a2/ dst, a3/ src, a4/ len
|
|
|
|
mov a5, a2 # copy dst so that a2 is return value
|
|
|
|
.Lmovecommon:
|
|
|
|
sub a6, a5, a3
|
|
|
|
bgeu a6, a4, .Lcommon
|
|
|
|
|
|
|
|
add a5, a5, a4
|
|
|
|
add a3, a3, a4
|
|
|
|
|
|
|
|
_bbsi.l a5, 0, .Lbackdst1mod2 # if dst is 1 mod 2
|
|
|
|
_bbsi.l a5, 1, .Lbackdst2mod4 # if dst is 2 mod 4
|
|
|
|
.Lbackdstaligned: # return here from .Lbackdst?mod? once dst is aligned
|
|
|
|
srli a7, a4, 4 # number of loop iterations with 16B
|
|
|
|
# per iteration
|
|
|
|
movi a8, 3 # if source is not aligned,
|
|
|
|
_bany a3, a8, .Lbacksrcunaligned # then use shifting copy
|
|
|
|
/*
|
|
|
|
* Destination and source are word-aligned, use word copy.
|
|
|
|
*/
|
|
|
|
# copy 16 bytes per iteration for word-aligned dst and word-aligned src
|
|
|
|
#if XCHAL_HAVE_LOOPS
|
|
|
|
loopnez a7, .backLoop1done
|
|
|
|
#else /* !XCHAL_HAVE_LOOPS */
|
|
|
|
beqz a7, .backLoop1done
|
|
|
|
slli a8, a7, 4
|
|
|
|
sub a8, a3, a8 # a8 = start of first 16B source chunk
|
|
|
|
#endif /* !XCHAL_HAVE_LOOPS */
|
|
|
|
.backLoop1:
|
|
|
|
addi a3, a3, -16
|
|
|
|
l32i a7, a3, 12
|
|
|
|
l32i a6, a3, 8
|
|
|
|
addi a5, a5, -16
|
|
|
|
s32i a7, a5, 12
|
|
|
|
l32i a7, a3, 4
|
|
|
|
s32i a6, a5, 8
|
|
|
|
l32i a6, a3, 0
|
|
|
|
s32i a7, a5, 4
|
|
|
|
s32i a6, a5, 0
|
|
|
|
#if !XCHAL_HAVE_LOOPS
|
|
|
|
bne a3, a8, .backLoop1 # continue loop if a3:src != a8:src_start
|
|
|
|
#endif /* !XCHAL_HAVE_LOOPS */
|
|
|
|
.backLoop1done:
|
|
|
|
bbci.l a4, 3, .Lback2
|
|
|
|
# copy 8 bytes
|
|
|
|
addi a3, a3, -8
|
|
|
|
l32i a6, a3, 0
|
|
|
|
l32i a7, a3, 4
|
|
|
|
addi a5, a5, -8
|
|
|
|
s32i a6, a5, 0
|
|
|
|
s32i a7, a5, 4
|
|
|
|
.Lback2:
|
|
|
|
bbsi.l a4, 2, .Lback3
|
|
|
|
bbsi.l a4, 1, .Lback4
|
|
|
|
bbsi.l a4, 0, .Lback5
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
.Lback3:
|
|
|
|
# copy 4 bytes
|
|
|
|
addi a3, a3, -4
|
|
|
|
l32i a6, a3, 0
|
|
|
|
addi a5, a5, -4
|
|
|
|
s32i a6, a5, 0
|
|
|
|
bbsi.l a4, 1, .Lback4
|
|
|
|
bbsi.l a4, 0, .Lback5
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
.Lback4:
|
|
|
|
# copy 2 bytes
|
|
|
|
addi a3, a3, -2
|
|
|
|
l16ui a6, a3, 0
|
|
|
|
addi a5, a5, -2
|
|
|
|
s16i a6, a5, 0
|
|
|
|
bbsi.l a4, 0, .Lback5
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
.Lback5:
|
|
|
|
# copy 1 byte
|
|
|
|
addi a3, a3, -1
|
|
|
|
l8ui a6, a3, 0
|
|
|
|
addi a5, a5, -1
|
|
|
|
s8i a6, a5, 0
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Destination is aligned, Source is unaligned
|
|
|
|
*/
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
.Lbacksrcunaligned:
|
|
|
|
_beqz a4, .Lbackdone # avoid loading anything for zero-length copies
|
|
|
|
# copy 16 bytes per iteration for word-aligned dst and unaligned src
|
2017-12-10 13:21:35 +08:00
|
|
|
__ssa8 a3 # set shift amount from byte offset
|
2012-10-16 12:41:19 +08:00
|
|
|
#define SIM_CHECKS_ALIGNMENT 1 /* set to 1 when running on ISS with
|
|
|
|
* the lint or ferret client, or 0
|
|
|
|
* to save a few cycles */
|
|
|
|
#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
|
|
|
|
and a11, a3, a8 # save unalignment offset for below
|
|
|
|
sub a3, a3, a11 # align a3
|
|
|
|
#endif
|
|
|
|
l32i a6, a3, 0 # load first word
|
|
|
|
#if XCHAL_HAVE_LOOPS
|
|
|
|
loopnez a7, .backLoop2done
|
|
|
|
#else /* !XCHAL_HAVE_LOOPS */
|
|
|
|
beqz a7, .backLoop2done
|
|
|
|
slli a10, a7, 4
|
|
|
|
sub a10, a3, a10 # a10 = start of first 16B source chunk
|
|
|
|
#endif /* !XCHAL_HAVE_LOOPS */
|
|
|
|
.backLoop2:
|
|
|
|
addi a3, a3, -16
|
|
|
|
l32i a7, a3, 12
|
|
|
|
l32i a8, a3, 8
|
|
|
|
addi a5, a5, -16
|
2017-12-10 13:21:35 +08:00
|
|
|
__src_b a6, a7, a6
|
2012-10-16 12:41:19 +08:00
|
|
|
s32i a6, a5, 12
|
|
|
|
l32i a9, a3, 4
|
2017-12-10 13:21:35 +08:00
|
|
|
__src_b a7, a8, a7
|
2012-10-16 12:41:19 +08:00
|
|
|
s32i a7, a5, 8
|
|
|
|
l32i a6, a3, 0
|
2017-12-10 13:21:35 +08:00
|
|
|
__src_b a8, a9, a8
|
2012-10-16 12:41:19 +08:00
|
|
|
s32i a8, a5, 4
|
2017-12-10 13:21:35 +08:00
|
|
|
__src_b a9, a6, a9
|
2012-10-16 12:41:19 +08:00
|
|
|
s32i a9, a5, 0
|
|
|
|
#if !XCHAL_HAVE_LOOPS
|
|
|
|
bne a3, a10, .backLoop2 # continue loop if a3:src != a10:src_start
|
|
|
|
#endif /* !XCHAL_HAVE_LOOPS */
|
|
|
|
.backLoop2done:
|
|
|
|
bbci.l a4, 3, .Lback12
|
|
|
|
# copy 8 bytes
|
|
|
|
addi a3, a3, -8
|
|
|
|
l32i a7, a3, 4
|
|
|
|
l32i a8, a3, 0
|
|
|
|
addi a5, a5, -8
|
2017-12-10 13:21:35 +08:00
|
|
|
__src_b a6, a7, a6
|
2012-10-16 12:41:19 +08:00
|
|
|
s32i a6, a5, 4
|
2017-12-10 13:21:35 +08:00
|
|
|
__src_b a7, a8, a7
|
2012-10-16 12:41:19 +08:00
|
|
|
s32i a7, a5, 0
|
|
|
|
mov a6, a8
|
|
|
|
.Lback12:
|
|
|
|
bbci.l a4, 2, .Lback13
|
|
|
|
# copy 4 bytes
|
|
|
|
addi a3, a3, -4
|
|
|
|
l32i a7, a3, 0
|
|
|
|
addi a5, a5, -4
|
2017-12-10 13:21:35 +08:00
|
|
|
__src_b a6, a7, a6
|
2012-10-16 12:41:19 +08:00
|
|
|
s32i a6, a5, 0
|
|
|
|
mov a6, a7
|
|
|
|
.Lback13:
|
|
|
|
#if XCHAL_UNALIGNED_LOAD_EXCEPTION || SIM_CHECKS_ALIGNMENT
|
|
|
|
add a3, a3, a11 # readjust a3 with correct misalignment
|
|
|
|
#endif
|
|
|
|
bbsi.l a4, 1, .Lback14
|
|
|
|
bbsi.l a4, 0, .Lback15
|
|
|
|
.Lbackdone:
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
.Lback14:
|
|
|
|
# copy 2 bytes
|
|
|
|
addi a3, a3, -2
|
|
|
|
l8ui a6, a3, 0
|
|
|
|
l8ui a7, a3, 1
|
|
|
|
addi a5, a5, -2
|
|
|
|
s8i a6, a5, 0
|
|
|
|
s8i a7, a5, 1
|
|
|
|
bbsi.l a4, 0, .Lback15
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
.Lback15:
|
|
|
|
# copy 1 byte
|
|
|
|
addi a3, a3, -1
|
|
|
|
addi a5, a5, -1
|
|
|
|
l8ui a6, a3, 0
|
|
|
|
s8i a6, a5, 0
|
2019-05-13 11:28:25 +08:00
|
|
|
abi_ret_default
|
2012-10-16 12:41:19 +08:00
|
|
|
|
2017-12-04 05:28:52 +08:00
|
|
|
ENDPROC(__memmove)
|