2019-06-04 16:11:39 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-05-07 11:24:01 +08:00
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/*
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* PXA910 Power Management Routines
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*
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* (C) Copyright 2009 Marvell International Ltd.
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* All Rights Reserved
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*/
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#ifndef __PXA910_PM_H__
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#define __PXA910_PM_H__
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#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
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#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
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#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
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#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
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#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
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#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
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#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
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#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
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#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
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#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
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#define MPMU_FCCR MPMU_REG(0x0008)
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#define MPMU_APCR MPMU_REG(0x1000)
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#define MPMU_APCR_AXISD (1 << 31)
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#define MPMU_APCR_DSPSD (1 << 30)
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#define MPMU_APCR_SLPEN (1 << 29)
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#define MPMU_APCR_DTCMSD (1 << 28)
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#define MPMU_APCR_DDRCORSD (1 << 27)
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#define MPMU_APCR_APBSD (1 << 26)
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#define MPMU_APCR_BBSD (1 << 25)
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#define MPMU_APCR_SLPWP0 (1 << 23)
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#define MPMU_APCR_SLPWP1 (1 << 22)
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#define MPMU_APCR_SLPWP2 (1 << 21)
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#define MPMU_APCR_SLPWP3 (1 << 20)
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#define MPMU_APCR_VCTCXOSD (1 << 19)
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#define MPMU_APCR_SLPWP4 (1 << 18)
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#define MPMU_APCR_SLPWP5 (1 << 17)
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#define MPMU_APCR_SLPWP6 (1 << 16)
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#define MPMU_APCR_SLPWP7 (1 << 15)
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#define MPMU_APCR_MSASLPEN (1 << 14)
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#define MPMU_APCR_STBYEN (1 << 13)
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#define MPMU_AWUCRM MPMU_REG(0x104c)
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#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
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#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
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#define MPMU_AWUCRM_SDH1 (1 << 23)
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#define MPMU_AWUCRM_SDH2 (1 << 22)
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#define MPMU_AWUCRM_KEYPRESS (1 << 21)
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#define MPMU_AWUCRM_TRACKBALL (1 << 20)
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#define MPMU_AWUCRM_NEWROTARY (1 << 19)
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#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
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#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
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#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
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#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
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#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
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#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
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#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
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#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
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enum {
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POWER_MODE_ACTIVE = 0,
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POWER_MODE_CORE_INTIDLE,
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POWER_MODE_CORE_EXTIDLE,
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POWER_MODE_APPS_IDLE,
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POWER_MODE_APPS_SLEEP,
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POWER_MODE_SYS_SLEEP,
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POWER_MODE_HIBERNATE,
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POWER_MODE_UDR,
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};
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extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
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#endif
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