44 lines
1.7 KiB
Plaintext
44 lines
1.7 KiB
Plaintext
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Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
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ZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265
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decoder ip core.
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Each actual codec engines is controlled by a microcontroller (MCU). Host
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software uses a provided mailbox interface to communicate with the MCU. The
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MCU share an interrupt.
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Required properties:
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- compatible: value should be one of the following
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"allegro,al5e-1.1", "allegro,al5e": encoder IP core
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"allegro,al5d-1.1", "allegro,al5d": decoder IP core
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- reg: base and length of the memory mapped register region and base and
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length of the memory mapped sram
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- reg-names: must include "regs" and "sram"
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- interrupts: shared interrupt from the MCUs to the processing system
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- clocks: must contain an entry for each entry in clock-names
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- clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk",
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"m_axi_mcu_aclk", "s_axi_lite_aclk"
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Example:
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al5e: video-codec@a0009000 {
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compatible = "allegro,al5e-1.1", "allegro,al5e";
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reg = <0 0xa0009000 0 0x1000>,
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<0 0xa0000000 0 0x8000>;
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reg-names = "regs", "sram";
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interrupts = <0 96 4>;
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clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,
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<&clkc 71>, <&clkc 71>, <&clkc 71>;
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clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
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"m_axi_mcu_aclk", "s_axi_lite_aclk"
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};
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al5d: video-codec@a0029000 {
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compatible = "allegro,al5d-1.1", "allegro,al5d";
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reg = <0 0xa0029000 0 0x1000>,
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<0 0xa0020000 0 0x8000>;
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reg-names = "regs", "sram";
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interrupts = <0 96 4>;
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clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,
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<&clkc 71>, <&clkc 71>, <&clkc 71>;
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clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
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"m_axi_mcu_aclk", "s_axi_lite_aclk"
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};
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