一次输出所有warp的打印信息到test_run_dir/first_test, 在该路径下运行GPGPU_output_diff.py, 将输出log文件按照warp id分开.

GPGPU_output_diff.py

@@ -0,0 +1,29 @@
+import os
+import re
+import argparse
+
+warp_number = 4
+
+parser = argparse.ArgumentParser()
+parser.add_argument("--input_file", default='output.txt', help="log file from idea")
+args = parser.parse_args()
+if __name__ == '__main__':
+    out_file = []
+    print("test")
+    print(args.input_file)
+    for i in range(warp_number):
+        out_file.append("warp"+str(i))
+    with open(args.input_file, 'r') as f:
+        print("open output_txt")
+        for line in f.readlines():
+            # open four new files and move matching output information to relevant file.
+            if(line[0] != "\n"):
+                for i in range(warp_number):
+                    # print(line[1])
+                    # print(str(i))
+                    if re.match(str(i), line[5]):
+                        with open(out_file[i], 'a') as wf:
+                            wf.write(line)
+
+
+        

dependencies/fpuv2

@@ -1 +1 @@
-Subproject commit 8a8c1edbd3bf9ce06dde27b871fd7643eaf9babb
+Subproject commit 05842f7fa24bbe939e0af28eac2c9104a02dcf5b

ventus/src/pipeline/SIMT_STACK.scala

@@ -13,7 +13,7 @@ package pipeline
 import chisel3._
 import chisel3.util._
 import parameters._
-
+import java.io._
 
 class hash(val width:Int) extends Module{
   val io = IO(new Bundle() {
@@ -284,8 +284,8 @@ class SIMT_STACK(val depth_stack : Int) extends Module{
   }
   if(SPIKE_OUTPUT){
     fetch_ctl.spike_info.get:=branch_ctl_buf.bits.spike_info.get
-    when(io.complete.valid&&io.complete.bits===wid_to_check.U&& !io.branch_ctl.fire){
-      printf(p"0x00000000${Hexadecimal(io.branch_ctl.bits.spike_info.get.pc)} 0x${Hexadecimal(io.branch_ctl.bits.spike_info.get.inst)}")
+    when(io.complete.valid/*&&io.complete.bits===wid_to_check.U*/&& !io.branch_ctl.fire){
+      printf(p"warp${Decimal(io.complete.bits)} 0x00000000${Hexadecimal(io.branch_ctl.bits.spike_info.get.pc)} 0x${Hexadecimal(io.branch_ctl.bits.spike_info.get.inst)}")
       if_mask.asTypeOf(Vec(num_thread,Bool())).reverse.foreach(x=>printf(p"${Hexadecimal(x.asUInt)}"))
       printf(p"\n")
     }

ventus/src/pipeline/issue.scala

@@ -68,7 +68,8 @@ class Issue extends Module{
   io.out_SIMT.bits.mask_init:=inputBuf.bits.mask.asUInt()
   if(SPIKE_OUTPUT) {
     io.out_SIMT.bits.spike_info.get:=inputBuf.bits.ctrl.spike_info.get
-    when(io.out_LSU.fire&&io.out_LSU.bits.ctrl.mem&&io.out_LSU.bits.ctrl.wid===wid_to_check.U){
+    when(io.out_LSU.fire&&io.out_LSU.bits.ctrl.mem/*&&io.out_LSU.bits.ctrl.wid===wid_to_check.U*/){
+      printf(p"warp${Decimal(io.out_LSU.bits.ctrl.wid)} ")
       printf(p"0x00000000${Hexadecimal(io.out_LSU.bits.ctrl.spike_info.get.pc)} 0x${Hexadecimal(io.out_LSU.bits.ctrl.spike_info.get.inst)}")
       when(io.out_LSU.bits.ctrl.mem_cmd===1.U){
         printf(p" ${io.out_LSU.bits.ctrl.reg_idxw} op${io.out_LSU.bits.ctrl.mop}base${Hexadecimal(io.out_LSU.bits.in1(0))}bias${Hexadecimal(io.out_LSU.bits.in2(0))}\n")
@@ -79,7 +80,8 @@ class Issue extends Module{
       printf(p"\n")
     }
   }
-    when(io.out_warpscheduler.fire&&io.out_LSU.bits.ctrl.wid===wid_to_check.U){
+    when(io.out_warpscheduler.fire/*&&io.out_LSU.bits.ctrl.wid===wid_to_check.U*/){
+      printf(p"warp${Decimal(io.out_LSU.bits.ctrl.wid)} ")
       printf(p"0x00000000${Hexadecimal(io.out_LSU.bits.ctrl.spike_info.get.pc)} 0x${Hexadecimal(io.out_LSU.bits.ctrl.spike_info.get.inst)}")
       when(io.out_warpscheduler.bits.ctrl.barrier){printf(p" barrier\n")}
       when(io.out_warpscheduler.bits.ctrl.simt_stack_op){printf(p" endprg\n")}

ventus/src/pipeline/pipe.scala

@@ -187,7 +187,7 @@ class pipe extends Module{
   //输出所有write mem的操作
   val wid_to_check = 2.U //exe_data.io.deq.bits.ctrl.wid===wid_to_check&
   when( exe_data.io.deq.fire&exe_data.io.deq.bits.ctrl.mem_cmd===2.U){
-    printf(p"${exe_data.io.deq.bits.ctrl.wid},0x${Hexadecimal(exe_data.io.deq.bits.ctrl.pc)},inst=0x${Hexadecimal(exe_data.io.deq.bits.ctrl.inst)} ,writedata=")
+    printf(p"warp${exe_data.io.deq.bits.ctrl.wid} 0x${Hexadecimal(exe_data.io.deq.bits.ctrl.pc)},inst=0x${Hexadecimal(exe_data.io.deq.bits.ctrl.inst)} ,writedata=")
     exe_data.io.deq.bits.in3.foreach(x=>{printf(p"${Hexadecimal(x.asUInt)} ")})
     printf(p"mask ${exe_data.io.deq.bits.mask} at${Hexadecimal(exe_data.io.deq.bits.in1(0))},${Hexadecimal(exe_data.io.deq.bits.in2(0))}")
     printf(p"\n")

ventus/src/pipeline/writeback.scala

@@ -26,7 +26,8 @@ class Branch_back extends Module{
   arbiter.io.in(1)<>fifo1
   arbiter.io.out<>io.out
   if (SPIKE_OUTPUT) {
-    when(io.out.fire && io.out.bits.wid === wid_to_check.U) {
+    when(io.out.fire/* && io.out.bits.wid === wid_to_check.U*/) {
+      printf(p"warp${io.out.bits.wid} ")
       printf(p"0x00000000${Hexadecimal(io.out.bits.spike_info.get.pc)} 0x${Hexadecimal(io.out.bits.spike_info.get.inst)}")
       printf(p" Jump?${io.out.bits.jump}  ${Hexadecimal(io.out.bits.new_pc)}\n")
     }
@@ -59,11 +60,13 @@ class Writeback(num_x:Int,num_v:Int) extends Module{
   arbiter_v.io.out<>io.out_v
   //send to operand collector
   if(SPIKE_OUTPUT){
-    when(io.out_x.fire&&io.out_x.bits.warp_id===wid_to_check.U){
+    when(io.out_x.fire/*&&io.out_x.bits.warp_id===wid_to_check.U*/){
+      printf(p"warp${Decimal(io.out_x.bits.warp_id)} ")
       printf(p"0x00000000${Hexadecimal(io.out_x.bits.spike_info.get.pc)} 0x${Hexadecimal(io.out_x.bits.spike_info.get.inst)}")
       printf(p" ${io.out_x.bits.reg_idxw}  ${Hexadecimal(io.out_x.bits.wb_wxd_rd)}\n")
     }
-    when(io.out_v.fire && io.out_v.bits.warp_id === wid_to_check.U) {
+    when(io.out_v.fire/* && io.out_v.bits.warp_id === wid_to_check.U*/) {
+      printf(p"warp${Decimal(io.out_x.bits.warp_id)} ")
       printf(p"0x00000000${Hexadecimal(io.out_v.bits.spike_info.get.pc)} 0x${Hexadecimal(io.out_v.bits.spike_info.get.inst)}")
       printf(p" ${io.out_v.bits.reg_idxw} ")
       io.out_v.bits.wvd_mask.reverse.foreach(x=>printf(p"${Hexadecimal(x.asUInt)}"))