mirror of https://github.com/RT-Thread/rt-thread
feat: support ARCH_REMAP_KERNEL on libcpu/c906 (#9123)
feat: [libcpu/c906] support ARCH_REMAP_KERNEL This change was necessary to enable the remapping of the kernel image to a high virtual address region on the c906 platform. Changes: - Introduced new configuration options `ARCH_REMAP_KERNEL`, and `ARCH_USING_ASID` under the `ARCH_RISCV64` section. - Updated MMU initialization and switching functions to incorporate remapping handling. - Modified page table setup for proper memory attribute settings. - Added support for early memory setup, kernel remapping - Added conditional compilation for ASID support in the `rt_aspace` struct, since this is not enable currently for most architecture. Signed-off-by: Shell <smokewood@qq.com>
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Shell
GitHub
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@ -49,7 +49,11 @@ typedef struct rt_aspace
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struct rt_mutex bst_lock;
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struct rt_mem_obj *private_object;
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#ifdef ARCH_USING_ASID
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rt_uint64_t asid;
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#endif /* ARCH_USING_ASID */
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} *rt_aspace_t;
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typedef struct rt_varea
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@ -262,13 +262,17 @@ config ARCH_RISCV64
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select ARCH_CPU_64BIT
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bool
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if ARCH_RISCV64
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config ARCH_REMAP_KERNEL
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bool
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depends on RT_USING_SMART
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help
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Remapping kernel image to high virtual address region
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endif
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config ARCH_REMAP_KERNEL
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bool
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depends on RT_USING_SMART
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help
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Remapping kernel image to high virtual address region
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config ARCH_USING_ASID
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bool
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depends on RT_USING_SMART
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help
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Using ASID support from architecture
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config ARCH_IA32
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bool
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@ -43,6 +43,7 @@ static void *current_mmu_table = RT_NULL;
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volatile __attribute__((aligned(4 * 1024)))
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rt_ubase_t MMUTable[__SIZE(VPN2_BIT)];
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#ifdef ARCH_USING_ASID
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static rt_uint8_t ASID_BITS = 0;
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static rt_uint32_t next_asid;
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static rt_uint64_t global_asid_generation;
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@ -109,6 +110,24 @@ void rt_hw_aspace_switch(rt_aspace_t aspace)
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asm volatile("sfence.vma x0,%0"::"r"(asid):"memory");
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}
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#define ASID_INIT() _asid_init()
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#else /* ARCH_USING_ASID */
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#define ASID_INIT()
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void rt_hw_aspace_switch(rt_aspace_t aspace)
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{
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uintptr_t page_table = (uintptr_t)rt_kmem_v2p(aspace->page_table);
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current_mmu_table = aspace->page_table;
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write_csr(satp, (((size_t)SATP_MODE) << SATP_MODE_OFFSET) |
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((rt_ubase_t)page_table >> PAGE_OFFSET_BIT));
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rt_hw_tlb_invalidate_all_local();
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}
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#endif /* ARCH_USING_ASID */
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void *rt_hw_mmu_tbl_get()
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{
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return current_mmu_table;
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@ -552,7 +571,7 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
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mdesc++;
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}
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_asid_init();
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ASID_INIT();
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rt_hw_aspace_switch(&rt_kernel_space);
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rt_page_cleanup();
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@ -601,13 +620,15 @@ void rt_hw_mem_setup_early(void)
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LOG_E("%s: not aligned virtual address. pv_offset %p", __func__, pv_off);
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RT_ASSERT(0);
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}
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/**
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* identical mapping,
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* PC are still at lower region before relocating to high memory
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*/
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for (size_t i = 0; i < __SIZE(PPN0_BIT); i++)
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{
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early_pgtbl[i] = COMBINEPTE(ps, PAGE_ATTR_RWX | PTE_G | PTE_V);
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early_pgtbl[i] = COMBINEPTE(ps, PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE |
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PTE_SHARE | PTE_BUF | PTE_A | PTE_D);
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ps += L1_PAGE_SIZE;
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}
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@ -621,7 +642,8 @@ void rt_hw_mem_setup_early(void)
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rt_size_t ve_idx = GET_L1(vs + 0x80000000);
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for (size_t i = vs_idx; i < ve_idx; i++)
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{
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early_pgtbl[i] = COMBINEPTE(ps, PAGE_ATTR_RWX | PTE_G | PTE_V);
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early_pgtbl[i] = COMBINEPTE(ps, PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE |
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PTE_SHARE | PTE_BUF | PTE_A | PTE_D);
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ps += L1_PAGE_SIZE;
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}
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@ -8,13 +8,16 @@
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* 2018/10/01 Bernard The first version
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* 2018/12/27 Jesven Add SMP support
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* 2020/6/12 Xim Port to QEMU and remove SMP support
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* 2024-06-30 Shell Support of kernel remapping
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*/
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#include <encoding.h>
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#include <cpuport.h>
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boot_hartid: .int
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.global boot_hartid
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.data
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.global boot_hartid /* global varible rt_boot_hartid in .data section */
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boot_hartid:
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.word 0xdeadbeef
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.global _start
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.section ".start", "ax"
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@ -72,8 +75,6 @@ _start:
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li x31,0
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/* set to disable FPU */
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li t0, SSTATUS_FS
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csrc sstatus, t0
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li t0, SSTATUS_SUM
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csrs sstatus, t0
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@ -86,8 +87,45 @@ _start:
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la sp, __stack_start__
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li t0, __STACKSIZE__
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add sp, sp, t0
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csrw sscratch, sp
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/**
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* sscratch is always zero on kernel mode
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*/
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csrw sscratch, zero
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call init_bss
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call sbi_init
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j primary_cpu_entry
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#ifdef ARCH_MM_MMU
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call rt_hw_mem_setup_early
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call rt_kmem_pvoff
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/* a0 := pvoff */
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beq a0, zero, 1f
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/* relocate pc */
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la x1, _after_pc_relocation
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sub x1, x1, a0
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ret
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_after_pc_relocation:
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/* relocate gp */
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sub gp, gp, a0
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/* relocate context: sp */
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la sp, __stack_start__
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li t0, __STACKSIZE__
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add sp, sp, t0
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/* reset s0-fp */
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mv s0, zero
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/* relocate stvec */
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la t0, trap_entry
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csrw stvec, t0
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1:
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#endif
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call sbi_init
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call primary_cpu_entry
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_never_return_here:
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j .
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.global _start_link_addr
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_start_link_addr:
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.dword __text_start
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