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rt-thread
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Merge remote-tracking branch 'remotes/gitee/master' into gitee_master

This commit is contained in:
aozima 2020-10-09 15:17:27 +08:00
parent 79fd12842b aeff91b2a7
commit 05777266b9
1119 changed files with 72124 additions and 329178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
.travis.yml
View File

@ -66,8 +66,8 @@ env:
# - RTT_BSP='mini4020' # no scons
# - RTT_BSP='mm32l07x' # not support gcc
# - RTT_BSP='nios_ii' # no scons
- RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='pic32ethernet' # no scons
- RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
@ -123,6 +123,7 @@ env:
- RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32l496-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32mp157a-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32mp157a-st-ev1' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
# - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
@ -132,7 +133,7 @@ env:
- RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
# - RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'
- RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f403a-start' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f407-start' RTT_TOOL_CHAIN='sourcery-arm'

1
bsp/allwinner_tina/drivers/drv_gpio.c
View File

@ -538,6 +538,7 @@ static const struct rt_pin_ops ops =
pin_attach_irq,
pin_detach_irq,
pin_irq_enable,
RT_NULL,
};
#endif

1
bsp/apollo2/board/gpio.c
View File

@ -212,6 +212,7 @@ const static struct rt_pin_ops am_pin_ops =
am_pin_attach_irq,
am_pin_dettach_irq,
am_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

44
bsp/at32/Libraries/rt_drivers/drv_eth.c
View File

@ -31,6 +31,9 @@
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2
#define LINK_THREAD_STACK_SIZE 256
#define LINK_THREAD_PREORITY 21
extern ETH_DMADESCTypeDef *DMATxDescToSet;
extern ETH_DMADESCTypeDef *DMARxDescToGet;
extern ETH_DMADESCTypeDef *DMAPTPTxDescToSet;
@ -38,6 +41,8 @@ extern ETH_DMADESCTypeDef *DMAPTPRxDescToGet;
static ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
static struct rt_thread eth_link_thread;
static rt_uint8_t eth_link_stack[LINK_THREAD_STACK_SIZE];
#define MAX_ADDR_LEN 6
/* Gloable variables ---------------------------------------------------------*/
@ -634,6 +639,37 @@ struct pbuf *rt_at32_eth_rx(rt_device_t dev)
return p;
}
static void eth_link_thread_entry(void *paramter)
{
uint8_t linked_down = 1;
struct netif *pnetif = at32_eth_device.parent.netif;
while(1){
if((ETH_ReadPHYRegister(PHY_ADDRESS, PHY_BSR) & PHY_Linked_Status) && (linked_down == 1))
{
/* link up */
linked_down = 0;
#ifndef RT_LWIP_DHCP
pnetif->ip_addr = inet_addr(RT_LWIP_IPADDR);
pnetif->gw = inet_addr(RT_LWIP_GWADDR);
pnetif->netmask = inet_addr(RT_LWIP_MSKADDR);
#else
IP4_ADDR(&(pnetif->ip_addr), 0, 0, 0, 0);
IP4_ADDR(&(pnetif->netmask), 0, 0, 0, 0);
IP4_ADDR(&(pnetif->gw), 0, 0, 0, 0);
#endif
eth_device_linkchange(&(at32_eth_device.parent), RT_TRUE);
}else if(!(ETH_ReadPHYRegister(PHY_ADDRESS, PHY_BSR) & PHY_Linked_Status) && (linked_down == 0))
{
/* link down */
linked_down = 1;
eth_device_linkchange(&(at32_eth_device.parent), RT_FALSE);
}
rt_thread_mdelay(500);
}
}
/* interrupt service routine */
void ETH_IRQHandler(void)
{
@ -707,9 +743,17 @@ static int rt_hw_at32_eth_init(void)
/* register eth device */
state = eth_device_init(&(at32_eth_device.parent), "e0");
if (RT_EOK == state)
{
LOG_D("emac device init success");
state = rt_thread_init(&eth_link_thread, "eth_link_detect", eth_link_thread_entry, RT_NULL,
&eth_link_stack[0], LINK_THREAD_STACK_SIZE, LINK_THREAD_PREORITY, 20);
if (state == RT_EOK)
{
rt_thread_startup(&eth_link_thread);
}
}
else
{

1
bsp/at32/Libraries/rt_drivers/drv_gpio.c
View File

@ -496,6 +496,7 @@ const static struct rt_pin_ops _at32_pin_ops =
at32_pin_attach_irq,
at32_pin_dettach_irq,
at32_pin_irq_enable,
RT_NULL,
};
rt_inline void pin_irq_hdr(int irqno)

4
bsp/beaglebone/drivers/gpio.c
View File

@ -84,6 +84,10 @@ static struct rt_pin_ops am33xx_pin_ops =
am33xx_pin_mode,
am33xx_pin_write,
am33xx_pin_read,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
};
int rt_hw_gpio_init(void)

1
bsp/efm32/rtconfig.h
View File

@ -213,6 +213,7 @@
/* SECTION: Runtime library */
// #define RT_USING_NOLIBC
// #define RT_USING_NEWLIB
#define RT_LIBC_USING_TIME
/* SECTION: Console options */
#define RT_USING_CONSOLE

1
bsp/essemi/es32f0271/drivers/drv_gpio.c
View File

@ -450,6 +450,7 @@ const static struct rt_pin_ops _es32f0_pin_ops =
es32f0_pin_attach_irq,
es32f0_pin_detach_irq,
es32f0_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

1
bsp/essemi/es32f0334/drivers/drv_gpio.c
View File

@ -408,6 +408,7 @@ const static struct rt_pin_ops _es32f0_pin_ops =
es32f0_pin_attach_irq,
es32f0_pin_detach_irq,
es32f0_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

1
bsp/essemi/es32f0654/drivers/drv_gpio.c
View File

@ -408,6 +408,7 @@ const static struct rt_pin_ops _es32f0_pin_ops =
es32f0_pin_attach_irq,
es32f0_pin_detach_irq,
es32f0_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

77
bsp/essemi/es32f369x/.config
View File

@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -114,12 +114,10 @@ CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
CONFIG_RT_USING_CAN=y
# CONFIG_RT_CAN_USING_HDR is not set
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_USING_I2C_BITOPS is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
@ -194,11 +192,15 @@ CONFIG_RT_USING_PIN=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
@ -225,6 +227,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
@ -237,9 +240,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@ -256,6 +260,11 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
#
# security packages
@ -263,6 +272,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@ -297,6 +308,9 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
#
# system packages
@ -307,6 +321,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@ -317,6 +332,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
#
# peripheral libraries and drivers
@ -333,6 +354,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@ -350,6 +375,21 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
#
# miscellaneous packages
@ -386,6 +426,9 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
CONFIG_SOC_ES32F3696LT=y
#
@ -425,6 +468,28 @@ CONFIG_BSP_USING_UART0=y
#
# CONFIG_BSP_USING_CAN is not set
#
# ADC Drivers
#
# CONFIG_BSP_USING_ADC is not set
#
# RTC Drivers
#
# CONFIG_BSP_USING_RTC is not set
#
# HWtimer Drivers
#
# CONFIG_BSP_USING_HWTIMER0 is not set
# CONFIG_BSP_USING_HWTIMER1 is not set
#
# PWM Drivers
#
# CONFIG_BSP_USING_PWM0 is not set
# CONFIG_BSP_USING_PWM1 is not set
#
# Onboard Peripheral Drivers
#

28
bsp/essemi/es32f369x/README.md
View File

@ -13,9 +13,9 @@ ES-PDS-ES32F369x 是东软载波微电子官方推出的一款基于 ARM Cortex-
开发板外观如下图所示：
ES-PDS-ES32F369x-V1.2
ES-PDS-ES32F369x-V1.3
![ES32F0654](figures/ES-PDS-ES32F369x-V1.2.jpg)
![ES32F0654](figures/ES-PDS-ES32F369x-V1.3.jpg)
该开发板常用 **板载资源** 如下：
@ -32,15 +32,19 @@ ES-PDS-ES32F369x-V1.2
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :--------------- |
| SPI FLASH | 支持 | SPI0 |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | 50 GPIOs |
| UART | 支持 | UART0/1/2/3/4/5 |
| SPI | 支持 | SPI0/1/2 |
| I2C | 支持 | I2C0/1 |
| CAN | 支持 | CAN0 |
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :-------------- |
| SPI FLASH | 支持 | SPI0 |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | 50 GPIOs |
| UART | 支持 | UART0/1/2/3/4/5 |
| SPI | 支持 | SPI0/1/2 |
| I2C | 支持 | I2C0/1 |
| CAN | 支持 | CAN0 |
| PWM | 支持 | PWM0/1 |
| TIMER | 支持 | TIMER0/1 |
| RTC | 支持 | RTC |
| ADC | 支持 | ADC0 |
### 1.2 注意事项
@ -56,7 +60,7 @@ ES-PDS-ES32F369x-V1.2
使用ESlinkⅡ(mini)连接开发板如下图所示：
ESLinkⅡ(mini) + ES-PDS-ES32F369x-V1.2
ESLinkⅡ(mini) + ES-PDS-ES32F369x-V1.3
![ESLinkII](figures/ESLinkII-mini.jpg)

53
bsp/essemi/es32f369x/drivers/Kconfig
View File

@ -21,25 +21,25 @@ menu "Hardware Drivers Config"
bool "Enable UART2 PC12/PD02(T/R)"
select RT_USING_SERIAL
default y
depends on !BSP_USING_HWTIMER1
config BSP_USING_UART3
bool "Enable UART3 PC04/PC05(T/R)"
select RT_USING_SERIAL
default n
depends on !BSP_USING_HWTIMER2
depends on !BSP_USING_SPI2
config BSP_USING_UART4
bool "Enable UART4 PB06/PB07(T/R)"
select RT_USING_SERIAL
default n
depends on !BSP_USING_I2C0
depends on !BSP_USING_PWM0
config BSP_USING_UART5
bool "Enable UART5 PB09/PB08(T/R)"
select RT_USING_SERIAL
default n
depends on !BSP_USING_PWM0
endmenu
menu "SPI Drivers"
@ -60,16 +60,18 @@ menu "Hardware Drivers Config"
select RT_USING_SPI
select RT_USING_PIN
default n
depends on !BSP_USING_UART3
endmenu
menu "I2C Drivers"
config BSP_USING_I2C0
bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)"
bool "Enable I2C0 BUS PB06/PB07(SCL/SDA)"
select RT_USING_I2C
default n
depends on !BSP_USING_PWM0
config BSP_USING_I2C1
bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)"
bool "Enable I2C1 BUS PA05/PA06(SCL/SDA)"
select RT_USING_I2C
default n
endmenu
@ -80,6 +82,47 @@ menu "Hardware Drivers Config"
select RT_USING_CAN
default n
endmenu
menu "ADC Drivers"
config BSP_USING_ADC
bool "Using ADC"
select RT_USING_ADC
default n
endmenu
menu "RTC Drivers"
config BSP_USING_RTC
bool "Using RTC"
select RT_USING_RTC
default n
endmenu
menu "HWtimer Drivers"
config BSP_USING_HWTIMER0
bool "Using timer0"
select RT_USING_HWTIMER
default n
config BSP_USING_HWTIMER1
bool "Using timer1"
select RT_USING_HWTIMER
default n
endmenu
menu "PWM Drivers"
config BSP_USING_PWM0
bool "Using PWM0 PB06/PB07/PB08/PB09"
select RT_USING_PWM
default n
depends on !BSP_USING_CAN
depends on !BSP_USING_I2C0
config BSP_USING_PWM1
bool "Using PWM1 PA00/PA01/PA02/PA03"
select RT_USING_PWM
default n
endmenu
endmenu
menu "Onboard Peripheral Drivers"

16
bsp/essemi/es32f369x/drivers/SConscript
View File

@ -28,6 +28,22 @@ if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
if GetDepend('BSP_USING_CAN'):
src += ['drv_can.c']
# add adc driver code
if GetDepend(['BSP_USING_ADC']):
src += ['drv_adc.c']
# add rtc driver code
if GetDepend(['BSP_USING_RTC']):
src += ['drv_rtc.c']
# add hwtimer driver code
if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1'):
src += ['drv_hwtimer.c']
# add pwm driver code
if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1'):
src += ['drv_pwm.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)

2
bsp/essemi/es32f369x/drivers/board.h
View File

@ -14,7 +14,7 @@
#include <es32f36xx.h>
#define ES32F3_SRAM_SIZE 0x80000
#define ES32F3_SRAM_SIZE 0x18000
#define ES32F3_SRAM_END (0x20000000 + ES32F3_SRAM_SIZE)
#if defined(__CC_ARM) || defined(__CLANG_ARM)

194
bsp/essemi/es32f369x/drivers/drv_adc.c Normal file
View File

@ -0,0 +1,194 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-03 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_adc.h"
#include <ald_gpio.h>
#include <ald_adc.h>
#ifdef RT_USING_ADC
/* define adc instance */
static struct rt_adc_device _device_adc0;
/* enable or disable adc */
static rt_err_t es32f3_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data;
RT_ASSERT(device != RT_NULL);
if (enabled)
{
ADC_ENABLE(_hadc); ;
}
else
{
ADC_DISABLE(_hadc);
}
return RT_EOK;
}
static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel)
{
adc_channel_t es32f3_channel;
gpio_init_t gpio_initstruct;
/* Initialize ADC pin */
gpio_initstruct.mode = GPIO_MODE_INPUT;
gpio_initstruct.pupd = GPIO_FLOATING;
gpio_initstruct.podrv = GPIO_OUT_DRIVE_1;
gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1;
gpio_initstruct.flt = GPIO_FILTER_DISABLE;
gpio_initstruct.type = GPIO_TYPE_CMOS;
gpio_initstruct.func = GPIO_FUNC_0;
/* select gpio pin as adc function */
switch (channel)
{
case 0:
es32f3_channel = ADC_CHANNEL_0;
ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
break;
case 1:
es32f3_channel = ADC_CHANNEL_1;
ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
break;
case 2:
es32f3_channel = ADC_CHANNEL_2;
ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
break;
case 3:
es32f3_channel = ADC_CHANNEL_3;
ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
break;
case 4:
es32f3_channel = ADC_CHANNEL_4;
ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
break;
case 5:
es32f3_channel = ADC_CHANNEL_5;
ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
break;
case 6:
es32f3_channel = ADC_CHANNEL_6;
ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
break;
case 7:
es32f3_channel = ADC_CHANNEL_7;
ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
break;
case 8:
es32f3_channel = ADC_CHANNEL_8;
ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
break;
case 9:
es32f3_channel = ADC_CHANNEL_9;
ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
break;
case 10:
es32f3_channel = ADC_CHANNEL_10;
ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
break;
case 11:
es32f3_channel = ADC_CHANNEL_11;
ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
break;
case 12:
es32f3_channel = ADC_CHANNEL_12;
ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
break;
case 13:
es32f3_channel = ADC_CHANNEL_13;
ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
break;
case 14:
es32f3_channel = ADC_CHANNEL_14;
ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
break;
case 15:
es32f3_channel = ADC_CHANNEL_15;
ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
break;
case 16:
es32f3_channel = ADC_CHANNEL_16;
break;
case 17:
es32f3_channel = ADC_CHANNEL_17;
break;
case 18:
es32f3_channel = ADC_CHANNEL_18;
break;
default:
break;
}
return es32f3_channel;
}
static rt_err_t es32f3_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data;
adc_nch_conf_t nm_config;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
/* config adc channel */
nm_config.channel = es32f3_adc_get_channel(channel);
nm_config.rank = ADC_NCH_RANK_1;
nm_config.samp_time = ADC_SAMPLETIME_4;
ald_adc_normal_channel_config(_hadc, &nm_config);
ald_adc_normal_start(_hadc);
if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK)
*value = ald_adc_normal_get_value(_hadc);
return RT_EOK;
}
static const struct rt_adc_ops es32f3_adc_ops =
{
es32f3_adc_enabled,
es32f3_get_adc_value,
};
int rt_hw_adc_init(void)
{
int result = RT_EOK;
static adc_handle_t _h_adc0;
/* adc function initialization */
_h_adc0.perh = ADC0;
_h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan_mode = DISABLE;
_h_adc0.init.cont_mode = DISABLE;
_h_adc0.init.disc_mode = ADC_ALL_DISABLE;
_h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
_h_adc0.init.conv_res = ADC_CONV_RES_10;
_h_adc0.init.clk_div = ADC_CKDIV_128;
_h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
_h_adc0.init.pos_ref = ADC_POS_REF_VDD;
ald_adc_init(&_h_adc0);
rt_hw_adc_register(&_device_adc0, "adc0", &es32f3_adc_ops, &_h_adc0);
return result;
}
INIT_BOARD_EXPORT(rt_hw_adc_init);
#endif

16
bsp/essemi/es32f369x/drivers/drv_adc.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-04-03 wangyq the first version
*/
#ifndef DRV_ADC_H__
#define DRV_ADC_H__
int rt_hw_adc_init(void);
#endif

137
bsp/essemi/es32f369x/drivers/drv_gpio.c
View File

@ -17,10 +17,10 @@
#ifdef RT_USING_PIN
#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
#define __ES32F3_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
#define __ES32F3_PIN_DEFAULT {-1, 0, 0}
/* ES32F0 GPIO driver */
/* ES32F3 GPIO driver */
struct pin_index
{
int index;
@ -30,71 +30,71 @@ struct pin_index
static const struct pin_index pins[] =
{
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(2, C, 13),
__ES32F0_PIN(3, C, 14),
__ES32F0_PIN(4, C, 15),
__ES32F0_PIN(5, H, 0),
__ES32F0_PIN(6, H, 1),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(8, C, 0),
__ES32F0_PIN(9, C, 1),
__ES32F0_PIN(10, C, 2),
__ES32F0_PIN(11, C, 3),
__ES32F0_PIN(12, H, 3),
__ES32F0_PIN(13, H, 4),
__ES32F0_PIN(14, A, 0),
__ES32F0_PIN(15, A, 1),
__ES32F0_PIN(16, A, 2),
__ES32F0_PIN(17, A, 3),
__ES32F0_PIN(18, F, 0),
__ES32F0_PIN(19, F, 1),
__ES32F0_PIN(20, A, 4),
__ES32F0_PIN(21, A, 5),
__ES32F0_PIN(22, A, 6),
__ES32F0_PIN(23, A, 7),
__ES32F0_PIN(24, C, 4),
__ES32F0_PIN(25, C, 5),
__ES32F0_PIN(26, B, 0),
__ES32F0_PIN(27, B, 1),
__ES32F0_PIN(28, B, 2),
__ES32F0_PIN(29, B, 10),
__ES32F0_PIN(30, B, 11),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(33, B, 12),
__ES32F0_PIN(34, B, 13),
__ES32F0_PIN(35, B, 14),
__ES32F0_PIN(36, B, 15),
__ES32F0_PIN(37, C, 6),
__ES32F0_PIN(38, C, 7),
__ES32F0_PIN(39, C, 8),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(46, A, 13),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN(49, A, 14),
__ES32F0_PIN(50, A, 15),
__ES32F0_PIN(51, C, 10),
__ES32F0_PIN(52, C, 11),
__ES32F0_PIN(53, C, 12),
__ES32F0_PIN(54, D, 2),
__ES32F0_PIN(55, B, 3),
__ES32F0_PIN(56, B, 4),
__ES32F0_PIN(57, B, 5),
__ES32F0_PIN(58, B, 6),
__ES32F0_PIN(59, B, 7),
__ES32F0_PIN(60, H, 2),
__ES32F0_PIN(61, B, 8),
__ES32F0_PIN(62, B, 9),
__ES32F0_PIN_DEFAULT,
__ES32F0_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(2, C, 13),
__ES32F3_PIN(3, C, 14),
__ES32F3_PIN(4, C, 15),
__ES32F3_PIN(5, H, 0),
__ES32F3_PIN(6, H, 1),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(8, C, 0),
__ES32F3_PIN(9, C, 1),
__ES32F3_PIN(10, C, 2),
__ES32F3_PIN(11, C, 3),
__ES32F3_PIN(12, H, 3),
__ES32F3_PIN(13, H, 4),
__ES32F3_PIN(14, A, 0),
__ES32F3_PIN(15, A, 1),
__ES32F3_PIN(16, A, 2),
__ES32F3_PIN(17, A, 3),
__ES32F3_PIN(18, F, 0),
__ES32F3_PIN(19, F, 1),
__ES32F3_PIN(20, A, 4),
__ES32F3_PIN(21, A, 5),
__ES32F3_PIN(22, A, 6),
__ES32F3_PIN(23, A, 7),
__ES32F3_PIN(24, C, 4),
__ES32F3_PIN(25, C, 5),
__ES32F3_PIN(26, B, 0),
__ES32F3_PIN(27, B, 1),
__ES32F3_PIN(28, B, 2),
__ES32F3_PIN(29, B, 10),
__ES32F3_PIN(30, B, 11),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(33, B, 12),
__ES32F3_PIN(34, B, 13),
__ES32F3_PIN(35, B, 14),
__ES32F3_PIN(36, B, 15),
__ES32F3_PIN(37, C, 6),
__ES32F3_PIN(38, C, 7),
__ES32F3_PIN(39, C, 8),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(46, A, 13),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN(49, A, 14),
__ES32F3_PIN(50, A, 15),
__ES32F3_PIN(51, C, 10),
__ES32F3_PIN(52, C, 11),
__ES32F3_PIN(53, C, 12),
__ES32F3_PIN(54, D, 2),
__ES32F3_PIN(55, B, 3),
__ES32F3_PIN(56, B, 4),
__ES32F3_PIN(57, B, 5),
__ES32F3_PIN(58, B, 6),
__ES32F3_PIN(59, B, 7),
__ES32F3_PIN(60, H, 2),
__ES32F3_PIN(61, B, 8),
__ES32F3_PIN(62, B, 9),
__ES32F3_PIN_DEFAULT,
__ES32F3_PIN_DEFAULT,
};
struct pin_irq_map
@ -408,6 +408,7 @@ const static struct rt_pin_ops _es32f3_pin_ops =
es32f3_pin_attach_irq,
es32f3_pin_detach_irq,
es32f3_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

193
bsp/essemi/es32f369x/drivers/drv_hwtimer.c Normal file
View File

@ -0,0 +1,193 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-3-19 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <drv_hwtimer.h>
#include <board.h>
#include <ald_cmu.h>
#include <ald_timer.h>
#ifdef RT_USING_HWTIMER
struct es32f3_hwtimer_dev
{
rt_hwtimer_t parent;
timer_handle_t *hwtimer_periph;
IRQn_Type IRQn;
};
#ifdef BSP_USING_HWTIMER0
static struct es32f3_hwtimer_dev hwtimer0;
void BS16T0_Handler(void)
{
ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer0.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode)
{
ald_timer_base_stop(hwtimer0.hwtimer_periph);
}
}
#endif
#ifdef BSP_USING_HWTIMER1
static struct es32f3_hwtimer_dev hwtimer1;
/* can not use when UART2 Handler is enabled */
void BS16T1_Handler(void)
{
/* if BS16T1 it */
if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
{
ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
rt_device_hwtimer_isr(&hwtimer1.parent);
if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
{
ald_timer_base_stop(hwtimer1.hwtimer_periph);
}
}
}
#endif
static struct rt_hwtimer_info es32f3_hwtimer_info =
{
96000000, /* maximum count frequency */
1, /* minimum count frequency */
65535, /* counter maximum value */
HWTIMER_CNTMODE_UP
};
static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
if (1 == state)
{
ald_timer_base_init(hwtimer->hwtimer_periph);
ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
NVIC_EnableIRQ(hwtimer->IRQn);
}
hwtimer->parent.freq = ald_cmu_get_pclk1_clock();
es32f3_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock();
es32f3_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock();
}
static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer,
rt_uint32_t cnt,
rt_hwtimer_mode_t mode)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
ald_timer_base_start(hwtimer->hwtimer_periph);
return RT_EOK;
}
static void es32f3_hwtimer_stop(rt_hwtimer_t *timer)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
ald_timer_base_stop(hwtimer->hwtimer_periph);
}
static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer)
{
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
uint32_t hwtimer_count = 0;
RT_ASSERT(hwtimer != RT_NULL);
hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT);
return hwtimer_count;
}
static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer,
rt_uint32_t cmd,
void *args)
{
rt_err_t ret = RT_EOK;
rt_uint32_t freq = 0;
struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
RT_ASSERT(hwtimer != RT_NULL);
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
freq = *(rt_uint32_t *)args;
if (freq != ald_cmu_get_pclk1_clock())
{
ret = -RT_ERROR;
}
break;
case HWTIMER_CTRL_STOP:
ald_timer_base_stop(hwtimer->hwtimer_periph);
break;
default:
ret = RT_EINVAL;
break;
}
return ret;
}
static struct rt_hwtimer_ops es32f3_hwtimer_ops =
{
es32f3_hwtimer_init,
es32f3_hwtimer_start,
es32f3_hwtimer_stop,
es32f3_hwtimer_count_get,
es32f3_hwtimer_control
};
int rt_hw_hwtimer_init(void)
{
rt_err_t ret = RT_EOK;
#ifdef BSP_USING_HWTIMER0
static timer_handle_t _hwtimer_periph0;
_hwtimer_periph0.perh = BS16T0;
hwtimer0.IRQn = BS16T0_IRQn;
hwtimer0.hwtimer_periph = &_hwtimer_periph0;
hwtimer0.parent.info = &es32f3_hwtimer_info;
hwtimer0.parent.ops = &es32f3_hwtimer_ops;
ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0);
#endif
#ifdef BSP_USING_HWTIMER1
static timer_handle_t _hwtimer_periph1;
_hwtimer_periph1.perh = BS16T1;
hwtimer1.IRQn = BS16T1_IRQn;
hwtimer1.hwtimer_periph = &_hwtimer_periph1;
hwtimer1.parent.info = &es32f3_hwtimer_info;
hwtimer1.parent.ops = &es32f3_hwtimer_ops;
ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
#endif
return ret;
}
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
#endif

16
bsp/essemi/es32f369x/drivers/drv_hwtimer.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-3-19 wangyq the first version
*/
#ifndef DRV_HWTIMER_H__
#define DRV_HWTIMER_H__
int rt_hw_hwtimer_init(void);
#endif

11
bsp/essemi/es32f369x/drivers/drv_i2c.c
View File

@ -16,6 +16,7 @@
#include "drv_i2c.h"
#include <ald_i2c.h>
#include <ald_gpio.h>
#include <rtdbg.h>
#ifdef RT_USING_I2C
@ -55,8 +56,8 @@ static void _i2c_init(void)
ald_i2c_reset(&_h_i2c0);
ald_i2c_init(&_h_i2c0);
/* PB8->I2C0_SCL, PB9->I2C0_SDA */
ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
/* PB06->I2C0_SCL, PB07->I2C0_SDA */
ald_gpio_init(GPIOB, GPIO_PIN_6 | GPIO_PIN_7, &gpio_instruct);
#endif
#ifdef BSP_USING_I2C1
@ -90,7 +91,7 @@ static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
{
if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
{
i2c_dbg("i2c bus write failed,i2c bus stop!\n");
LOG_E("i2c bus write failed,i2c bus stop!\n");
goto out;
}
}
@ -98,7 +99,7 @@ static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
{
if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
{
i2c_dbg("i2c bus write failed,i2c bus stop!\n");
LOG_E("i2c bus write failed,i2c bus stop!\n");
goto out;
}
}
@ -107,7 +108,7 @@ static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
ret = i;
out:
i2c_dbg("send stop condition\n");
LOG_E("send stop condition\n");
return ret;
}

171
bsp/essemi/es32f369x/drivers/drv_pwm.c Normal file
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@ -0,0 +1,171 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-11 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include <ald_cmu.h>
#include <ald_timer.h>
#include <ald_gpio.h>
static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns)
{
uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
(timer_initstruct->init.prescaler + 1);
WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr);
timer_initstruct->init.period = (uint32_t)_arr;
}
static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns)
{
uint64_t tmp = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
(timer_initstruct->init.prescaler + 1);
if (ch == TIMER_CHANNEL_1)
WRITE_REG(timer_initstruct->perh->CCVAL1, (uint32_t)tmp);
else if (ch == TIMER_CHANNEL_2)
WRITE_REG(timer_initstruct->perh->CCVAL2, (uint32_t)tmp);
else if (ch == TIMER_CHANNEL_3)
WRITE_REG(timer_initstruct->perh->CCVAL3, (uint32_t)tmp);
else if (ch == TIMER_CHANNEL_4)
WRITE_REG(timer_initstruct->perh->CCVAL4, (uint32_t)tmp);
}
static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
rt_err_t ret = RT_EOK;
uint32_t _ccep;
timer_channel_t pwm_channel;
timer_oc_init_t tim_ocinit;
timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data;
struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
RT_ASSERT(timer_initstruct != RT_NULL);
tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1;
tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH;
tim_ocinit.oc_fast_en = DISABLE;
tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH;
tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET;
tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET;
/* select pwm output channel */
if (1 == cfg->channel)
pwm_channel = TIMER_CHANNEL_1;
else if (2 == cfg->channel)
pwm_channel = TIMER_CHANNEL_2;
else if (3 == cfg->channel)
pwm_channel = TIMER_CHANNEL_3;
else if (4 == cfg->channel)
pwm_channel = TIMER_CHANNEL_4;
else
return RT_EINVAL;
switch (cmd)
{
case PWM_CMD_ENABLE:
ald_timer_pwm_start(timer_initstruct, pwm_channel);
break;
case PWM_CMD_DISABLE:
ald_timer_pwm_stop(timer_initstruct, pwm_channel);
break;
case PWM_CMD_SET:
_ccep = timer_initstruct->perh->CCEP;
/* count registers max 0xFFFF, auto adjust prescaler */
do
{
pwm_set_freq(timer_initstruct, cfg->period);
timer_initstruct->init.prescaler ++;
}
while (timer_initstruct->init.period > 0xFFFF);
/* update prescaler */
WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler);
ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse);
timer_initstruct->perh->CCEP = _ccep;
break;
case PWM_CMD_GET:
cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 /
READ_REG(timer_initstruct->perh->AR);
break;
default:
break;
}
return ret;
}
const static struct rt_pwm_ops es32f3_pwm_ops =
{
es32f3_pwm_control
};
int rt_hw_pwm_init(void)
{
rt_err_t ret = RT_EOK;
gpio_init_t gpio_initstructure;
gpio_initstructure.mode = GPIO_MODE_OUTPUT;
gpio_initstructure.odos = GPIO_PUSH_PULL;
gpio_initstructure.pupd = GPIO_PUSH_UP;
gpio_initstructure.podrv = GPIO_OUT_DRIVE_6;
gpio_initstructure.nodrv = GPIO_OUT_DRIVE_6;
gpio_initstructure.flt = GPIO_FILTER_DISABLE;
gpio_initstructure.type = GPIO_TYPE_TTL;
#ifdef BSP_USING_PWM0 /* 4 channels */
static struct rt_device_pwm pwm_dev0;
static timer_handle_t timer_initstruct0;
timer_initstruct0.perh = GP16C4T0;
ald_timer_pwm_init(&timer_initstruct0);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_2;
ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f3_pwm_ops,
&timer_initstruct0);
#endif
#ifdef BSP_USING_PWM1 /* 4 channels */
static struct rt_device_pwm pwm_dev1;
static timer_handle_t timer_initstruct1;
timer_initstruct1.perh = GP16C4T1;
ald_timer_pwm_init(&timer_initstruct1);
/* gpio initialization */
gpio_initstructure.func = GPIO_FUNC_5;
ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstructure);
ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstructure);
ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f3_pwm_ops,
&timer_initstruct1);
#endif
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_pwm_init);

16
bsp/essemi/es32f369x/drivers/drv_pwm.h Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-11 wangyq the first version
*/
#ifndef DRV_PWM_H__
#define DRV_PWM_H__
int rt_hw_pwm_init(void);
#endif

158
bsp/essemi/es32f369x/drivers/drv_rtc.c Normal file
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@ -0,0 +1,158 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-22 wangyq the first version
* 2019-11-01 wangyq update libraries
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <string.h>
#include "board.h"
#include "drv_rtc.h"
#include <ald_cmu.h>
#include <ald_rtc.h>
#ifdef RT_USING_RTC
static void __rtc_init(rtc_init_t *init)
{
assert_param(IS_RTC_HOUR_FORMAT(init->hour_format));
assert_param(IS_RTC_OUTPUT_SEL(init->output));
assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
ald_rtc_reset();
RTC_UNLOCK();
MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS);
MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS);
MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS);
MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS);
MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS);
RTC_LOCK();
return;
}
static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
struct tm time_temp;
struct tm *pNow;
rtc_date_t date;
rtc_time_t time;
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
ald_rtc_get_date_time(&date, &time, RTC_FORMAT_DEC);
time_temp.tm_sec = time.second;
time_temp.tm_min = time.minute;
time_temp.tm_hour = time.hour;
time_temp.tm_mday = date.day;
time_temp.tm_mon = date.month - 1;
time_temp.tm_year = date.year - 1900 + 2000;
*((time_t *)args) = mktime(&time_temp);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
rt_enter_critical();
/* converts calendar time time into local time. */
pNow = localtime((const time_t *)args);
/* copy the statically located variable */
memcpy(&time_temp, pNow, sizeof(struct tm));
/* unlock scheduler. */
rt_exit_critical();
time.hour = time_temp.tm_hour;
time.minute = time_temp.tm_min;
time.second = time_temp.tm_sec;
date.year = time_temp.tm_year + 1900 - 2000;
date.month = time_temp.tm_mon + 1;
date.day = time_temp.tm_mday;
ald_rtc_set_time(&time, RTC_FORMAT_DEC);
ald_rtc_set_date(&date, RTC_FORMAT_DEC);
/* start RTC */
RTC_UNLOCK();
SET_BIT(RTC->CON, RTC_CON_GO_MSK);
RTC_LOCK();
break;
case RT_DEVICE_CTRL_RTC_GET_ALARM:
break;
case RT_DEVICE_CTRL_RTC_SET_ALARM:
break;
default:
break;
}
return result;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops es32f0_rtc_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
es32f0_rtc_control
};
#endif
int rt_hw_rtc_init(void)
{
rt_err_t ret = RT_EOK;
static struct rt_device rtc_dev;
rtc_init_t rtc_initstruct;
/* enable external 32.768kHz */
CMU_LOSC_ENABLE();
ald_cmu_losc_safe_config(ENABLE);
/* set default time */
RTC_UNLOCK();
WRITE_REG(RTC->TIME, 0x134251);
WRITE_REG(RTC->DATE, 0x1190401);
RTC_LOCK();
/* RTC function initialization */
rtc_initstruct.hour_format = RTC_HOUR_FORMAT_24;
rtc_initstruct.asynch_pre_div = 0;
rtc_initstruct.synch_pre_div = 32767;
rtc_initstruct.output = RTC_OUTPUT_DISABLE;
__rtc_init(&rtc_initstruct);
rtc_dev.type = RT_Device_Class_RTC;
rtc_dev.rx_indicate = RT_NULL;
rtc_dev.tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
rtc_dev.ops = &es32f0_rtc_ops;
#else
rtc_dev.init = RT_NULL;
rtc_dev.open = RT_NULL;
rtc_dev.close = RT_NULL;
rtc_dev.read = RT_NULL;
rtc_dev.write = RT_NULL;
rtc_dev.control = es32f0_rtc_control;
#endif
rtc_dev.user_data = RTC;
ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR);
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif

16
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-22 wangyq the first version
*/
#ifndef DRV_RTC_H__
#define DRV_RTC_H__
int rt_hw_rtc_init(void);
#endif

2
bsp/essemi/es32f369x/drivers/drv_uart.c
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@ -39,7 +39,7 @@ static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial
gpio_initstructure.odos = GPIO_PUSH_PULL;
gpio_initstructure.pupd = GPIO_PUSH_UP;
gpio_initstructure.podrv = GPIO_OUT_DRIVE_1;
gpio_initstructure.nodrv = GPIO_OUT_DRIVE_0_1;
gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1;
gpio_initstructure.flt = GPIO_FILTER_DISABLE;
gpio_initstructure.type = GPIO_TYPE_TTL;

34
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@ -0,0 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, last block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

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810
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0
bsp/nuvoton_nuc472/project.eww → bsp/essemi/es32f369x/project.eww
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23
bsp/essemi/es32f369x/project.uvprojx
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@ -331,7 +331,7 @@
<MiscControls />
<Define>ES32F36xx</Define>
<Undefine />
<IncludePath>.;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common</IncludePath>
<IncludePath>.;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -795,27 +795,6 @@
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>can.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\can\can.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>i2c_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\i2c\i2c_core.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>i2c_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\i2c\i2c_dev.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>pin.c</FileName>

16
bsp/essemi/es32f369x/rtconfig.h
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@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
@ -76,8 +76,6 @@
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_USING_I2C
#define RT_USING_PIN
/* Using USB */
@ -166,6 +164,18 @@
/* CAN Drivers */
/* ADC Drivers */
/* RTC Drivers */
/* HWtimer Drivers */
/* PWM Drivers */
/* Onboard Peripheral Drivers */
/* Offboard Peripheral Drivers */

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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

1
bsp/essemi/es8p508x/drivers/drv_gpio.c
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@ -382,6 +382,7 @@ const static struct rt_pin_ops _es8p_pin_ops =
es8p_pin_attach_irq,
es8p_pin_detach_irq,
es8p_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

1
bsp/gd32303e-eval/drivers/drv_gpio.c
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@ -497,6 +497,7 @@ const static struct rt_pin_ops _gd32_pin_ops =
gd32_pin_attach_irq,
gd32_pin_detach_irq,
gd32_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

1
bsp/gd32e230k-start/drivers/drv_gpio.c
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@ -388,6 +388,7 @@ const static struct rt_pin_ops _gd32_pin_ops =
gd32_pin_attach_irq,
gd32_pin_detach_irq,
gd32_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

1
bsp/gd32vf103v-eval/drivers/drv_gpio.c
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@ -427,6 +427,7 @@ const static struct rt_pin_ops _gd32vf_pin_ops =
gd32vf_pin_attach_irq,
gd32vf_pin_dettach_irq,
gd32vf_pin_irq_enable,
RT_NULL,
};
rt_inline void pin_irq_hdr(int irqno)

113
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@ -1,105 +1,80 @@
# i.MX RT1050 EVK 开发板 BSP 说明
# NXP i. MX RT1050 EVK BSP(Board Support Package) Execution Instruction.
## 简介
[中文页](README_zh.md) |
本文档为 RT-Thread 开发团队为 NXP i.MX RT1050 EVK 开发板提供的 BSP (板级支持包) 说明。
## Introduction
主要内容如下：
This document records the execution instruction of the BSP (board support package) provided by the RT-Thread development team for the NXP i. MX RT1050 EVK development board.
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
The document is covered in three parts:
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
- NXP i. MX RT1050 EVK Board Resources Introduction
- Quickly Get Started
- Advanced Features
## 开发板介绍
By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
i.MX RT1050 EVK 是 NXP 官方推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 600MHz，该开发板具有丰富的板载资源，可以充分发挥 RT1052 的芯片性能。
## Board Resources Introduction
开发板外观如下图所示：
The i.MX RT1050 EVK is a development board based on ARM Cortex-M7. The maximum main frequency is 600 MHz, and it has a wealth of on-board resources that can take full advantage of the RT1052's chip performance.
![board](figures/board.jpg)
[![board](https://github.com/RT-Thread/rt-thread/raw/master/bsp/imxrt/imxrt1052-nxp-evk/figures/board.jpg)](https://github.com/RT-Thread/rt-thread/blob/master/bsp/imxrt/imxrt1052-nxp-evk/figures/board.jpg)
该开发板常用**板载资源**如下：
The mainly-used resources of this board are shown as follows:
- MCU：MIMXRT1052DVL6A，主频 600MHz
- 存储：256MB SDRAM、512MB Hyper FLASH
- 常用外设
- 运动传感器：FXOS8700CQ
- MCU: MIMXRT1052DVL6A. Main Frequency 600MHz,
- Memory: 256MB SDRAM、512MB Hyper FLASH
- Common-used peripherals:
- Motion Sensors: FXOS8700CQ
- LED
- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口、摄像头接口
- 调试接口：标准 JTAG/SWD
- Common-used interfaces: USB、SD Card、Ethernet、LCD、Camera.
- Debug interface: Standard JTAG/SWD. For more details about this board, please refer to [nxp.com](https://www.nxp.com/)
开发板更多的详细信息请参考 NXP [i.MX RT1050 EVK 开发板介绍](https://www.nxp.com)。
## Peripheral Condition
## 外设支持
Each peripheral supporting condition for this BSP is as follows:
本 BSP 目前对外设的支持情况如下：
| **On-chip Peripheral** | **Support** | **Remark** |
| ---------------------- | ----------- | ---------- |
| GPIO | Support | |
| UART | Support | UART1 |
| **片上外设** | **支持情况** | **备注** |
| :---------------- | :----------: | :------------------------------------------------------ |
| GPIO | 支持 | |
| UART | 支持 | UART1 |
## Execution Instruction
## 使用说明
### Quickly Get Started
使用说明分为如下两个章节：
This BSP provides MDK 5 and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system.
- 快速上手
#### Hardware Connection
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
Use a USB cable to connect the development board to the PC and turn on the power switch.
- 进阶使用
#### Compile and Download
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
Double-click the project.uvprojx file, to open the MDK 5 project, compile and download the project to the board.
> By default, the project uses the CMSIS-DAP to download the program, when the CMSIS-DAP connects the board, clicking the download button can download the program to the board.
### 快速上手
### **Running Results**
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
Once the project is successfully downloaded, the system runs automatically. The green LED on the board will flash periodically.
#### 硬件连接
Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，绿色 LED 会周期性闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
```
\ | /
- RT - Thread Operating System
/ | \ 4.0.1 build May 5 2019
2006 - 2019 Copyright by rt-thread team
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口 1 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
## **Advanced Features**
1. 在 bsp 下打开 env 工具。
This BSP only enables GPIO and serial port 1 by default. If you need more advanced features, you need to configure the BSP with RT-Thread [Env tools](https://www.rt-thread.io/download.html?download=Env), as follows:
2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
1. Open the env tool under BSP;
2. Enter menuconfig command to configure the project, then save and exit;
3. Enter pkgs --update command to update the package;
4. Enter scons --target=mdk4/mdk5/iar command to regenerate the project.
3. 输入 `pkgs --update` 命令更新软件包。
4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。
本章节更多详细的介绍请参考 [i.MXRT 系列 BSP 外设驱动使用教程](../docs/IMXRT系列BSP外设驱动使用教程.md)。
## 注意事项
暂无
## 联系人信息
维护人:
- [tyustli](https://github.com/tyustli)
Learn how to use RT-Thread Env, click [Here](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md).

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@ -0,0 +1,105 @@
# i.MX RT1050 EVK 开发板 BSP 说明
## 简介
本文档为 RT-Thread 开发团队为 NXP i.MX RT1050 EVK 开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
i.MX RT1050 EVK 是 NXP 官方推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 600MHz，该开发板具有丰富的板载资源，可以充分发挥 RT1052 的芯片性能。
开发板外观如下图所示：
![board](figures/board.jpg)
该开发板常用**板载资源**如下：
- MCU：MIMXRT1052DVL6A，主频 600MHz
- 存储：256MB SDRAM、512MB Hyper FLASH
- 常用外设
- 运动传感器：FXOS8700CQ
- LED
- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口、摄像头接口
- 调试接口：标准 JTAG/SWD
开发板更多的详细信息请参考 NXP [i.MX RT1050 EVK 开发板介绍](https://www.nxp.com)。
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :---------------- | :----------: | :------------------------------------------------------ |
| GPIO | 支持 | |
| UART | 支持 | UART1 |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，绿色 LED 会周期性闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.1 build May 5 2019
2006 - 2019 Copyright by rt-thread team
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口 1 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
3. 输入 `pkgs --update` 命令更新软件包。
4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。
本章节更多详细的介绍请参考 [i.MXRT 系列 BSP 外设驱动使用教程](../docs/IMXRT系列BSP外设驱动使用教程.md)。
## 注意事项
暂无
## 联系人信息
维护人:
- [tyustli](https://github.com/tyustli)

6
bsp/imxrt/imxrt1064-nxp-evk/SConstruct
View File

@ -46,10 +46,10 @@ Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/Libraries'):
libraries_path_prefix = SDK_ROOT + '/Libraries'
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries'
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')

5
bsp/imxrt/libraries/drivers/drv_eth.c
View File

@ -22,6 +22,7 @@
#include "fsl_phy.h"
#include "fsl_cache.h"
#include "fsl_iomuxc.h"
#include "fsl_common.h"
#ifdef RT_USING_LWIP
@ -62,10 +63,10 @@ struct rt_imxrt_eth
enet_mii_duplex_t duplex;
};
ALIGN(ENET_BUFF_ALIGNMENT) enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] SECTION("NonCacheable");
AT_NONCACHEABLE_SECTION_ALIGN(enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT);
ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)];
ALIGN(ENET_BUFF_ALIGNMENT) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] SECTION("NonCacheable");
AT_NONCACHEABLE_SECTION_ALIGN(enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT);
ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)];
static struct rt_imxrt_eth imxrt_eth_device;

3
bsp/imxrt/libraries/drivers/drv_gpio.c
View File

@ -587,7 +587,8 @@ const static struct rt_pin_ops imxrt_pin_ops =
imxrt_pin_read,
imxrt_pin_attach_irq,
imxrt_pin_detach_irq,
imxrt_pin_irq_enable
imxrt_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

3
bsp/k210/driver/drv_gpio.c
View File

@ -251,7 +251,8 @@ const static struct rt_pin_ops drv_pin_ops =
drv_pin_attach_irq,
drv_pin_detach_irq,
drv_pin_irq_enable
drv_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

151
bsp/lpc408x/.config
View File

@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@ -63,8 +64,9 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40001
CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -138,6 +140,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
@ -147,10 +150,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
@ -158,10 +161,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using WiFi
#
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
@ -175,6 +178,7 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_LIBC_USING_TIME=y
#
# Network
@ -185,18 +189,15 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP202 is not set
# CONFIG_RT_USING_LWIP210 is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
@ -211,16 +212,9 @@ CONFIG_RT_USING_PIN=y
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
#
# ARM CMSIS
#
# CONFIG_RT_USING_CMSIS_OS is not set
# CONFIG_RT_USING_RTT_CMSIS is not set
# CONFIG_RT_USING_LWP is not set
#
@ -230,13 +224,20 @@ CONFIG_RT_USING_PIN=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
@ -254,10 +255,14 @@ CONFIG_RT_USING_PIN=y
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
@ -267,7 +272,29 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
#
# security packages
@ -275,6 +302,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@ -288,6 +317,9 @@ CONFIG_RT_USING_PIN=y
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
@ -299,6 +331,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
@ -310,27 +351,74 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
#
# miscellaneous packages
@ -341,11 +429,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
@ -356,6 +448,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_THREES is not set
CONFIG_SOC_LPC4088=y
#

16
bsp/lpc408x/rtconfig.h
View File

@ -40,8 +40,9 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40001
#define RT_VER_NUM 0x40003
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
@ -101,26 +102,24 @@
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using WiFi */
/* Using USB */
/* POSIX layer and C standard library */
#define RT_LIBC_USING_TIME
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* Modbus master and slave stack */
/* AT commands */
@ -130,9 +129,6 @@
/* Utilities */
/* ARM CMSIS */
/* RT-Thread online packages */
/* IoT - internet of things */

45
bsp/lpc54114-lite/drivers/drv_gpio.c
View File

@ -38,6 +38,48 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{-1, 0, RT_NULL, RT_NULL},
};
static rt_base_t lpc_pin_get(const char *name)
{
rt_base_t pin = 0;
int hw_port_num, hw_pin_num = 0;
int i, name_len = 1;
int mul = 1;
name_len = rt_strlen(name);
if ((name_len < 4) || (name_len >= 6))
{
return -RT_EINVAL;
}
if ((name[0] != 'P') || (name[2] != '.'))
{
return -RT_EINVAL;
}
if ((name[1] >= '0') && (name[1] <= '9'))
{
hw_port_num = (int)(name[1] - '0');
}
else
{
return -RT_EINVAL;
}
for (i = name_len - 1; i > 2; i--)
{
hw_pin_num += ((int)(name[i] - '0') * mul);
mul = mul * 10;
}
pin = 32 * hw_port_num + hw_pin_num;
if ((pin > PIN_MAX_VAL) || (pin < 0))
{
return -RT_EINVAL;
}
return pin;
}
/* Configure pin mode. pin 0~63 means PIO0_0 ~ PIO1_31 */
static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
@ -288,7 +330,8 @@ const static struct rt_pin_ops _lpc_pin_ops =
lpc_pin_read,
lpc_pin_attach_irq,
lpc_pin_detach_irq,
lpc_pin_irq_enable,
lpc_pin_irq_enable,
lpc_pin_get,
};
int rt_hw_pin_init(void)

1
bsp/lpc55sxx/Libraries/drivers/drv_pin.c
View File

@ -419,6 +419,7 @@ int rt_hw_pin_init(void)
lpc_pin_ops.pin_attach_irq = lpc_pin_attach_irq;
lpc_pin_ops.pin_detach_irq = lpc_pin_detach_irq;
lpc_pin_ops.pin_irq_enable = lpc_pin_irq_enable;
lpc_pin_ops.pin_get = RT_NULL,
ret = rt_device_pin_register("pin", &lpc_pin_ops, RT_NULL);

1
bsp/ls1bdev/SConstruct
View File

@ -19,6 +19,7 @@ env = Environment(tools = ['mingw'],
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')

2
bsp/ls1cdev/SConstruct
View File

@ -12,7 +12,6 @@ from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
rtconfig.AFLAGS += ' -I' + str(Dir('#'))
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
@ -21,6 +20,7 @@ env = Environment(tools = ['mingw'],
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')

3
bsp/ls1cdev/drivers/drv_gpio.c
View File

@ -122,7 +122,8 @@ const static struct rt_pin_ops _ls1c_pin_ops =
ls1c_pin_attach_irq,
ls1c_pin_detach_irq,
ls1c_pin_irq_enable
ls1c_pin_irq_enable,
RT_NULL,
};

176
bsp/ls2kdev/.config
View File

@ -6,7 +6,7 @@
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_NAME_MAX=30
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=8
@ -14,12 +14,12 @@ CONFIG_RT_ALIGN_SIZE=8
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=2048
CONFIG_IDLE_THREAD_STACK_SIZE=16384
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
@ -65,6 +65,7 @@ CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_CPU_64BIT=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_MIPS64=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -74,7 +75,7 @@ CONFIG_ARCH_MIPS64=y
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_STACK_SIZE=16384
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
@ -93,7 +94,7 @@ CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_THREAD_STACK_SIZE=16384
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
@ -106,23 +107,42 @@ CONFIG_FINSH_ARG_MAX=10
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FILESYSTEMS_MAX=10
CONFIG_DFS_FILESYSTEM_TYPES_MAX=10
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=936
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=9
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=16384
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=5
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
@ -132,6 +152,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
@ -172,22 +193,91 @@ CONFIG_RT_USING_POSIX=y
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
CONFIG_RT_USING_SAL=y
#
# protocol stack implement
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_POSIX is not set
CONFIG_SAL_SOCKETS_NUM=16
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=8
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
CONFIG_RT_LWIP_SNMP=y
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=5
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16384
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=5
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=16384
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32
CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
CONFIG_RT_LWIP_STATS=y
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_LWIP_DEBUG is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
@ -213,7 +303,9 @@ CONFIG_RT_USING_POSIX=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
@ -259,7 +351,7 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
@ -281,6 +373,8 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
#
# security packages
@ -289,6 +383,7 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@ -323,7 +418,9 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
#
# system packages
@ -331,9 +428,15 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
CONFIG_PKG_USING_LWEXT4=y
CONFIG_PKG_LWEXT4_PATH="/packages/system/lwext4"
CONFIG_RT_USING_DFS_LWEXT4=y
CONFIG_PKG_USING_LWEXT4_LATEST_VERSION=y
# CONFIG_PKG_USING_LWEXT4_V100 is not set
CONFIG_PKG_LWEXT4_VER="latest"
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@ -346,6 +449,10 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
#
# peripheral libraries and drivers
@ -383,6 +490,7 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
@ -390,6 +498,13 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
#
# miscellaneous packages
@ -426,36 +541,5 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_ALI_LINKKIT is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
# CONFIG_PKG_USING_ZBAR is not set
# CONFIG_PKG_USING_MCF is not set
# CONFIG_PKG_USING_URPC is not set
# CONFIG_PKG_USING_CRCLIB is not set
CONFIG_SOC_LS2K1000=y

34
bsp/ls2kdev/README.md
View File

@ -84,13 +84,43 @@ Hi, this is RT-Thread!!
msh >
```
## 4. 支持情况
## 4.开机自动启动
在调试阶段，可以利用脚本，在pmon阶段从TFTP服务器上获取固件，然后引导启动。这样可以节省开发配置的时间。具体的步骤如下：
**第一步：**
设置开发板的IP地址，在进入pmon的控制台后，输入`set ifconfig syn0:10.1.1.100`。其中`syn0`后面的ip地址为开发板的ip地址，与存放rt-thread固件的TFTP的服务器IP地址在**同一网段**。
**第二步：**
进入龙芯的Debian系统，用管理员权限进入，输入用户名`root`，密码`loongson`。并且修改boot分区下的boot.cfg文件。增加如下：
```
title TFTPBOOT
kernel tftfp://10.1.1.118/rtthread.elf
args console=tty root=/dev/sda2
initrd (wd0,0)/initrd.img
```
其中`tftfp://10.1.1.118/rtthread.elf`中的`10.1.1.118`为tftp服务器的ip地址。
**第三步：**
电脑开启TFTP服务器，将路径指向存放有ls2k的rt-thread固件的目录下。
以上三步完成之后，重启系统，就可以省略每次都需要进入pmon的输入命令的麻烦，板子上电后，可以自动从系统TFTP服务器中获取固件，然后启动，大大提高调试代码效率。
## 5. 支持情况
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
| UART | 支持 | UART0|
| GPIO | 支持 | - |
| PWM | 支持 | - |
| GMAC | 支持 | 网卡驱动 |
| RTC | 支持 | - |
## 5. 联系人信息
## 6. 联系人信息
维护人：[bernard][4]

4
bsp/ls2kdev/SConstruct
View File

@ -9,15 +9,15 @@ from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
rtconfig.AFLAGS += ' -I' + str(Dir('#')) + ' -I ' + RTT_ROOT + '/libcpu/mips/common/'
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')

10
bsp/ls2kdev/drivers/SConscript
View File

@ -7,4 +7,14 @@ CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
group = group + objs
Return('group')

11
bsp/ls2kdev/drivers/board.c
View File

@ -12,18 +12,26 @@
#include <rthw.h>
#include "mips_regs.h"
#include "mips_fpu.h"
#include "exception.h"
#include "drv_uart.h"
#include "board.h"
#include "ls2k1000.h"
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
WDT_EN = 0x01;
WDT_TIMER = 0x01;
WDT_SET = 0x01;
rt_kprintf("reboot system...\n");
while (1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset cpu);
/**
* this function will shutdown CPU
@ -31,10 +39,13 @@ void rt_hw_cpu_reset(void)
*/
void rt_hw_cpu_shutdown(void)
{
PM1_STS &= 0xffffffff;
PM1_CNT = 0x3c00;
rt_kprintf("shutdown...\n");
while (1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_shutdown, poweroff, shutdown cpu);
/**

4
bsp/ls2kdev/drivers/board.h
View File

@ -15,8 +15,8 @@
extern unsigned char __bss_end;
#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000
#define RT_HW_HEAP_BEGIN KSEG1BASE//(void*)&__bss_end
#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
void rt_hw_board_init(void);

1
bsp/ls2kdev/drivers/clk.c
View File

@ -14,7 +14,6 @@
#include <rtthread.h>
#include "ls2k1000.h"
struct loongson_pll {
rt_uint64_t PLL_SYS_0;
rt_uint64_t PLL_SYS_1;

7
bsp/ls2kdev/drivers/drv_gpio.c
View File

@ -5,8 +5,8 @@
* Change Logs:
* Date Author Notes
* 2015-01-20 Bernard the first version
* 2017-10-20 ZYH add mode open drain and input pull down
* 2020-06-01 Du Huanpeng GPIO driver based on <components/drivers/include/drivers/pin.h>
* 2017-10-20 ZYH add mode open drain and input pull down
* 2020-06-01 Du Huanpeng GPIO driver based on <components/drivers/include/drivers/pin.h>
*/
#include <rtthread.h>
#include <drivers/pin.h>
@ -73,7 +73,7 @@ static int loongson_pin_read(struct rt_device *device, rt_base_t pin)
gpio = (void *)device->user_data;
rt_uint64_t m;
m = gpio->GPIO1_I;
m = gpio->GPIO0_I;
m &= (rt_uint64_t)1 << pin;
rc = !!m;
@ -221,6 +221,7 @@ static struct rt_pin_ops loongson_pin_ops = {
.pin_attach_irq = loongson_pin_attach_irq,
.pin_detach_irq = loongson_pin_detach_irq,
.pin_irq_enable = loongson_pin_irq_enable,
.pin_get = RT_NULL,
};

3
bsp/ls2kdev/drivers/drv_gpio.h
View File

@ -6,7 +6,7 @@
*
* Change Logs:
* Date Author Notes
* 2017-11-24 勤为本 first version
* 2017-11-24 勤为本 first version
* 2018-05-11 zhuangwei add gpio interrupt ops
*/
@ -36,6 +36,5 @@ struct loongson_gpio {
int loongson_pin_init(void);
#endif

4
bsp/ls2kdev/drivers/drv_rtc.c
View File

@ -17,6 +17,8 @@
#include <rtthread.h>
#include "ls2k1000.h"
#ifdef RT_USING_RTC
struct loongson_rtc {
rt_uint32_t sys_toytrim;
rt_uint32_t sys_toywrite0;
@ -176,3 +178,5 @@ int rt_hw_rtc_init(void)
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif /*RT_USING_RTC*/

149
bsp/ls2kdev/drivers/drv_uart.h
View File

@ -15,100 +15,99 @@
#include <rthw.h>
/* UART registers */
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_DAT(base) HWREG8(base + 0x00)
#define UART_IER(base) HWREG8(base + 0x01)
#define UART_IIR(base) HWREG8(base + 0x02)
#define UART_FCR(base) HWREG8(base + 0x02)
#define UART_LCR(base) HWREG8(base + 0x03)
#define UART_MCR(base) HWREG8(base + 0x04)
#define UART_LSR(base) HWREG8(base + 0x05)
#define UART_MSR(base) HWREG8(base + 0x06)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
#define UART_LSB(base) HWREG8(base + 0x00)
#define UART_MSB(base) HWREG8(base + 0x01)
/* interrupt enable register */
#define IER_IRxE 0x1
#define IER_ITxE 0x2
#define IER_ILE 0x4
#define IER_IME 0x8
#define IER_IRxE 0x1
#define IER_ITxE 0x2
#define IER_ILE 0x4
#define IER_IME 0x8
/* interrupt identification register */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
// 线路控制寄存器
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
/* modem control register */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
/* line status register */
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
#endif

26
bsp/ls2kdev/drivers/interrupt.h
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@ -64,22 +64,22 @@
#define LS2K_GPIO2_INT_IRQ (62)
#define LS2K_GPIO3_INT_IRQ (63)
#define MAX_INTR 64
#define LIOINTC0_IRQBASE 0
#define LIOINTC1_IRQBASE 32
#define MAX_INTR (64)
#define LIOINTC0_IRQBASE (0)
#define LIOINTC1_IRQBASE (32)
#define LIOINTC_SHIFT_INTx 4
#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
#define LIOINTC_SHIFT_INTx (4)
#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
#define LIOINTC_INTC_CHIP_START 0x20
#define LIOINTC_INTC_CHIP_START 0x20
#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00)
#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00)
#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
void liointc_set_irq_mode(int irq, int mode);
#endif
#endif

39
bsp/ls2kdev/drivers/ls2k1000.h
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@ -3,14 +3,15 @@
#include <mips.h>
#include "interrupt.h"
#include <rthw.h>
#define APB_BASE CKSEG1ADDR(0xbfe00000)
#define UART0_BASE_ADDR 0xbfe00000
#define UART0_OFF 0x0
#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
#define UART0_BASE_ADDR (0xbfe00000)
#define UART0_OFF (0x0)
#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8)))
#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8)))
#define LIOINTC0_BASE CKSEG1ADDR(0x1fe11400)
#define CORE0_INTISR0 CKSEG1ADDR(0x1fe11040)
@ -18,11 +19,33 @@
#define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440)
#define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048)
#define GPIO_BASE 0xFFFFFFFFBFE10500
#define PLL_SYS_BASE 0xFFFFFFFFBFE10480
#define RTC_BASE 0xFFFFFFFFBFE07820
#define GPIO_BASE (0xFFFFFFFFBFE10500)
#define PLL_SYS_BASE (0xFFFFFFFFBFE10480)
#define RTC_BASE (0xFFFFFFFFBFE07820)
#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420
#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420)
/*
* General PM Configuration Register
*/
#define PMCON_BASE (APB_BASE | (0x7 << 12))
/*
* Power Management1 Configuration Registers
*/
#define PM1_BASE (PMCON_BASE + 0x0C)
#define PM1_STS HWREG32(PM1_BASE)
#define PM1_EN HWREG32(PM1_BASE + 0x04)
#define PM1_CNT HWREG32(PM1_BASE + 0x08)
/*
* Watch Dog Configuration Registers
*/
#define WDT_BASE (PMCON_BASE + 0x30)
#define WDT_EN HWREG32(WDT_BASE)
#define WDT_SET HWREG32(WDT_BASE + 0x04)
#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
void rt_hw_timer_handler(void);
void rt_hw_uart_init(void);

16
bsp/ls2kdev/drivers/net/SConscript Normal file
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@ -0,0 +1,16 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
if GetDepend('RT_USING_LWIP') == False:
SrcRemove(src, 'mii.c')
SrcRemove(src, 'synopGMAC.c')
SrcRemove(src, 'synopGMAC_Dev.c')
SrcRemove(src, 'synopGMAC_plat.c')
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

132
bsp/ls2kdev/drivers/net/mii.c Normal file
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@ -0,0 +1,132 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
*/
#include "mii.h"
static inline unsigned int mii_nway_result (unsigned int negotiated)
{
unsigned int ret;
if (negotiated & LPA_100FULL)
ret = LPA_100FULL;
else if (negotiated & LPA_100BASE4)
ret = LPA_100BASE4;
else if (negotiated & LPA_100HALF)
ret = LPA_100HALF;
else if (negotiated & LPA_10FULL)
ret = LPA_10FULL;
else
ret = LPA_10HALF;
return ret;
}
static int mii_check_gmii_support(struct mii_if_info *mii)
{
int reg;
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
if (reg & BMSR_ESTATEN) {
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS);
if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF))
return 1;
}
return 0;
}
static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
{
struct synopGMACNetworkAdapter * dev = mii->dev;
u32 advert, bmcr, lpa, nego;
u32 advert2 = 0, bmcr2 = 0, lpa2 = 0;
ecmd->supported =
(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
if (mii->supports_gmii)
ecmd->supported |= SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
/* only supports twisted-pair */
ecmd->port = PORT_MII;
/* only supports internal transceiver */
ecmd->transceiver = XCVR_INTERNAL;
/* this isn't fully supported at higher layers */
ecmd->phy_address = mii->phy_id;
ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
if (mii->supports_gmii)
advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
if (advert & ADVERTISE_10HALF)
ecmd->advertising |= ADVERTISED_10baseT_Half;
if (advert & ADVERTISE_10FULL)
ecmd->advertising |= ADVERTISED_10baseT_Full;
if (advert & ADVERTISE_100HALF)
ecmd->advertising |= ADVERTISED_100baseT_Half;
if (advert & ADVERTISE_100FULL)
ecmd->advertising |= ADVERTISED_100baseT_Full;
if (advert2 & ADVERTISE_1000HALF)
ecmd->advertising |= ADVERTISED_1000baseT_Half;
if (advert2 & ADVERTISE_1000FULL)
ecmd->advertising |= ADVERTISED_1000baseT_Full;
bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
if (mii->supports_gmii) {
bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000);
}
if (bmcr & BMCR_ANENABLE) {
ecmd->advertising |= ADVERTISED_Autoneg;
ecmd->autoneg = AUTONEG_ENABLE;
nego = mii_nway_result(advert & lpa);
if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) &
(lpa2 >> 2))
ecmd->speed = SPEED_1000;
else if (nego == LPA_100FULL || nego == LPA_100HALF)
ecmd->speed = SPEED_100;
else
ecmd->speed = SPEED_10;
if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL ||
nego == LPA_10FULL) {
ecmd->duplex = DUPLEX_FULL;
mii->full_duplex = 1;
} else {
ecmd->duplex = DUPLEX_HALF;
mii->full_duplex = 0;
}
} else {
ecmd->autoneg = AUTONEG_DISABLE;
ecmd->speed = ((bmcr & BMCR_SPEED1000 &&
(bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 :
(bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10);
ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
}
/* ignore maxtxpkt, maxrxpkt for now */
return 0;
}
static int mii_link_ok (struct mii_if_info *mii)
{
/* first, a dummy read, needed to latch some MII phys */
mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS)
return 1;
return 0;
}

229
bsp/ls2kdev/drivers/net/mii.h Normal file
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@ -0,0 +1,229 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
*/
#ifndef __MII_H__
#define __MII_H__
/* Generic MII registers. */
#include "synopGMAC_types.h"
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
#define MII_SREVISION 0x16 /* Silicon revision */
#define MII_RESV1 0x17 /* Reserved... */
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
#define MII_PHYADDR 0x19 /* PHY address */
#define MII_RESV2 0x1a /* Reserved... */
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
#define MII_NCONFIG 0x1c /* Network interface config */
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
/* Basic mode status register. */
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
#define BMSR_JCD 0x0002 /* Jabber detected */
#define BMSR_LSTATUS 0x0004 /* Link status */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
#define ADVERTISE_RESV 0x1000 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Indicates what features are advertised by the interface. */
#define ADVERTISED_10baseT_Half (1 << 0)
#define ADVERTISED_10baseT_Full (1 << 1)
#define ADVERTISED_100baseT_Half (1 << 2)
#define ADVERTISED_100baseT_Full (1 << 3)
#define ADVERTISED_1000baseT_Half (1 << 4)
#define ADVERTISED_1000baseT_Full (1 << 5)
#define ADVERTISED_Autoneg (1 << 6)
#define ADVERTISED_TP (1 << 7)
#define ADVERTISED_AUI (1 << 8)
#define ADVERTISED_MII (1 << 9)
#define ADVERTISED_FIBRE (1 << 10)
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
#define ADVERTISED_Pause (1 << 13)
#define ADVERTISED_Asym_Pause (1 << 14)
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
#define LPA_PAUSE_CAP 0x0400 /* Can pause */
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
#define LPA_RESV 0x1000 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
/* 1000BASE-T Control register */
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
/* 1000BASE-T Status register */
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
#define SUPPORTED_10baseT_Half (1 << 0)
#define SUPPORTED_10baseT_Full (1 << 1)
#define SUPPORTED_100baseT_Half (1 << 2)
#define SUPPORTED_100baseT_Full (1 << 3)
#define SUPPORTED_1000baseT_Half (1 << 4)
#define SUPPORTED_1000baseT_Full (1 << 5)
#define SUPPORTED_Autoneg (1 << 6)
#define SUPPORTED_TP (1 << 7)
#define SUPPORTED_AUI (1 << 8)
#define SUPPORTED_MII (1 << 9)
#define SUPPORTED_FIBRE (1 << 10)
#define SUPPORTED_BNC (1 << 11)
#define SUPPORTED_10000baseT_Full (1 << 12)
#define SUPPORTED_Pause (1 << 13)
#define SUPPORTED_Asym_Pause (1 << 14)
/* Which connector port. */
#define PORT_TP 0x00
#define PORT_AUI 0x01
#define PORT_MII 0x02
#define PORT_FIBRE 0x03
#define PORT_BNC 0x04
/* Which transceiver to use. */
#define XCVR_INTERNAL 0x00
#define XCVR_EXTERNAL 0x01
#define XCVR_DUMMY1 0x02
#define XCVR_DUMMY2 0x03
#define XCVR_DUMMY3 0x04
#define AUTONEG_DISABLE 0x00
#define AUTONEG_ENABLE 0x01
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
#define SPEED_2500 2500
#define SPEED_10000 10000
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
struct ethtool_cmd {
u32 cmd;
u32 supported; /* Features this interface supports */
u32 advertising; /* Features this interface advertises */
u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
u8 duplex; /* Duplex, half or full */
u8 port; /* Which connector port */
u8 phy_address;
u8 transceiver; /* Which transceiver to use */
u8 autoneg; /* Enable or disable autonegotiation */
u32 maxtxpkt; /* Tx pkts before generating tx int */
u32 maxrxpkt; /* Rx pkts before generating rx int */
u32 reserved[4];
};
struct mii_if_info {
int phy_id;
int advertising;
int phy_id_mask;
int reg_num_mask;
unsigned int full_duplex : 1; /* is full duplex? */
unsigned int force_media : 1; /* is autoneg. disabled? */
unsigned int supports_gmii : 1; /* are GMII registers supported? */
struct synopGMACNetworkAdapter *dev;
int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location);
void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val);
};
#endif

988
bsp/ls2kdev/drivers/net/synopGMAC.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
* 2020-08-10 lizhirui porting to ls2k
*/
#include <rtthread.h>
#include <rtdef.h>
//#include <lwip/pbuf.h>
#include "synopGMAC.h"
#include "mii.c"
#include "synopGMAC_debug.h"
#define RMII
#define PCI_BASE (0xFE00001800)
#define Buffer_Size 2048
#define MAX_ADDR_LEN 6
#define NAMESIZE 16
#define LS1B_GMAC0_IRQ 34
#define BUS_SIZE_ALIGN(x) ((x+15)&~15)
#define DEFAULT_MAC_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7}
u64 gmac_base = 0;
static u32 GMAC_Power_down;
extern void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) ;
extern s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter) ;
extern int init_phy(synopGMACdevice *gmacdev);
dma_addr_t plat_dma_map_single(void *hwdev, void *ptr, u32 size);
void eth_rx_irq(int irqno, void *param);
static char Rx_Buffer[Buffer_Size];
static char Tx_Buffer[Buffer_Size];
struct pci_header
{
uint16_t VendorID;
uint16_t DeviceID;
uint16_t Command;
uint16_t Status;
uint32_t RevisionID : 8;
uint32_t ClassCode : 24;
uint8_t CachelineSize;
uint8_t LatencyTimer;
uint8_t HeaderType;
uint8_t BIST;
uint32_t BaseAddressRegister[6];
uint32_t CardbusCISPointer;
uint16_t SubsystemVendorID;
uint16_t SubsystemID;
uint32_t ExpansionROMBaseAddress;
uint32_t CapabilitiesPointer : 8;
uint32_t resv1 : 24;
uint32_t resv2;
uint8_t InterruptLine;
uint8_t InterruptPin;
uint8_t Min_Gnt;
uint8_t Max_Lat;
};
struct rt_eth_dev
{
struct eth_device parent;
rt_uint8_t dev_addr[MAX_ADDR_LEN];
char *name;
int iobase;
int state;
int index;
struct rt_timer link_timer;
struct rt_timer rx_poll_timer;
void *priv;
};
static struct rt_eth_dev eth_dev;
static struct rt_semaphore sem_ack, sem_lock;
/**
* This sets up the transmit Descriptor queue in ring or chain mode.
* This function is tightly coupled to the platform and operating system
* Device is interested only after the descriptors are setup. Therefore this function
* is not included in the device driver API. This function should be treated as an
* example code to design the descriptor structures for ring mode or chain mode.
* This function depends on the pcidev structure for allocation consistent dma-able memory in case
* of linux.
* This limitation is due to the fact that linux uses pci structure to allocate a dmable memory
* - Allocates the memory for the descriptors.
* - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor).
* - Initialize the Busy and Next descriptors to first descriptor address.
* - Initialize the last descriptor with the endof ring in case of ring mode.
* - Initialize the descriptors in chain mode.
* @param[in] pointer to synopGMACdevice.
* @param[in] pointer to pci_device structure.
* @param[in] number of descriptor expected in tx descriptor queue.
* @param[in] whether descriptors to be created in RING mode or CHAIN mode.
* \return 0 upon success. Error code upon failure.
* \note This function fails if allocation fails for required number of descriptors in Ring mode,
* but in chain mode
* function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from
* this function
* user should for gmacdev->TxDescCount to see how many descriptors are there in the chain. Should
* continue further
* only if the number of descriptors in the chain meets the requirements
*/
s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice *gmacdev, u32 no_of_desc, u32 desc_mode)
{
s32 i;
DmaDesc *bf1;
DmaDesc *first_desc = NULL;
dma_addr_t dma_addr;
gmacdev->TxDescCount = 0;
first_desc = (DmaDesc *)plat_alloc_consistent_dmaable_memory(gmacdev, sizeof(DmaDesc) * (no_of_desc), &dma_addr);
if (first_desc == NULL)
{
rt_kprintf("Error in Tx Descriptors memory allocation\n");
return -ESYNOPGMACNOMEM;
}
DEBUG_MES("tx_first_desc_addr = %p\n", first_desc);
DEBUG_MES("dmaadr = %p\n", dma_addr);
gmacdev->TxDescCount = no_of_desc;
gmacdev->TxDesc = first_desc;
gmacdev->TxDescDma = dma_addr;
for (i = 0; i < gmacdev->TxDescCount; i++)
{
synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount - 1);
#if SYNOP_TOP_DEBUG
rt_kprintf("\n%02d %08x \n", i, (unsigned int)(gmacdev->TxDesc + i));
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i))->status);
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->length));
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->buffer1));
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->buffer2));
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->data1));
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->data2));
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->dummy1));
rt_kprintf("%08x ", (unsigned int)((gmacdev->TxDesc + i)->dummy2));
#endif
}
gmacdev->TxNext = 0;
gmacdev->TxBusy = 0;
gmacdev->TxNextDesc = gmacdev->TxDesc;
gmacdev->TxBusyDesc = gmacdev->TxDesc;
gmacdev->BusyTxDesc = 0;
return -ESYNOPGMACNOERR;
}
/**
* This sets up the receive Descriptor queue in ring or chain mode.
* This function is tightly coupled to the platform and operating system
* Device is interested only after the descriptors are setup. Therefore this function
* is not included in the device driver API. This function should be treated as an
* example code to design the descriptor structures in ring mode or chain mode.
* This function depends on the pcidev structure for allocation of consistent dma-able memory in
* case of linux.
* This limitation is due to the fact that linux uses pci structure to allocate a dmable memory
* - Allocates the memory for the descriptors.
* - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor).
* - Initialize the Busy and Next descriptors to first descriptor address.
* - Initialize the last descriptor with the endof ring in case of ring mode.
* - Initialize the descriptors in chain mode.
* @param[in] pointer to synopGMACdevice.
* @param[in] pointer to pci_device structure.
* @param[in] number of descriptor expected in rx descriptor queue.
* @param[in] whether descriptors to be created in RING mode or CHAIN mode.
* \return 0 upon success. Error code upon failure.
* \note This function fails if allocation fails for required number of descriptors in Ring mode,
* but in chain mode
* function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from
* this function
* user should for gmacdev->RxDescCount to see how many descriptors are there in the chain. Should
* continue further
* only if the number of descriptors in the chain meets the requirements
*/
s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice *gmacdev, u32 no_of_desc, u32 desc_mode)
{
s32 i;
DmaDesc *bf1;
DmaDesc *first_desc = NULL;
dma_addr_t dma_addr;
gmacdev->RxDescCount = 0;
first_desc = (DmaDesc *)plat_alloc_consistent_dmaable_memory(gmacdev, sizeof(DmaDesc) * no_of_desc, &dma_addr);
if (first_desc == NULL)
{
rt_kprintf("Error in Rx Descriptor Memory allocation in Ring mode\n");
return -ESYNOPGMACNOMEM;
}
DEBUG_MES("rx_first_desc_addr = %p\n", first_desc);
DEBUG_MES("dmaadr = %p\n", dma_addr);
gmacdev->RxDescCount = no_of_desc;
gmacdev->RxDesc = (DmaDesc *)first_desc;
gmacdev->RxDescDma = dma_addr;
for (i = 0; i < gmacdev->RxDescCount; i++)
{
synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount - 1);
}
gmacdev->RxNext = 0;
gmacdev->RxBusy = 0;
gmacdev->RxNextDesc = gmacdev->RxDesc;
gmacdev->RxBusyDesc = gmacdev->RxDesc;
gmacdev->BusyRxDesc = 0;
return -ESYNOPGMACNOERR;
}
void synopGMAC_linux_cable_unplug_function(void *adaptr)
{
s32 data;
synopGMACPciNetworkAdapter *adapter = (synopGMACPciNetworkAdapter *)adaptr;
synopGMACdevice *gmacdev = adapter->synopGMACdev;
struct ethtool_cmd cmd;
if (!mii_link_ok(&adapter->mii))
{
if (gmacdev->LinkState)
rt_kprintf("\r\nNo Link\r\n");
gmacdev->DuplexMode = 0;
gmacdev->Speed = 0;
gmacdev->LoopBackMode = 0;
gmacdev->LinkState = 0;
}
else
{
data = synopGMAC_check_phy_init(adapter);
if (gmacdev->LinkState != data)
{
gmacdev->LinkState = data;
synopGMAC_mac_init(gmacdev);
rt_kprintf("Link is up in %s mode\n", (gmacdev->DuplexMode == FULLDUPLEX) ? "FULL DUPLEX" : "HALF DUPLEX");
if (gmacdev->Speed == SPEED1000)
rt_kprintf("Link is with 1000M Speed \r\n");
if (gmacdev->Speed == SPEED100)
rt_kprintf("Link is with 100M Speed \n");
if (gmacdev->Speed == SPEED10)
rt_kprintf("Link is with 10M Speed \n");
}
}
}
s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter)
{
struct ethtool_cmd cmd;
synopGMACdevice *gmacdev = adapter->synopGMACdev;
if (!mii_link_ok(&adapter->mii))
{
gmacdev->DuplexMode = FULLDUPLEX;
gmacdev->Speed = SPEED100;
return 0;
}
else
{
mii_ethtool_gset(&adapter->mii, &cmd);
gmacdev->DuplexMode = (cmd.duplex == DUPLEX_FULL) ? FULLDUPLEX : HALFDUPLEX ;
if (cmd.speed == SPEED_1000)
gmacdev->Speed = SPEED1000;
else if (cmd.speed == SPEED_100)
gmacdev->Speed = SPEED100;
else
gmacdev->Speed = SPEED10;
}
return gmacdev->Speed | (gmacdev->DuplexMode << 4);
}
static int Mac_change_check(u8 *macaddr0, u8 *macaddr1)
{
int i;
for (i = 0; i < 6; i++)
{
if (macaddr0[i] != macaddr1[i])
return 1;
}
return 0;
}
static rt_err_t eth_init(rt_device_t device)
{
struct eth_device *eth_device = (struct eth_device *)device;
RT_ASSERT(eth_device != RT_NULL);
s32 ijk;
s32 status = 0;
u64 dma_addr;
u32 Mac_changed = 0;
struct pbuf *pbuf;
u8 macaddr[6] = DEFAULT_MAC_ADDRESS;
struct rt_eth_dev *dev = &eth_dev;
struct synopGMACNetworkAdapter *adapter = dev->priv;
synopGMACdevice *gmacdev = (synopGMACdevice *)adapter->synopGMACdev;
synopGMAC_reset(gmacdev);
synopGMAC_attach(gmacdev, (gmac_base + MACBASE), (gmac_base + DMABASE), DEFAULT_PHY_BASE, macaddr);
synopGMAC_read_version(gmacdev);
synopGMAC_set_mdc_clk_div(gmacdev, GmiiCsrClk3);
gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev);
init_phy(adapter->synopGMACdev);
DEBUG_MES("tx desc_queue\n");
synopGMAC_setup_tx_desc_queue(gmacdev, TRANSMIT_DESC_SIZE, RINGMODE);
synopGMAC_init_tx_desc_base(gmacdev);
DEBUG_MES("rx desc_queue\n");
synopGMAC_setup_rx_desc_queue(gmacdev, RECEIVE_DESC_SIZE, RINGMODE);
synopGMAC_init_rx_desc_base(gmacdev);
DEBUG_MES("DmaRxBaseAddr = %08x\n", synopGMACReadReg(gmacdev->DmaBase, DmaRxBaseAddr));
// u32 dmaRx_Base_addr = synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr);
// rt_kprintf("first_desc_addr = 0x%x\n", dmaRx_Base_addr);
#ifdef ENH_DESC_8W
synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2 | DmaDescriptor8Words);
#else
synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip1);
//synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip2);
#endif
synopGMAC_dma_control_init(gmacdev, DmaStoreAndForward | DmaTxSecondFrame | DmaRxThreshCtrl128);
status = synopGMAC_check_phy_init(adapter);
synopGMAC_mac_init(gmacdev);
synopGMAC_pause_control(gmacdev);
#ifdef IPC_OFFLOAD
synopGMAC_enable_rx_chksum_offload(gmacdev);
synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev);
#endif
u64 skb;
do
{
skb = (u64)plat_alloc_memory(RX_BUF_SIZE); //should skb aligned here?
if (skb == RT_NULL)
{
rt_kprintf("ERROR in skb buffer allocation\n");
break;
}
dma_addr = plat_dma_map_single(gmacdev, (void *)skb, RX_BUF_SIZE); //获取 skb 的 dma 地址
status = synopGMAC_set_rx_qptr(gmacdev, dma_addr, RX_BUF_SIZE, (u64)skb, 0, 0, 0);
if (status < 0)
{
rt_kprintf("status < 0!!\n");
plat_free_memory((void *)skb);
}
}
while (status >= 0 && (status < (RECEIVE_DESC_SIZE - 1)));
synopGMAC_clear_interrupt(gmacdev);
synopGMAC_disable_mmc_tx_interrupt(gmacdev, 0xFFFFFFFF);
synopGMAC_disable_mmc_rx_interrupt(gmacdev, 0xFFFFFFFF);
synopGMAC_disable_mmc_ipc_rx_interrupt(gmacdev, 0xFFFFFFFF);
// synopGMAC_disable_interrupt_all(gmacdev);
synopGMAC_enable_interrupt(gmacdev, DmaIntEnable);
synopGMAC_enable_dma_rx(gmacdev);
synopGMAC_enable_dma_tx(gmacdev);
plat_delay(DEFAULT_LOOP_VARIABLE);
synopGMAC_check_phy_init(adapter);
synopGMAC_mac_init(gmacdev);
rt_timer_init(&dev->link_timer, "link_timer",
synopGMAC_linux_cable_unplug_function,
(void *)adapter,
RT_TICK_PER_SECOND,
RT_TIMER_FLAG_PERIODIC);
rt_timer_start(&dev->link_timer);
#ifdef RT_USING_GMAC_INT_MODE
/* installl isr */
DEBUG_MES("%s\n", __FUNCTION__);
rt_hw_interrupt_install(LS1C_MAC_IRQ, eth_rx_irq, RT_NULL, "e0_isr");
rt_hw_interrupt_umask(LS1C_MAC_IRQ);
#else
rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
eth_rx_irq,
(void *)adapter,
1,
RT_TIMER_FLAG_PERIODIC);
rt_timer_start(&dev->rx_poll_timer);
#endif /*RT_USING_GMAC_INT_MODE*/
return RT_EOK;
}
static rt_err_t eth_open(rt_device_t dev, rt_uint16_t oflag)
{
rt_kprintf("eth_open!!\n");
return RT_EOK;
}
static rt_err_t eth_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t eth_control(rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case NIOCTL_GADDR:
if (args) rt_memcpy(args, eth_dev.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
return RT_EOK;
}
rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
{
/* lock eth device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
DEBUG_MES("in %s\n", __FUNCTION__);
s32 status;
u64 pbuf;
u64 dma_addr;
u32 offload_needed = 0;
u32 index;
DmaDesc *dpr;
struct rt_eth_dev *dev = (struct rt_eth_dev *) device;
struct synopGMACNetworkAdapter *adapter;
synopGMACdevice *gmacdev;
adapter = (struct synopGMACNetworkAdapter *) dev->priv;
if (adapter == NULL)
return -1;
gmacdev = (synopGMACdevice *) adapter->synopGMACdev;
if (gmacdev == NULL)
return -1;
if (!synopGMAC_is_desc_owned_by_dma(gmacdev->TxNextDesc))
{
pbuf = (u64)plat_alloc_memory(p->tot_len);
//pbuf = (u32)pbuf_alloc(PBUF_LINK, p->len, PBUF_RAM);
if (pbuf == 0)
{
rt_kprintf("===error in alloc bf1\n");
return -1;
}
DEBUG_MES("p->len = %d\n", p->len);
pbuf_copy_partial(p, (void *)pbuf, p->tot_len, 0);
dma_addr = plat_dma_map_single(gmacdev, (void *)pbuf, p->tot_len);
status = synopGMAC_set_tx_qptr(gmacdev, dma_addr, p->tot_len, pbuf, 0, 0, 0, offload_needed, &index, dpr);
if (status < 0)
{
rt_kprintf("%s No More Free Tx Descriptors\n", __FUNCTION__);
plat_free_memory((void *)pbuf);
return -16;
}
}
synopGMAC_resume_dma_tx(gmacdev);
s32 desc_index;
u64 data1, data2;
u32 dma_addr1, dma_addr2;
u32 length1, length2;
#ifdef ENH_DESC_8W
u32 ext_status;
u16 time_stamp_higher;
u32 time_stamp_high;
u32 time_stamp_low;
#endif
do
{
#ifdef ENH_DESC_8W
desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2, &ext_status, &time_stamp_high, &time_stamp_low);
synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher);
#else
desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &dma_addr2, &length2, &data2);
#endif
if (desc_index >= 0 && data1 != 0)
{
#ifdef IPC_OFFLOAD
if (synopGMAC_is_tx_ipv4header_checksum_error(gmacdev, status))
{
rt_kprintf("Harware Failed to Insert IPV4 Header Checksum\n");
}
if (synopGMAC_is_tx_payload_checksum_error(gmacdev, status))
{
rt_kprintf("Harware Failed to Insert Payload Checksum\n");
}
#endif
plat_free_memory((void *)(data1)); //sw: data1 = buffer1
if (synopGMAC_is_desc_valid(status))
{
adapter->synopGMACNetStats.tx_bytes += length1;
adapter->synopGMACNetStats.tx_packets++;
}
else
{
adapter->synopGMACNetStats.tx_errors++;
adapter->synopGMACNetStats.tx_aborted_errors += synopGMAC_is_tx_aborted(status);
adapter->synopGMACNetStats.tx_carrier_errors += synopGMAC_is_tx_carrier_error(status);
}
}
adapter->synopGMACNetStats.collisions += synopGMAC_get_tx_collision_count(status);
}
while (desc_index >= 0);
/* unlock eth device */
rt_sem_release(&sem_lock);
// rt_kprintf("output %d bytes\n", p->len);
u32 test_data;
test_data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus);
//rt_kprintf("dma_status = 0x%08x\n",test_data);
return RT_EOK;
}
struct pbuf *rt_eth_rx(rt_device_t device)
{
DEBUG_MES("%s : \n", __FUNCTION__);
struct rt_eth_dev *dev = &eth_dev;
struct synopGMACNetworkAdapter *adapter;
synopGMACdevice *gmacdev;
// struct PmonInet * pinetdev;
s32 desc_index;
int i;
char *ptr;
u32 bf1;
u64 data1;
u64 data2;
u32 len;
u32 status;
u32 dma_addr1;
u32 dma_addr2;
struct pbuf *pbuf = RT_NULL;
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
adapter = (struct synopGMACNetworkAdapter *) dev->priv;
if (adapter == NULL)
{
rt_kprintf("%S : Unknown Device !!\n", __FUNCTION__);
return NULL;
}
gmacdev = (synopGMACdevice *) adapter->synopGMACdev;
if (gmacdev == NULL)
{
rt_kprintf("%s : GMAC device structure is missing\n", __FUNCTION__);
return NULL;
}
/*Handle the Receive Descriptors*/
desc_index = synopGMAC_get_rx_qptr(gmacdev, &status, &dma_addr1, NULL, &data1, &dma_addr2, NULL, &data2);
if(((u32)desc_index >= RECEIVE_DESC_SIZE) && (desc_index != -1))
{
rt_kprintf("host receive descriptor address pointer = 0x%08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxCurrDesc));
rt_kprintf("host receive buffer = 0x%08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxCurrAddr));
rt_kprintf("desc_index error!!!!,tick = %d\n",rt_tick_get());
while(1);
}
if (desc_index >= 0 && data1 != 0)
{
DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n", desc_index, dma_addr1, status);
if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK)
{
dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE);
len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes
pbuf = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n");
rt_memcpy(pbuf->payload, (char *)data1, len);
DEBUG_MES("==get pkg len: %d\n", len);
}
else
{
rt_kprintf("s: %08x\n", status);
adapter->synopGMACNetStats.rx_errors++;
adapter->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status);
adapter->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status);
adapter->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status);
adapter->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status);
}
desc_index = synopGMAC_set_rx_qptr(gmacdev, dma_addr1, RX_BUF_SIZE, (u64)data1, 0, 0, 0);
if (desc_index < 0)
{
#if SYNOP_RX_DEBUG
rt_kprintf("Cannot set Rx Descriptor for data1 %08x\n", (u32)data1);
#endif
plat_free_memory((void *)data1);
}
}
rt_sem_release(&sem_lock);
DEBUG_MES("%s : before return \n", __FUNCTION__);
return pbuf;
}
static int rtl88e1111_config_init(synopGMACdevice *gmacdev)
{
int retval, err;
u16 data;
DEBUG_MES("in %s\n", __FUNCTION__);
synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, &data);
data = data | 0x82;
err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, data);
synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, &data);
data = data | 0x8000;
err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, data);
#if SYNOP_PHY_LOOPBACK
synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, &data);
data = data | 0x70;
data = data & 0xffdf;
err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x14, data);
data = 0x8000;
err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, data);
data = 0x5140;
err = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x00, data);
#endif
if (err < 0)
return err;
return 0;
}
int init_phy(synopGMACdevice *gmacdev)
{
u16 data;
synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 2, &data);
/*set 88e1111 clock phase delay*/
if (data == 0x141)
rtl88e1111_config_init(gmacdev);
#if defined (RMII)
else if (data == 0x8201)
{
//RTL8201
data = 0x400; // set RMII mode
synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x19, data);
synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x19, &data);
TR("phy reg25 is %0x \n", data);
data = 0x3100; //set 100M speed
synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x0, data);
}
else if (data == 0x0180 || data == 0x0181)
{
//DM9161
synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x10, &data);
data |= (1 << 8); //set RMII mode
synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x10, data); //set RMII mode
synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x10, &data);
TR("phy reg16 is 0x%0x \n", data);
// synopGMAC_read_phy_reg(gmacdev->MacBase,gmacdev->PhyBase,0x0,&data);
// data &= ~(1<<10);
data = 0x3100; //set auto-
//data = 0x0100; //set 10M speed
synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, 0x0, data);
}
#endif
return 0;
}
u32 synopGMAC_wakeup_filter_config3[] =
{
0x00000000,
0x000000FF,
0x00000000,
0x00000000,
0x00000100,
0x00003200,
0x7eED0000,
0x00000000
};
static void synopGMAC_linux_powerdown_mac(synopGMACdevice *gmacdev)
{
rt_kprintf("Put the GMAC to power down mode..\n");
GMAC_Power_down = 1;
synopGMAC_disable_dma_tx(gmacdev);
plat_delay(10000);
synopGMAC_tx_disable(gmacdev);
synopGMAC_rx_disable(gmacdev);
plat_delay(10000);
synopGMAC_disable_dma_rx(gmacdev);
synopGMAC_magic_packet_enable(gmacdev);
synopGMAC_write_wakeup_frame_register(gmacdev, synopGMAC_wakeup_filter_config3);
synopGMAC_wakeup_frame_enable(gmacdev);
synopGMAC_rx_enable(gmacdev);
synopGMAC_pmt_int_enable(gmacdev);
synopGMAC_power_down_enable(gmacdev);
return;
}
static void synopGMAC_linux_powerup_mac(synopGMACdevice *gmacdev)
{
GMAC_Power_down = 0;
if (synopGMAC_is_magic_packet_received(gmacdev))
rt_kprintf("GMAC wokeup due to Magic Pkt Received\n");
if (synopGMAC_is_wakeup_frame_received(gmacdev))
rt_kprintf("GMAC wokeup due to Wakeup Frame Received\n");
synopGMAC_pmt_int_disable(gmacdev);
synopGMAC_rx_enable(gmacdev);
synopGMAC_enable_dma_rx(gmacdev);
synopGMAC_tx_enable(gmacdev);
synopGMAC_enable_dma_tx(gmacdev);
return;
}
static int mdio_read(synopGMACPciNetworkAdapter *adapter, int addr, int reg)
{
synopGMACdevice *gmacdev;
u16 data;
gmacdev = adapter->synopGMACdev;
synopGMAC_read_phy_reg(gmacdev->MacBase, addr, reg, &data);
return data;
}
static void mdio_write(synopGMACPciNetworkAdapter *adapter, int addr, int reg, int data)
{
synopGMACdevice *gmacdev;
gmacdev = adapter->synopGMACdev;
synopGMAC_write_phy_reg(gmacdev->MacBase, addr, reg, data);
}
void eth_rx_irq(int irqno, void *param)
{
struct rt_eth_dev *dev = &eth_dev;
struct synopGMACNetworkAdapter *adapter = dev->priv;
//DEBUG_MES("in irq!!\n");
#ifdef RT_USING_GMAC_INT_MODE
int i ;
for (i = 0; i < 7200; i++)
;
#endif /*RT_USING_GMAC_INT_MODE*/
synopGMACdevice *gmacdev = (synopGMACdevice *)adapter->synopGMACdev;
u32 interrupt, dma_status_reg;
s32 status;
u32 dma_addr;
//rt_kprintf("irq i = %d\n", i++);
dma_status_reg = synopGMACReadReg(gmacdev->DmaBase, DmaStatus);
if (dma_status_reg == 0)
{
rt_kprintf("dma_status ==0 \n");
return;
}
//rt_kprintf("dma_status_reg is 0x%x\n", dma_status_reg);
u32 gmacstatus;
synopGMAC_disable_interrupt_all(gmacdev);
gmacstatus = synopGMACReadReg(gmacdev->MacBase, GmacStatus);
if (dma_status_reg & GmacPmtIntr)
{
rt_kprintf("%s:: Interrupt due to PMT module\n", __FUNCTION__);
//synopGMAC_linux_powerup_mac(gmacdev);
}
if (dma_status_reg & GmacMmcIntr)
{
rt_kprintf("%s:: Interrupt due to MMC module\n", __FUNCTION__);
DEBUG_MES("%s:: synopGMAC_rx_int_status = %08x\n", __FUNCTION__, synopGMAC_read_mmc_rx_int_status(gmacdev));
DEBUG_MES("%s:: synopGMAC_tx_int_status = %08x\n", __FUNCTION__, synopGMAC_read_mmc_tx_int_status(gmacdev));
}
if (dma_status_reg & GmacLineIntfIntr)
{
//rt_kprintf("%s:: Interrupt due to GMAC LINE module\n", __FUNCTION__);
}
interrupt = synopGMAC_get_interrupt_type(gmacdev);
//rt_kprintf("%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt);
if (interrupt & synopGMACDmaError)
{
u8 mac_addr0[6];
rt_kprintf("%s::Fatal Bus Error Inetrrupt Seen\n", __FUNCTION__);
memcpy(mac_addr0, dev->dev_addr, 6);
synopGMAC_disable_dma_tx(gmacdev);
synopGMAC_disable_dma_rx(gmacdev);
synopGMAC_take_desc_ownership_tx(gmacdev);
synopGMAC_take_desc_ownership_rx(gmacdev);
synopGMAC_init_tx_rx_desc_queue(gmacdev);
synopGMAC_reset(gmacdev);
synopGMAC_set_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr0);
synopGMAC_dma_bus_mode_init(gmacdev, DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip1);
synopGMAC_dma_control_init(gmacdev, DmaStoreAndForward);
synopGMAC_init_rx_desc_base(gmacdev);
synopGMAC_init_tx_desc_base(gmacdev);
synopGMAC_mac_init(gmacdev);
synopGMAC_enable_dma_rx(gmacdev);
synopGMAC_enable_dma_tx(gmacdev);
}
if (interrupt & synopGMACDmaRxNormal)
{
//DEBUG_MES("%s:: Rx Normal \n", __FUNCTION__);
//synop_handle_received_data(netdev);
eth_device_ready(&eth_dev.parent);
}
if (interrupt & synopGMACDmaRxAbnormal)
{
//rt_kprintf("%s::Abnormal Rx Interrupt Seen\n",__FUNCTION__);
if (GMAC_Power_down == 0)
{
adapter->synopGMACNetStats.rx_over_errors++;
synopGMACWriteReg(gmacdev->DmaBase, DmaStatus, 0x80);
synopGMAC_resume_dma_rx(gmacdev);
}
}
if (interrupt & synopGMACDmaRxStopped)
{
rt_kprintf("%s::Receiver stopped seeing Rx interrupts\n", __FUNCTION__); //Receiver gone in to stopped state
}
if (interrupt & synopGMACDmaTxNormal)
{
DEBUG_MES("%s::Finished Normal Transmission \n", __FUNCTION__);
// synop_handle_transmit_over(netdev);
}
if (interrupt & synopGMACDmaTxAbnormal)
{
rt_kprintf("%s::Abnormal Tx Interrupt Seen\n", __FUNCTION__);
}
if (interrupt & synopGMACDmaTxStopped)
{
TR("%s::Transmitter stopped sending the packets\n", __FUNCTION__);
if (GMAC_Power_down == 0) // If Mac is not in powerdown
{
synopGMAC_disable_dma_tx(gmacdev);
synopGMAC_take_desc_ownership_tx(gmacdev);
synopGMAC_enable_dma_tx(gmacdev);
// netif_wake_queue(netdev);
TR("%s::Transmission Resumed\n", __FUNCTION__);
}
}
/* Enable the interrrupt before returning from ISR*/
synopGMAC_enable_interrupt(gmacdev, DmaIntEnable);
return;
}
int rt_hw_eth_init(void)
{
struct pci_header *p = (struct pci_header *)(0x9000000000000000 | PCI_BASE);
gmac_base = (0x9000000000000000 | ((p->BaseAddressRegister[0]) & 0xffffff00));
struct synopGMACNetworkAdapter *synopGMACadapter;
static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
int index;
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
memset(&eth_dev, 0, sizeof(eth_dev));
synopGMACadapter = (struct synopGMACNetworkAdapter *)plat_alloc_memory(sizeof(struct synopGMACNetworkAdapter));
if (!synopGMACadapter)
{
rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__);
}
memset((char *)synopGMACadapter, 0, sizeof(struct synopGMACNetworkAdapter));
synopGMACadapter->synopGMACdev = NULL;
synopGMACadapter->synopGMACdev = (synopGMACdevice *) plat_alloc_memory(sizeof(synopGMACdevice));
if (!synopGMACadapter->synopGMACdev)
{
rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__);
}
memset((char *)synopGMACadapter->synopGMACdev, 0, sizeof(synopGMACdevice));
/*
* Attach the device to MAC struct This will configure all the required base addresses
* such as Mac base, configuration base, phy base address(out of 32 possible phys)
* */
synopGMAC_attach(synopGMACadapter->synopGMACdev, (gmac_base + MACBASE), gmac_base + DMABASE, DEFAULT_PHY_BASE, mac_addr0);
init_phy(synopGMACadapter->synopGMACdev);
synopGMAC_reset(synopGMACadapter->synopGMACdev);
/* MII setup */
synopGMACadapter->mii.phy_id_mask = 0x1F;
synopGMACadapter->mii.reg_num_mask = 0x1F;
synopGMACadapter->mii.dev = synopGMACadapter;
synopGMACadapter->mii.mdio_read = mdio_read;
synopGMACadapter->mii.mdio_write = mdio_write;
synopGMACadapter->mii.phy_id = synopGMACadapter->synopGMACdev->PhyBase;
synopGMACadapter->mii.supports_gmii = mii_check_gmii_support(&synopGMACadapter->mii);
eth_dev.iobase = gmac_base;
eth_dev.name = "e0";
eth_dev.priv = synopGMACadapter;
eth_dev.dev_addr[0] = mac_addr0[0];
eth_dev.dev_addr[1] = mac_addr0[1];
eth_dev.dev_addr[2] = mac_addr0[2];
eth_dev.dev_addr[3] = mac_addr0[3];
eth_dev.dev_addr[4] = mac_addr0[4];
eth_dev.dev_addr[5] = mac_addr0[5];
eth_dev.parent.parent.type = RT_Device_Class_NetIf;
eth_dev.parent.parent.init = eth_init;
eth_dev.parent.parent.open = eth_open;
eth_dev.parent.parent.close = eth_close;
eth_dev.parent.parent.read = eth_read;
eth_dev.parent.parent.write = eth_write;
eth_dev.parent.parent.control = eth_control;
eth_dev.parent.parent.user_data = RT_NULL;
eth_dev.parent.eth_tx = rt_eth_tx;
eth_dev.parent.eth_rx = rt_eth_rx;
eth_device_init(&(eth_dev.parent), "e0");
eth_device_linkchange(&eth_dev.parent, RT_TRUE); //linkup the e0 for lwip to check
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_eth_init);

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
*/
#ifndef __SYNOPGMAC__H
#define __SYNOPGMAC__H
#include "synopGMAC_network_interface.h"
#include "synopGMAC_Host.h"
#include "synopGMAC_Dev.h"
#include "synopGMAC_plat.h"
#include "mii.h"
#include "synopGMAC_types.h"
int rt_hw_eth_init(void);
#endif /*__SYNOPGMAC__H*/

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1717
bsp/ls2kdev/drivers/net/synopGMAC_Dev.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
*/
#ifndef SYNOP_GMAC_HOST_H
#define SYNOP_GMAC_HOST_H 1
#include "synopGMAC_plat.h"
#include "synopGMAC_Dev.h"
#include "mii.h"
struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};
typedef struct synopGMACNetworkAdapter{
/*Device Dependent Data structur*/
synopGMACdevice * synopGMACdev;
struct net_device_stats synopGMACNetStats;
struct mii_if_info mii;
} synopGMACPciNetworkAdapter;
#endif

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
*/
#ifndef __DEBUG_H__
#define __DEBUG_H__
//#define GMAC_DEBUG
#include <rtthread.h>
#ifdef GMAC_DEBUG
#define DEBUG_MES rt_kprintf
#else
#define DEBUG_MES(...)
#endif
#endif /*__DEBUG_H__*/

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bsp/ls2kdev/drivers/net/synopGMAC_network_interface.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
*/
#ifndef SYNOP_GMAC_NETWORK_INTERFACE_H
#define SYNOP_GMAC_NETWORK_INTERFACE_H 1
#include <lwip/sys.h>
#include <netif/ethernetif.h>
#include "synopGMAC_plat.h"
#include "synopGMAC_Host.h"
#include "synopGMAC_Dev.h"
#define NET_IF_TIMEOUT (10*HZ)
#define CHECK_TIME (HZ)
s32 synopGMAC_init_network_interface(char* xname,u64 synopGMACMappedAddr);
void synopGMAC_exit_network_interface(void);
s32 synopGMAC_linux_open(struct eth_device *);
s32 synopGMAC_linux_close(struct eth_device *);
struct net_device_stats * synopGMAC_linux_get_stats(struct synopGMACNetworkAdapter *);
s32 synopGMAC_test(synopGMACdevice * gmacdev_0,synopGMACdevice * gmacdev_1);
void dumpreg(u64 );
void dumpphyreg();
/*
* gethex(vp,p,n)
* convert n hex digits from p to binary, result in vp,
* rtn 1 on success
*/
static int gethex(u8 *vp, char *p, int n)
{
u8 v;
int digit;
for (v = 0; n > 0; n--) {
if (*p == 0)
return (0);
if (*p >= '0' && *p <= '9')
digit = *p - '0';
else if (*p >= 'a' && *p <= 'f')
digit = *p - 'a' + 10;
else if (*p >= 'A' && *p <= 'F')
digit = *p - 'A' + 10;
else
return (0);
v <<= 4;
v |= digit;
p++;
}
*vp = v;
return (1);
}
#endif /* End of file */

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
* 2020-08-10 lizhirui porting to ls2k
*/
#include "synopGMAC_plat.h"
#include "synopGMAC_Dev.h"
#include <rthw.h>
#include <rtthread.h>
void flush_cache(unsigned long start_addr, unsigned long size)
{
/*r4k_dcache_wback_inv(start_addr,size);
//rt_kprintf("flush_cache:start_addr = 0x%p,size = 0x%p",start_addr,size);
unsigned long new_addr = start_addr - CACHED_MEMORY_ADDR + UNCACHED_MEMORY_ADDR;
rt_memcpy(new_addr,start_addr,size);
if(rt_memcmp(start_addr,new_addr,size) != 0)
{
rt_kprintf("flush_cache:data isn't matched!\n");
while(1);
}
else
{
//rt_kprintf("flush_cache:data is matched!\n");
}*/
}
//convert virtual address to physical address
dma_addr_t __attribute__((weak)) gmac_dmamap(unsigned long va,u32 size)
{
return VA_TO_PA (va);
//return UNCACHED_TO_PHYS(va);
}
/**
* This is a wrapper function for Memory allocation routine. In linux Kernel
* it it kmalloc function
* @param[in] bytes in bytes to allocate
*/
void *plat_alloc_memory(u32 bytes)
{
//return (void*)malloc((size_t)bytes, M_DEVBUF, M_DONTWAIT);
void *buf = (void*)rt_malloc((u32)bytes);
flush_cache((unsigned long)buf, bytes);
return buf;
}
/**
* This is a wrapper function for consistent dma-able Memory allocation routine.
* In linux Kernel, it depends on pci dev structure
* @param[in] bytes in bytes to allocate
*/
//allocate a space aligned to 16-byte boundary without cache
void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr)
{
void *buf;
buf = (void*)rt_malloc((u32)(size + 16));
//CPU_IOFlushDCache( buf,size, SYNC_W);
unsigned long i = (unsigned long)buf;
// rt_kprintf("size = %d\n", size);
// rt_kprintf("bufaddr = %p\n", buf);
// rt_kprintf("i%%16 == %d\n", i%16);
if(i % 16 == 8){
i += 8;
}
else if(i % 16 == 4){
i += 12;
}
else if(i % 16 == 12){
i += 4;
}
flush_cache(i, size);
*addr = gmac_dmamap(i, size);
buf = (unsigned char *)CACHED_TO_UNCACHED(i);
//rt_kprintf("bufaddr = %p\n", buf);
return buf;
}
/**
* This is a wrapper function for freeing consistent dma-able Memory.
* In linux Kernel, it depends on pci dev structure
* @param[in] bytes in bytes to allocate
*/
//void plat_free_consistent_dmaable_memory(void * addr)
void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u64 dma_addr)
{
rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr)));
return;
}
/**
* This is a wrapper function for Memory free routine. In linux Kernel
* it it kfree function
* @param[in] buffer pointer to be freed
*/
void plat_free_memory(void *buffer)
{
rt_free(buffer);
return ;
}
//convert virtual address to physical address and flush cache
dma_addr_t plat_dma_map_single(void *hwdev,void *ptr,u32 size)
{
unsigned long addr = (unsigned long) ptr;
//CPU_IOFlushDCache(addr,size, direction);
flush_cache(addr, size);
return gmac_dmamap(addr, size);
}
/**
* This is a wrapper function for platform dependent delay
* Take care while passing the argument to this function
* @param[in] buffer pointer to be freed
*/
void plat_delay(u32 delay)
{
while (delay--);
return;
}

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bsp/ls2kdev/drivers/net/synopGMAC_plat.h Normal file
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@ -0,0 +1,242 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
* 2020-08-10 lizhirui porting to ls2k
*/
#ifndef SYNOP_GMAC_PLAT_H
#define SYNOP_GMAC_PLAT_H 1
/* sw
#include <linux/kernel.h>
#include <asm/io.h>
#include <linux/gfp.h>
#include <linux/slab.h>
#include <linux/pci.h>
*/
#include "synopGMAC_types.h"
#include "synopGMAC_debug.h"
//#include "mii.h"
//#include "GMAC_Pmon.h"
//#include "synopGMAC_Host.h"
#include <rtthread.h>
#include <stdint.h>
#include "mips_addrspace.h"
//sw: copy the type define into here
#define IOCTL_READ_REGISTER SIOCDEVPRIVATE+1
#define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2
#define IOCTL_READ_IPSTRUCT SIOCDEVPRIVATE+3
#define IOCTL_READ_RXDESC SIOCDEVPRIVATE+4
#define IOCTL_READ_TXDESC SIOCDEVPRIVATE+5
#define IOCTL_POWER_DOWN SIOCDEVPRIVATE+6
#define SYNOP_GMAC0 1
typedef int bool;
//typedef unsigned long dma_addr_t;
#define KUSEG_ADDR 0x0
#define CACHED_MEMORY_ADDR KSEG0BASE
#define UNCACHED_MEMORY_ADDR KSEG0BASE
#define KSEG2_ADDR KSEG2BASE
#define MAX_MEM_ADDR KSEG3BASE
#define RESERVED_ADDR KSEG3BASE
#define CACHED_TO_PHYS(x) ((uint64_t)(x) - CACHED_MEMORY_ADDR)
#define PHYS_TO_CACHED(x) ((uint64_t)(x) + CACHED_MEMORY_ADDR)
#define UNCACHED_TO_PHYS(x) ((uint64_t)(x) - UNCACHED_MEMORY_ADDR)
#define PHYS_TO_UNCACHED(x) ((uint64_t)(x) + UNCACHED_MEMORY_ADDR)
#define VA_TO_CINDEX(x) (PHYS_TO_CACHED(UNCACHED_TO_PHYS(x)))
#define CACHED_TO_UNCACHED(x) (PHYS_TO_UNCACHED(CACHED_TO_PHYS(x)))
#define VA_TO_PA(x) CACHED_TO_PHYS(x)
/* sw
#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
#ifdef DEBUG
#undef TR
# define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
#else
# define TR(fmt, args...) // not debugging: nothing
#endif
*/
/*
#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)
*/
/*
#ifdef DEBUG
#undef TR
# define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#else
//# define TR(fmt, args...) // not debugging: nothing
#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#endif
*/
//sw: nothing to display
#define TR0(fmt, args...) //rt_kprintf(fmt, ##args)
#define TR(fmt, args...) //rt_kprintf(fmt, ##args)
//typedef int bool;
enum synopGMAC_boolean
{
false = 0,
true = 1
};
#define DEFAULT_DELAY_VARIABLE 10
#define DEFAULT_LOOP_VARIABLE 10000
/* There are platform related endian conversions
*
*/
#define LE32_TO_CPU __le32_to_cpu
#define BE32_TO_CPU __be32_to_cpu
#define CPU_TO_LE32 __cpu_to_le32
/* Error Codes */
#define ESYNOPGMACNOERR 0
#define ESYNOPGMACNOMEM 1
#define ESYNOPGMACPHYERR 2
#define ESYNOPGMACBUSY 3
struct Network_interface_data
{
u32 unit;
u64 addr;
u32 data;
};
/**
* These are the wrapper function prototypes for OS/platform related routines
*/
void * plat_alloc_memory(u32 );
void plat_free_memory(void *);
//void * plat_alloc_consistent_dmaable_memory(struct pci_dev *, u32, u32 *);
//void plat_free_consistent_dmaable_memory (struct pci_dev *, u32, void *, u32);
void plat_delay(u32);
/**
* The Low level function to read register contents from Hardware.
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* \return Returns the register contents
*/
static u32 synopGMACReadReg(u64 RegBase, u32 RegOffset)
{
u64 addr;
u32 data;
addr = RegBase + (u32)RegOffset;
data = *(volatile u32 *)addr;
#if SYNOP_REG_DEBUG
TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
#endif
// rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data );
return data;
}
/**
* The Low level function to write to a register in Hardware.
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Data to be written
* \return void
*/
static void synopGMACWriteReg(u64 RegBase, u32 RegOffset, u32 RegData )
{
u64 addr;
addr = RegBase + (u32)RegOffset;
// rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
#if SYNOP_REG_DEBUG
TR("%s RegBase = 0x%p RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
#endif
*(volatile u32 *)addr = RegData;
/*if(addr == 0xbfe1100c)
DEBUG_MES("regdata = %08x\n", RegData);*/
return;
}
/**
* The Low level function to set bits of a register in Hardware.
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to set bits to logical 1
* \return void
*/
static void synopGMACSetBits(u64 RegBase, u32 RegOffset, u32 BitPos)
{
//u64 addr = (u64)RegBase + (u64)RegOffset;
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data |= BitPos;
synopGMACWriteReg(RegBase, RegOffset, data);
// writel(data,(void *)addr);
#if SYNOP_REG_DEBUG
TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
#endif
return;
}
/**
* The Low level function to clear bits of a register in Hardware.
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to clear bits to logical 0
* \return void
*/
static void synopGMACClearBits(u64 RegBase, u32 RegOffset, u32 BitPos)
{
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data &= (~BitPos);
synopGMACWriteReg(RegBase, RegOffset, data);
#if SYNOP_REG_DEBUG
TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
#endif
return;
}
/**
* The Low level function to Check the setting of the bits.
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to set bits to logical 1
* \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument.
*
*/
static bool synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos)
{
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data &= BitPos;
if(data)
{
return true;
}
else
{
return false;
}
}
#endif

23
bsp/ls2kdev/drivers/net/synopGMAC_types.h Normal file
View File

@ -0,0 +1,23 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-08-24 chinesebear first version
*/
#ifndef __TYPES__H
#define __TYPES__H
typedef unsigned char uint8_t;
typedef unsigned long long u64;
typedef unsigned int u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef signed int s32;
typedef u32 dma_addr_t;
#endif /*__TYPES__H*/

17
bsp/ls2kdev/ls2k_ram.lds
View File

@ -78,6 +78,23 @@ SECTIONS
*(.sdata.*)
}
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
.stack :
{
. = ALIGN(8);

96
bsp/ls2kdev/rtconfig.h
View File

@ -6,16 +6,16 @@
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_NAME_MAX 30
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 2048
#define IDLE_THREAD_STACK_SIZE 16384
#define RT_DEBUG
/* Inter-Thread communication */
@ -39,13 +39,14 @@
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40003
#define ARCH_CPU_64BIT
#define ARCH_MIPS64
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_STACK_SIZE 16384
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
@ -60,7 +61,7 @@
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 16384
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
@ -70,15 +71,30 @@
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FILESYSTEMS_MAX 10
#define DFS_FILESYSTEM_TYPES_MAX 10
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 936
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 9
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 16384
#define RT_SYSTEM_WORKQUEUE_PRIORITY 5
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
@ -96,12 +112,69 @@
/* Socket abstraction layer */
#define RT_USING_SAL
/* protocol stack implement */
#define SAL_USING_LWIP
#define SAL_SOCKETS_NUM 16
/* Network interface device */
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
#define RT_LWIP_MEM_ALIGNMENT 8
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_SNMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 5
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
#define RT_LWIP_TCPTHREAD_STACKSIZE 16384
#define RT_LWIP_ETHTHREAD_PRIORITY 5
#define RT_LWIP_ETHTHREAD_STACKSIZE 16384
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_STATS
#define RT_LWIP_USING_PING
/* AT commands */
@ -145,6 +218,9 @@
/* system packages */
#define PKG_USING_LWEXT4
#define RT_USING_DFS_LWEXT4
#define PKG_USING_LWEXT4_LATEST_VERSION
/* peripheral libraries and drivers */
@ -154,12 +230,6 @@
/* samples: kernel and components samples */
/* Privated Packages of RealThread */
/* Network Utilities */
#define SOC_LS2K1000
#endif

1
bsp/ls2kdev/rtconfig.py
View File

@ -31,6 +31,7 @@ BUILD = 'debug'
PREFIX = 'mips-sde-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'

1
bsp/mm32l3xx/drivers/drv_gpio.c
View File

@ -409,6 +409,7 @@ const static struct rt_pin_ops _mm32_pin_ops =
mm32_pin_attach_irq,
mm32_pin_detach_irq,
mm32_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

9
bsp/nrf5x/libraries/drivers/SConscript
View File

@ -22,10 +22,19 @@ if GetDepend(['BSP_USING_SPI']):
if GetDepend(['BSP_USING_GPIO']):
src += ['drv_gpio.c']
if GetDepend(['BSP_USING_SAADC']):
src += ['drv_adc.c']
if GetDepend(['BSP_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_ONCHIP_RTC']):
src += ['drv_rtc.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)

261
bsp/nrf5x/libraries/drivers/drv_adc.c Normal file
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@ -0,0 +1,261 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-18 guohp1128 the first version
*/
#include "drv_adc.h"
#ifdef RT_USING_ADC
struct rt_adc_device nrf5x_adc_device;
drv_nrfx_saadc_result_t results;
nrf_saadc_value_t result_buff_cache[8];
static void nrf5x_saadc_event_hdr(nrfx_saadc_evt_t const * p_event)
{
uint8_t i,j;
if(p_event->type == NRFX_SAADC_EVT_DONE)
{
j = 0;
for(i = 0; i < 8; i++)
{
if(results.channels[i].channel_index == i)
{
results.result_buffer[i] = result_buff_cache[j];
j ++;
}
}
results.done = 1;
}
}
static uint32_t get_channels_mask(void)
{
uint8_t i;
uint32_t mask = 0;
for(i = 0; i < 8; i++)
{
if(results.channels[i].channel_index != 0xff)
{
mask |= (1 << results.channels[i].channel_index);
}
}
return mask;
}
static void set_channels(drv_nrfx_saadc_channel_t * channel)
{
uint8_t i;
if(channel -> mode == NRF_SAADC_MODE_SINGLE_ENDED)
{
results.channels[channel->channel_num] = (nrfx_saadc_channel_t)NRFX_SAADC_DEFAULT_CHANNEL_SE(channel -> pin_p + 1, channel -> channel_num);
}
else if(channel -> mode == NRF_SAADC_MODE_DIFFERENTIAL)
{
results.channels[channel->channel_num] = (nrfx_saadc_channel_t)NRFX_SAADC_DEFAULT_CHANNEL_DIFFERENTIAL(channel -> pin_p + 1, channel -> pin_n + 1, channel -> channel_num);
}
results.channel_count = 0;
for(i = 0; i < 8; i++)
{
if(results.channels[i].channel_index != 0xff)
{
results.channel_count ++;
}
}
}
/* channel: 0-7 */
static rt_err_t nrf5x_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
nrfx_err_t err_code = NRFX_SUCCESS;
uint8_t i,j;
if (enabled)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->parent.user_data != RT_NULL);
drv_nrfx_saadc_channel_t * drv_channel_config = NULL;
drv_channel_config = (drv_nrfx_saadc_channel_t *)device->parent.user_data;
set_channels(drv_channel_config);
nrfx_saadc_channel_t channels_cache[results.channel_count];
j = 0;
for(i = 0; i < 8; i++)
{
if(results.channels[i].channel_index != 0xff)
{
channels_cache[j] = results.channels[i];
j ++;
}
}
err_code = nrfx_saadc_channels_config(channels_cache,results.channel_count);
err_code = nrfx_saadc_simple_mode_set(get_channels_mask(),
NRF_SAADC_RESOLUTION_12BIT,
NRF_SAADC_OVERSAMPLE_DISABLED,
nrf5x_saadc_event_hdr);
err_code = nrfx_saadc_buffer_set(result_buff_cache, results.channel_count);
}
else
{
results.channels[channel].channel_index = 0xff;
results.channel_count = 0;
for(i = 0; i < 8; i++)
{
if(results.channels[i].channel_index != 0xff)
{
results.channel_count ++;
}
}
if(results.channel_count == 0)
{
nrfx_saadc_channel_t channels_cache[1];
err_code = nrfx_saadc_channels_config(channels_cache, 0);
return err_code;
}
else
{
nrfx_saadc_channel_t channels_cache[results.channel_count];
j = 0;
for(i = 0; i < 8; i++)
{
if(results.channels[i].channel_index != 0xff)
{
channels_cache[j] = results.channels[i];
j ++;
}
}
err_code = nrfx_saadc_channels_config(channels_cache,results.channel_count);
err_code = nrfx_saadc_simple_mode_set(get_channels_mask(),
NRF_SAADC_RESOLUTION_12BIT,
NRF_SAADC_OVERSAMPLE_DISABLED,
nrf5x_saadc_event_hdr);
err_code = nrfx_saadc_buffer_set(result_buff_cache, results.channel_count);
}
}
return err_code;
}
static rt_err_t nrf5x_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
nrfx_err_t err_code = NRFX_SUCCESS;
if (results.channels[channel].channel_index != 0xff)
{
results.done = 0;
err_code = nrfx_saadc_mode_trigger();
while(results.done == 0)
{
;
}
* value = results.result_buffer[channel];
results.done = 0;
}
return err_code;
}
static const struct rt_adc_ops nrf5x_adc_ops =
{
.enabled = nrf5x_adc_enabled,
.convert = nrf5x_get_adc_value,
};
int rt_hw_adc_init(void)
{
int result = RT_EOK;
uint8_t i;
char name_buf[6] = {'S', 'A', 'A', 'D', 'C', 0};
for(i = 0; i < 8; i++)
{
results.channels[i].channel_index = 0xff;
results.result_buffer[i] = 0;
results.channel_count = 0;
results.done = 0;
}
/* initializing SAADC interrupt priority */
if (nrfx_saadc_init(NRFX_SAADC_CONFIG_IRQ_PRIORITY) != NRFX_SUCCESS)
{
rt_kprintf("%s init failed", name_buf);
rt_kprintf("The driver is already initialized.");
result = -RT_ERROR;
}
else
{
/* register ADC device */
if (rt_hw_adc_register(&nrf5x_adc_device, name_buf, &nrf5x_adc_ops, nrf5x_adc_device.parent.user_data) == RT_EOK)
{
rt_kprintf("%s init success", name_buf);
}
else
{
rt_kprintf("%s register failed", name_buf);
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(rt_hw_adc_init);
/*test saadc*/
#include <drv_adc.h>
void saadc_sample(void)
{
drv_nrfx_saadc_channel_t channel_config;
rt_uint32_t result;
rt_adc_device_t adc_dev;
adc_dev = (rt_adc_device_t)rt_device_find("SAADC");
adc_dev->parent.user_data = &channel_config;
channel_config = (drv_nrfx_saadc_channel_t){.mode = 0, .pin_p = 1, .pin_n = 1, .channel_num = 0};
rt_adc_enable(adc_dev, channel_config.channel_num);
channel_config = (drv_nrfx_saadc_channel_t){.mode = 0, .pin_p = 2, .pin_n = 1, .channel_num = 1};
rt_adc_enable(adc_dev, channel_config.channel_num);
channel_config = (drv_nrfx_saadc_channel_t){.mode = 0, .pin_p = 7, .pin_n = 1, .channel_num = 5};
rt_adc_enable(adc_dev, channel_config.channel_num);
int count = 1;
while(count++)
{
result = rt_adc_read(adc_dev, 0);
rt_kprintf("saadc channel 0 value = %d, ",result);
result = rt_adc_read(adc_dev, 1);
rt_kprintf("saadc channel 1 value = %d, ",result);
result = rt_adc_read(adc_dev, 5);
rt_kprintf("saadc channel 5 value = %d",result);
rt_kprintf("\r\n");
rt_thread_mdelay(1000);
}
}
MSH_CMD_EXPORT(saadc_sample, saadc sample);
#endif /* RT_USING_ADC */

46
bsp/nrf5x/libraries/drivers/drv_adc.h Normal file
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@ -0,0 +1,46 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-18 guohp1128 the first version
*/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
#include <board.h>
#include "rtdevice.h"
#include <hal/nrf_saadc.h>
#include <drivers/include/nrfx_saadc.h>
/*
previous definition in application
set single-ended mode or differential mode.
selection ADC input pin, and config the number of Channel.
mode: 0 single-ended mode,1 differential mode
pin_p: 0-7
pin_n: 0-7,if single-ended mode, pin_n invalid
channel_num: 0-7
*/
typedef struct
{
nrf_saadc_mode_t mode; ///< SAADC mode. Single-ended or differential.
uint8_t pin_p; ///< Input positive pin selection.
uint8_t pin_n; ///< Input negative pin selection.
uint8_t channel_num; ///< Channel number.
} drv_nrfx_saadc_channel_t;
typedef struct
{
nrfx_saadc_channel_t channels[8];
uint8_t channel_count;
nrf_saadc_value_t result_buffer[8];
uint8_t done;
} drv_nrfx_saadc_result_t;
#endif /* __DRV_ADC_H__ */

120
bsp/nrf5x/libraries/drivers/drv_gpio.c
View File

@ -46,6 +46,24 @@ static const struct pin_index pins[] =
__NRF5X_PIN(29, 0, 29),
__NRF5X_PIN(30, 0, 30),
__NRF5X_PIN(31, 0, 31),
#ifdef SOC_NRF52840
__NRF5X_PIN(32, 1, 0 ),
__NRF5X_PIN(33, 1, 1 ),
__NRF5X_PIN(34, 1, 2 ),
__NRF5X_PIN(35, 1, 3 ),
__NRF5X_PIN(36, 1, 4 ),
__NRF5X_PIN(37, 1, 5 ),
__NRF5X_PIN(38, 1, 6 ),
__NRF5X_PIN(39, 1, 7 ),
__NRF5X_PIN(40, 1, 8 ),
__NRF5X_PIN(41, 1, 9 ),
__NRF5X_PIN(42, 1, 10),
__NRF5X_PIN(43, 1, 11),
__NRF5X_PIN(44, 1, 12),
__NRF5X_PIN(45, 1, 13),
__NRF5X_PIN(46, 1, 14),
__NRF5X_PIN(47, 1, 15),
#endif /* SOC_NRF52840 */
};
/* EVENTS_IN[n](n=0..7) and EVENTS_PORT */
@ -335,6 +353,7 @@ const static struct rt_pin_ops _nrf5x_pin_ops =
nrf5x_pin_attach_irq,
nrf5x_pin_dettach_irq,
nrf5x_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)
@ -356,4 +375,105 @@ int rt_hw_pin_init(void)
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
/* test GPIO write, read, input interrupt */
#define DK_BOARD_LED_1 13
#define DK_BOARD_LED_2 14
#define DK_BOARD_LED_3 15
#define DK_BOARD_LED_4 16
#define DK_BOARD_BUTTON_1 11
#define DK_BOARD_BUTTON_2 12
#define DK_BOARD_BUTTON_3 24
#define DK_BOARD_BUTTON_4 25
void button_1_callback(void *args)
{
static int flag1 = 0;
if(flag1 == 0)
{
flag1 = 1;
rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
}
else
{
flag1 = 0;
rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
}
}
void button_2_callback(void *args)
{
static int flag2 = 0;
if(flag2 == 0)
{
flag2 = 1;
rt_pin_write(DK_BOARD_LED_2, PIN_LOW);
}
else
{
flag2 = 0;
rt_pin_write(DK_BOARD_LED_2, PIN_HIGH);
}
}
void button_3_callback(void *args)
{
static int flag3 = 0;
if(flag3 == 0)
{
flag3 = 1;
rt_pin_write(DK_BOARD_LED_3, PIN_LOW);
}
else
{
flag3 = 0;
rt_pin_write(DK_BOARD_LED_3, PIN_HIGH);
}
}
void button_4_callback(void *args)
{
static int flag4 = 0;
if(flag4 == 0)
{
flag4 = 1;
rt_pin_write(DK_BOARD_LED_4, PIN_LOW);
}
else
{
flag4 = 0;
rt_pin_write(DK_BOARD_LED_4, PIN_HIGH);
}
}
void gpio_sample(void)
{
rt_err_t err_code;
rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
rt_pin_mode(DK_BOARD_LED_2, PIN_MODE_OUTPUT);
rt_pin_mode(DK_BOARD_LED_3, PIN_MODE_OUTPUT);
rt_pin_mode(DK_BOARD_LED_4, PIN_MODE_OUTPUT);
rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
rt_pin_write(DK_BOARD_LED_2, PIN_HIGH);
rt_pin_write(DK_BOARD_LED_3, PIN_HIGH);
rt_pin_write(DK_BOARD_LED_4, PIN_HIGH);
err_code = rt_pin_attach_irq(DK_BOARD_BUTTON_1, PIN_IRQ_MODE_FALLING,
button_1_callback, (void*) true); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
rt_pin_irq_enable(DK_BOARD_BUTTON_1, PIN_IRQ_ENABLE);
err_code = rt_pin_attach_irq(DK_BOARD_BUTTON_2, PIN_IRQ_MODE_FALLING,
button_2_callback, (void*) true); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
rt_pin_irq_enable(DK_BOARD_BUTTON_2, PIN_IRQ_ENABLE);
err_code = rt_pin_attach_irq(DK_BOARD_BUTTON_3, PIN_IRQ_MODE_FALLING,
button_3_callback, (void*) true); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
rt_pin_irq_enable(DK_BOARD_BUTTON_3, PIN_IRQ_ENABLE);
err_code = rt_pin_attach_irq(DK_BOARD_BUTTON_4, PIN_IRQ_MODE_FALLING,
button_4_callback, (void*) false); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
rt_pin_irq_enable(DK_BOARD_BUTTON_4, PIN_IRQ_ENABLE);
}
MSH_CMD_EXPORT(gpio_sample, gpio sample);
#endif /* RT_USING_PIN */

162
bsp/nrf5x/libraries/drivers/drv_rtc.c Normal file
View File

@ -0,0 +1,162 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-09-08 Chenyingchun first version
*/
#include "board.h"
#include <rtthread.h>
#include <rtdevice.h>
#include <nrfx_rtc.h>
#include <nrfx_clock.h>
#ifdef BSP_USING_ONCHIP_RTC
#define LOG_TAG "drv.rtc"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
/* 2018-01-30 14:44:50 = RTC_TIME_INIT(2018, 1, 30, 14, 44, 50) */
#define RTC_TIME_INIT(year, month, day, hour, minute, second) \
{.tm_year = year - 1900, .tm_mon = month - 1, .tm_mday = day, .tm_hour = hour, .tm_min = minute, .tm_sec = second}
#ifndef ONCHIP_RTC_TIME_DEFAULT
#define ONCHIP_RTC_TIME_DEFAULT RTC_TIME_INIT(2018, 1, 1, 0, 0 ,0)
#endif
#ifndef RTC_INSTANCE_ID
#define RTC_INSTANCE_ID (2)
#endif
#define TICK_FREQUENCE_HZ (RT_TICK_PER_SECOND) // RTC tick frequence, in HZ
static struct rt_device rtc;
static time_t init_time;
static uint32_t tick = 0;
static void rtc_callback(nrfx_rtc_int_type_t int_type)
{
static uint32_t count = 0;
if (int_type == NRFX_RTC_INT_TICK)
{
count++;
if((count % TICK_FREQUENCE_HZ) == 0)
{
tick++;
}
}
}
static rt_err_t rt_rtc_config(struct rt_device *dev)
{
#define SYSTICK_CLOCK_HZ (32768UL)
#define RTC_PRESCALER ((uint32_t) (NRFX_ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_FREQUENCE_HZ) - 1))
const nrfx_rtc_t rtc_instance = NRFX_RTC_INSTANCE(RTC_INSTANCE_ID);
nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC);
nrfx_clock_lfclk_start();
//Initialize RTC instance
nrfx_rtc_config_t config = NRFX_RTC_DEFAULT_CONFIG;
config.prescaler = RTC_PRESCALER;
nrfx_rtc_init(&rtc_instance, &config, rtc_callback);
nrfx_rtc_tick_enable(&rtc_instance, true);
//Power on RTC instance
nrfx_rtc_enable(&rtc_instance);
return RT_EOK;
}
static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
{
time_t *time;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
{
time = (time_t *) args;
*time = init_time + tick;
break;
}
case RT_DEVICE_CTRL_RTC_SET_TIME:
{
time = (time_t *) args;
init_time = *time - tick;
break;
}
}
return RT_EOK;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops rtc_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
rt_rtc_control
};
#endif
static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
{
struct tm time_new = ONCHIP_RTC_TIME_DEFAULT;
RT_ASSERT(device != RT_NULL);
init_time = mktime(&time_new);
if (rt_rtc_config(device) != RT_EOK)
{
return -RT_ERROR;
}
#ifdef RT_USING_DEVICE_OPS
device->ops = &rtc_ops;
#else
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_rtc_control;
#endif
device->type = RT_Device_Class_RTC;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->user_data = RT_NULL;
/* register a character device */
rt_device_register(device, name, flag);
return RT_EOK;
}
int rt_hw_rtc_init(void)
{
rt_err_t result;
result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
if (result != RT_EOK)
{
LOG_E("rtc register err code: %d", result);
return result;
}
LOG_D("rtc init success");
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif /* BSP_USING_ONCHIP_RTC */

89
bsp/nrf5x/libraries/drivers/drv_wdt.c Normal file
View File

@ -0,0 +1,89 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-08-18 ylz0923 first version
*/
#include <board.h>
#include <rtdevice.h>
#include <nrfx_wdt.h>
#ifdef RT_USING_WDT
struct nrf5x_wdt_obj
{
rt_watchdog_t watchdog;
nrfx_wdt_t wdt;
nrfx_wdt_channel_id ch;
rt_uint16_t is_start;
};
static struct nrf5x_wdt_obj nrf5x_wdt = {
.wdt = NRFX_WDT_INSTANCE(0),
};
static nrfx_wdt_config_t nrf5x_wdt_cfg = NRFX_WDT_DEFAULT_CONFIG;
static struct rt_watchdog_ops ops;
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
return RT_EOK;
}
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
switch (cmd)
{
/* feed the watchdog */
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
nrfx_wdt_feed(&nrf5x_wdt.wdt);
break;
/* set watchdog timeout */
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
nrf5x_wdt_cfg.reload_value = (rt_uint32_t)arg * 1000;
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
*((rt_uint32_t*)arg) = nrf5x_wdt_cfg.reload_value;
break;
case RT_DEVICE_CTRL_WDT_START:
if (nrf5x_wdt.is_start != 1)
{
nrfx_wdt_init(&nrf5x_wdt.wdt, &nrf5x_wdt_cfg, RT_NULL);
nrfx_wdt_channel_alloc(&nrf5x_wdt.wdt, &nrf5x_wdt.ch);
nrfx_wdt_enable(&nrf5x_wdt.wdt);
nrf5x_wdt.is_start = 1;
}
break;
default:
return -RT_ERROR;
}
return RT_EOK;
}
int rt_wdt_init(void)
{
nrf5x_wdt.is_start = 0;
ops.init = &wdt_init;
ops.control = &wdt_control;
nrf5x_wdt.watchdog.ops = &ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&nrf5x_wdt.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
return -RT_ERROR;
}
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_wdt_init);
static int wdt_sample(int argc, char *argv[])
{
rt_device_t wdt = rt_device_find("wdt");
rt_device_init(wdt);
rt_device_control(wdt, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, (void *)2);
rt_device_control(wdt, RT_DEVICE_CTRL_WDT_START, RT_NULL);
}
MSH_CMD_EXPORT(wdt_sample, wdt sample);
#endif /* RT_USING_WDT */

143
bsp/nrf5x/nrf52832/board/Kconfig
View File

@ -6,6 +6,16 @@ config SOC_NRF52832
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config NRFX_CLOCK_ENABLED
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_CLOCK_CONFIG_LF_SRC
int
default 1
config SOC_NORDIC
bool
@ -26,6 +36,20 @@ menu "On-chip Peripheral Drivers"
bool "Enable GPIO"
select RT_USING_PIN
default y
if BSP_USING_GPIO
config NRFX_GPIOTE_ENABLED
int
default 1
endif
config BSP_USING_SAADC
bool "Enable SAADC"
select RT_USING_ADC
default n
if BSP_USING_SAADC
config NRFX_SAADC_ENABLED
int
default 1
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
select RT_USING_PWM
@ -44,19 +68,19 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_PWM0_CH0
int "PWM0 channel 0 pin number set"
range 0 47
default 13
default 17
config BSP_USING_PWM0_CH1
int "PWM0 channel 1 pin number set"
range 0 47
default 14
default 18
config BSP_USING_PWM0_CH2
int "PWM0 channel 2 pin number set"
range 0 47
default 15
default 19
config BSP_USING_PWM0_CH3
int "PWM0 channel 3 pin number set"
range 0 47
default 16
default 20
endif
config BSP_USING_PWM1
bool "Enable PWM1 bus"
@ -131,47 +155,25 @@ menu "On-chip Peripheral Drivers"
default 16
endif
endif
menuconfig BSP_USING_SOFTDEVICE
bool "Enable NRF SOFTDEVICE"
select PKG_USING_NRF5X_SDK
select NRFX_CLOCK_ENABLED
default n
if BSP_USING_SOFTDEVICE
config NRFX_CLOCK_ENABLED
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_RTC_ENABLED
int
default 1
config NRFX_RTC1_ENABLED
int
default 1
config NRF_CLOCK_ENABLED
int
default 1
config NRF_SDH_BLE_ENABLED
int
default 1
config NRF_SDH_ENABLED
int
default 1
config NRF_SDH_SOC_ENABLED
int
default 1
endif
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config NRFX_UART_ENABLED
int
default 1
config BSP_USING_UART0
bool "Enable UART0"
default y
if BSP_USING_UART0
config NRFX_UART0_ENABLED
int
default 1
config BSP_UART0_RX_PIN
int "uart0 rx pin number"
range 0 31
@ -192,6 +194,9 @@ endif
default y
if BSP_USING_SPI
config NRFX_SPI_ENABLED
int
default 1
config BSP_USING_SPI0
bool "Enable SPI0 bus"
default y
@ -289,6 +294,74 @@ endif
range 0x1000 0x1000
default 0x1000
endmenu
config BSP_USING_WDT
bool "Enable WDT"
select RT_USING_WDT
default n
if BSP_USING_WDT
config NRFX_WDT_ENABLED
int
default 1
config NRFX_WDT0_ENABLED
int
default 1
config NRFX_WDT_CONFIG_NO_IRQ
int
default 1
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
config NRFX_CLOCK_ENABLED
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_RTC_ENABLED
int
default 1
config NRFX_RTC0_ENABLED
int
default 1
config NRFX_RTC1_ENABLED
int
default 1
config NRFX_RTC2_ENABLED
int
default 1
config RTC_INSTANCE_ID
int
default 2
config RTC_INSTANCE_ID
int "select RTC instance id, must be 0, 1, 2"
range 0 2
default 2
endif
endmenu
choice
prompt "BLE STACK"
default BLE_STACK_USING_NULL
help
Select the ble stack
config BLE_STACK_USING_NULL
bool "not use the ble stack"
config BSP_USING_SOFTDEVICE
select PKG_USING_NRF5X_SDK
bool "Nordic softdevice(perpheral)"
config BSP_USING_NIMBLE
select PKG_USING_NIMBLE
select PKG_NIMBLE_BSP_NRF52840
bool "use nimble stack(iot)"
endchoice
endmenu

53
bsp/nrf5x/nrf52832/board/board.c
View File

@ -14,25 +14,8 @@
#include "board.h"
#include "drv_uart.h"
#ifdef BSP_USING_SOFTDEVICE
#include <nrfx_rtc.h>
#include <nrfx_clock.h>
#include "app_error.h"
#include "nrf_drv_clock.h"
const nrfx_rtc_t rtc = NRFX_RTC_INSTANCE(1); /**< Declaring an instance of nrf_drv_rtc for RTC0. */
static void rtc_handler(nrfx_rtc_int_type_t int_type)
{
if (int_type == NRFX_RTC_INT_TICK)
{
rt_interrupt_enter();
rt_tick_increase();
rt_interrupt_leave();
}
}
#else
/**
* This is the timer interrupt service routine.
*
@ -47,36 +30,14 @@ void SysTick_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
static void clk_event_handler(nrfx_clock_evt_type_t event){}
void SysTick_Configuration(void)
{
#ifdef BSP_USING_SOFTDEVICE
nrf_drv_clock_init();
nrf_drv_clock_lfclk_request(NULL);
uint32_t err_code;
#define TICK_RATE_HZ RT_TICK_PER_SECOND
#define SYSTICK_CLOCK_HZ ( 32768UL )
#define NRF_RTC_REG NRF_RTC1
/* IRQn used by the selected RTC */
#define NRF_RTC_IRQn RTC1_IRQn
/* Constants required to manipulate the NVIC. */
#define NRF_RTC_PRESCALER ( (uint32_t) (NRFX_ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) )
nrfx_rtc_config_t config = NRFX_RTC_DEFAULT_CONFIG;
config.prescaler = NRF_RTC_PRESCALER;
err_code = nrfx_rtc_init(&rtc, &config, rtc_handler);
// APP_ERROR_CHECK(err_code);
nrfx_rtc_tick_enable(&rtc, true);
#define COMPARE_COUNTERTIME (3UL) /**< Get Compare event COMPARE_TIME seconds after the counter starts from 0. */
//Set compare channel to trigger interrupt after COMPARE_COUNTERTIME seconds
err_code = nrfx_rtc_cc_set(&rtc, 0, COMPARE_COUNTERTIME * 8, true);
// APP_ERROR_CHECK(err_code);
//Power on RTC instance
nrfx_rtc_enable(&rtc);
#else
nrfx_clock_init(clk_event_handler);
nrfx_clock_enable();
nrfx_clock_lfclk_start();
/* Set interrupt priority */
NVIC_SetPriority(SysTick_IRQn, 0xf);
@ -85,7 +46,7 @@ void SysTick_Configuration(void)
nrf_systick_val_clear();
nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
| NRF_SYSTICK_CSR_ENABLE);
#endif
}

8
bsp/nrf5x/nrf52832/board/sdk_config.h
View File

@ -1899,7 +1899,7 @@
// <e> NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
//==========================================================
#ifndef NRFX_GPIOTE_ENABLED
#define NRFX_GPIOTE_ENABLED 1
#define NRFX_GPIOTE_ENABLED 0
#endif
// <o> NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
@ -2903,7 +2903,7 @@
// <e> NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
//==========================================================
#ifndef NRFX_QSPI_ENABLED
#define NRFX_QSPI_ENABLED 1
#define NRFX_QSPI_ENABLED 0
#endif
// <o> NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255>
@ -4382,11 +4382,11 @@
// <e> NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
//==========================================================
#ifndef NRFX_UART_ENABLED
#define NRFX_UART_ENABLED 1
#define NRFX_UART_ENABLED 0
#endif
// <o> NRFX_UART0_ENABLED - Enable UART0 instance
#ifndef NRFX_UART0_ENABLED
#define NRFX_UART0_ENABLED 1
#define NRFX_UART0_ENABLED 0
#endif
// <o> NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control

144
bsp/nrf5x/nrf52840/board/Kconfig
View File

@ -6,13 +6,22 @@ config SOC_NRF52840
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config NRFX_CLOCK_ENABLED
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_CLOCK_CONFIG_LF_SRC
int
default 1
config SOC_NORDIC
bool
config SOC_NORDIC
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_JLINK_TO_USART
bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)"
@ -26,6 +35,9 @@ menu "Onboard Peripheral Drivers"
default n
if BSP_USING_QSPI_FLASH
config NRFX_QSPI_ENABLED
int
default 1
config BSP_QSPI_SCK_PIN
int "QSPI SCK pin number"
range 0 31
@ -61,6 +73,20 @@ menu "On-chip Peripheral Drivers"
bool "Enable GPIO"
select RT_USING_PIN
default y
if BSP_USING_GPIO
config NRFX_GPIOTE_ENABLED
int
default 1
endif
config BSP_USING_SAADC
bool "Enable SAADC"
select RT_USING_ADC
default n
if BSP_USING_SAADC
config NRFX_SAADC_ENABLED
int
default 1
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
select RT_USING_PWM
@ -166,47 +192,25 @@ menu "On-chip Peripheral Drivers"
default 16
endif
endif
menuconfig BSP_USING_SOFTDEVICE
bool "Enable NRF SOFTDEVICE"
select PKG_USING_NRF5X_SDK
select NRFX_CLOCK_ENABLED
default n
if BSP_USING_SOFTDEVICE
config NRFX_CLOCK_ENABLED
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_RTC_ENABLED
int
default 1
config NRFX_RTC1_ENABLED
int
default 1
config NRF_CLOCK_ENABLED
int
default 1
config NRF_SDH_BLE_ENABLED
int
default 1
config NRF_SDH_ENABLED
int
default 1
config NRF_SDH_SOC_ENABLED
int
default 1
endif
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config NRFX_UART_ENABLED
int
default 1
config BSP_USING_UART0
bool "Enable UART0"
default y
if BSP_USING_UART0
config NRFX_UART0_ENABLED
int
default 1
config BSP_UART0_RX_PIN
int "uart0 rx pin number"
range 0 31
@ -227,6 +231,9 @@ endif
default y
if BSP_USING_SPI
config NRFX_SPI_ENABLED
int
default 1
config BSP_USING_SPI0
bool "Enable SPI0 bus"
default y
@ -324,6 +331,77 @@ endif
range 0x1000 0x1000
default 0x1000
endmenu
endmenu
config BSP_USING_WDT
bool "Enable WDT"
select RT_USING_WDT
default n
if BSP_USING_WDT
config NRFX_WDT_ENABLED
int
default 1
config NRFX_WDT0_ENABLED
int
default 1
config NRFX_WDT_CONFIG_NO_IRQ
int
default 1
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
config NRFX_CLOCK_ENABLED
int
default 1
config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
int
default 7
config NRFX_RTC_ENABLED
int
default 1
config NRFX_RTC0_ENABLED
int
default 1
config NRFX_RTC1_ENABLED
int
default 1
config NRFX_RTC2_ENABLED
int
default 1
config RTC_INSTANCE_ID
int
default 2
config RTC_INSTANCE_ID
int "select RTC instance id, must be 0, 1, 2"
range 0 2
default 2
endif
endmenu
choice
prompt "BLE STACK"
default BLE_STACK_USING_NULL
help
Select the ble stack
config BLE_STACK_USING_NULL
bool "not use the ble stack"
config BSP_USING_SOFTDEVICE
select PKG_USING_NRF5X_SDK
bool "Nordic softdevice(perpheral)"
config BSP_USING_NIMBLE
select PKG_USING_NIMBLE
select PKG_NIMBLE_BSP_NRF52840
bool "use nimble stack(iot)"
endchoice
endmenu

53
bsp/nrf5x/nrf52840/board/board.c
View File

@ -14,25 +14,8 @@
#include "board.h"
#include "drv_uart.h"
#ifdef BSP_USING_SOFTDEVICE
#include <nrfx_rtc.h>
#include <nrfx_clock.h>
#include "app_error.h"
#include "nrf_drv_clock.h"
const nrfx_rtc_t rtc = NRFX_RTC_INSTANCE(1); /**< Declaring an instance of nrf_drv_rtc for RTC0. */
static void rtc_handler(nrfx_rtc_int_type_t int_type)
{
if (int_type == NRFX_RTC_INT_TICK)
{
rt_interrupt_enter();
rt_tick_increase();
rt_interrupt_leave();
}
}
#else
/**
* This is the timer interrupt service routine.
*
@ -47,36 +30,14 @@ void SysTick_Handler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
static void clk_event_handler(nrfx_clock_evt_type_t event){}
void SysTick_Configuration(void)
{
#ifdef BSP_USING_SOFTDEVICE
nrf_drv_clock_init();
nrf_drv_clock_lfclk_request(NULL);
uint32_t err_code;
#define TICK_RATE_HZ RT_TICK_PER_SECOND
#define SYSTICK_CLOCK_HZ ( 32768UL )
#define NRF_RTC_REG NRF_RTC1
/* IRQn used by the selected RTC */
#define NRF_RTC_IRQn RTC1_IRQn
/* Constants required to manipulate the NVIC. */
#define NRF_RTC_PRESCALER ( (uint32_t) (NRFX_ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) )
nrfx_rtc_config_t config = NRFX_RTC_DEFAULT_CONFIG;
config.prescaler = NRF_RTC_PRESCALER;
err_code = nrfx_rtc_init(&rtc, &config, rtc_handler);
// APP_ERROR_CHECK(err_code);
nrfx_rtc_tick_enable(&rtc, true);
#define COMPARE_COUNTERTIME (3UL) /**< Get Compare event COMPARE_TIME seconds after the counter starts from 0. */
//Set compare channel to trigger interrupt after COMPARE_COUNTERTIME seconds
err_code = nrfx_rtc_cc_set(&rtc, 0, COMPARE_COUNTERTIME * 8, true);
// APP_ERROR_CHECK(err_code);
//Power on RTC instance
nrfx_rtc_enable(&rtc);
#else
nrfx_clock_init(clk_event_handler);
nrfx_clock_enable();
nrfx_clock_lfclk_start();
/* Set interrupt priority */
NVIC_SetPriority(SysTick_IRQn, 0xf);
@ -85,7 +46,7 @@ void SysTick_Configuration(void)
nrf_systick_val_clear();
nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
| NRF_SYSTICK_CSR_ENABLE);
#endif
}

8
bsp/nrf5x/nrf52840/board/sdk_config.h
View File

@ -1899,7 +1899,7 @@
// <e> NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
//==========================================================
#ifndef NRFX_GPIOTE_ENABLED
#define NRFX_GPIOTE_ENABLED 1
#define NRFX_GPIOTE_ENABLED 0
#endif
// <o> NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
@ -2903,7 +2903,7 @@
// <e> NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
//==========================================================
#ifndef NRFX_QSPI_ENABLED
#define NRFX_QSPI_ENABLED 1
#define NRFX_QSPI_ENABLED 0
#endif
// <o> NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255>
@ -4382,11 +4382,11 @@
// <e> NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
//==========================================================
#ifndef NRFX_UART_ENABLED
#define NRFX_UART_ENABLED 1
#define NRFX_UART_ENABLED 0
#endif
// <o> NRFX_UART0_ENABLED - Enable UART0 instance
#ifndef NRFX_UART0_ENABLED
#define NRFX_UART0_ENABLED 1
#define NRFX_UART0_ENABLED 0
#endif
// <o> NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control

11
bsp/nuclei/README.md
View File

@ -1,16 +1,21 @@
# Nuclei RISC-V Processor Support Package
This directory provided support for [Nuclei RISC-V Processor](https://nucleisys.com/) based board, currently
we mainly provided the following support package.
This directory provided support for [Nuclei RISC-V Processor](https://nucleisys.com/) based board,
currently we mainly provided the following board support packages.
| **BSP** | **Development Board Name** |
| :----------------------------------- | :-------------------------------------------------------------------------------------------------------------------------- |
| [gd32vf103_rvstar](gd32vf103_rvstar) | [Nuclei RV-STAR Arduino Compatible Development Board](https://www.riscv-mcu.com/quickstart-quickstart-index-u-RV_STAR.html) |
| [hbird_eval](hbird_eval) | [Nuclei HummingBird FPGA Evaluation Development Board](https://nucleisys.com/developboard.php) |
**If you want to learn more about Nuclei Processors, please click the following links:**
* [Professional RISC-V IPs](https://nucleisys.com/product.php)
* [Nuclei Open Source Software Organization in Github](https://github.com/Nuclei-Software/)
* [Nuclei Open Source Software Organization in Gitee](https://gitee.com/Nuclei-Software/)
* [RISC-V MCU Open Source Software Organization in Github](https://github.com/riscv-mcu/)
* [RISC-V MCU Open Source Software Organization in Gitee](https://gitee.com/riscv-mcu/)
* [Professional Nuclei Processor Development Boards](https://nucleisys.com/developboard.php)
* [Comprehensive Documents and Development Tools](https://nucleisys.com/download.php)
* [Active RISC-V IP and MCU Community](https://www.rvmcu.com/)
* [Professional University Program](https://nucleisys.com/campus.php)
* [Professional University Program](https://nucleisys.com/campus.php)

228
bsp/nuvoton_m487/.config → bsp/nuclei/hbird_eval/.config
View File

@ -19,11 +19,14 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_IDLE_THREAD_STACK_SIZE=396
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_COLOR is not set
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
@ -41,13 +44,13 @@ CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
# CONFIG_RT_USING_MESSAGEQUEUE is not set
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
# CONFIG_RT_USING_MEMPOOL is not set
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
@ -64,8 +67,9 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_RISCV=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
@ -92,12 +96,12 @@ CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=2048
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
@ -107,40 +111,23 @@ CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=32
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=64
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
@ -151,32 +138,17 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
# CONFIG_RT_DEBUG_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using Hardware Crypto drivers
#
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
#
# Using WiFi
#
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
@ -209,74 +181,16 @@ CONFIG_RT_USING_POSIX=y
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
CONFIG_NETDEV_USING_PING=y
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP210 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=19
CONFIG_RT_LWIP_PBUF_NUM=0
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=19
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=2920
CONFIG_RT_LWIP_TCP_WND=2920
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=768
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_LWIP_DEBUG is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
@ -301,10 +215,14 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
@ -326,6 +244,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
@ -337,12 +256,28 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
#
# security packages
@ -350,6 +285,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
#
# language packages
@ -364,6 +300,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
@ -376,6 +314,13 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
@ -393,6 +338,11 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
#
# peripheral libraries and drivers
@ -400,7 +350,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
@ -409,15 +359,43 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
CONFIG_PKG_USING_NUCLEI_SDK=y
#
# !!!Nuclei SDK only works with Nuclei RISC-V Processor IP!!!
#
CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk"
# CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set
CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y
CONFIG_PKG_NUCLEI_SDK_VER="latest"
#
# miscellaneous packages
@ -428,12 +406,15 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
@ -445,3 +426,30 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_HUMMINGBIRD=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_UART_CONSOLE=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
#
# Board extended module Drivers
#

16
bsp/nuvoton_m05x/Kconfig → bsp/nuclei/hbird_eval/Kconfig
View File

@ -8,23 +8,21 @@ config BSP_DIR
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"
config SOC_M051
bool
config SOC_HUMMINGBIRD
bool
select ARCH_RISCV
select PKG_USING_NUCLEI_SDK
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config RT_USING_UART0
bool "Using Uart0"
select RT_USING_SERIAL
default y

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