248 lines
6.6 KiB
Makefile
248 lines
6.6 KiB
Makefile
#***************************************************************************************
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# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
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# Copyright (c) 2020-2021 Peng Cheng Laboratory
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#
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# DiffTest is licensed under Mulan PSL v2.
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# You can use this software according to the terms and conditions of the Mulan PSL v2.
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# You may obtain a copy of Mulan PSL v2 at:
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# http://license.coscl.org.cn/MulanPSL2
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#
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# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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#
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# See the Mulan PSL v2 for more details.
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#***************************************************************************************
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NOOP_HOME ?= $(abspath .)
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export NOOP_HOME
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SIM_TOP ?= SimTop
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DESIGN_DIR ?= $(NOOP_HOME)
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NUM_CORES ?= 1
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MFC ?= 1
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BUILD_DIR = $(DESIGN_DIR)/build
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RTL_DIR = $(BUILD_DIR)/rtl
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RTL_SUFFIX ?= sv
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SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX)
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# generate difftest files for non-chisel design.
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.DEFAULT_GOAL := difftest_verilog
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ifeq ($(MFC), 1)
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CHISEL_VERSION = chisel
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MILL_ARGS += --target systemverilog --split-verilog
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else
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CHISEL_VERSION = chisel3
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endif
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ifneq ($(PROFILE), )
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MILL_ARGS += --profile $(abspath $(PROFILE))
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endif
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ifneq ($(NUM_CORES), )
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MILL_ARGS += --num-cores $(NUM_CORES)
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endif
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ifneq ($(CONFIG), )
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MILL_ARGS += --difftest-config $(CONFIG)
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endif
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difftest_verilog:
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mill -i difftest[$(CHISEL_VERSION)].test.runMain difftest.DifftestMain --target-dir $(RTL_DIR) $(MILL_ARGS)
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TIMELOG = $(BUILD_DIR)/time.log
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TIME_CMD = time -avp -o $(TIMELOG)
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# remote machine with more cores to speedup c++ build
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REMOTE ?= localhost
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# simulation
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SIM_CONFIG_DIR = $(abspath ./config)
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SIM_CSRC_DIR = $(abspath ./src/test/csrc/common)
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SIM_CXXFILES = $(shell find $(SIM_CSRC_DIR) -name "*.cpp")
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SIM_CXXFLAGS = -I$(SIM_CSRC_DIR) -I$(SIM_CONFIG_DIR)
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SIM_CXXFLAGS += -DNOOP_HOME=\\\"$(NOOP_HOME)\\\"
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# generated-src
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GEN_CSRC_DIR = $(BUILD_DIR)/generated-src
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SIM_CXXFILES += $(shell find $(GEN_CSRC_DIR) -name "*.cpp" 2> /dev/null)
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SIM_CXXFLAGS += -I$(GEN_CSRC_DIR)
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PLUGIN_CSRC_DIR = $(abspath ./src/test/csrc/plugin)
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PLUGIN_INC_DIR = $(abspath $(PLUGIN_CSRC_DIR)/include)
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SIM_CXXFLAGS += -I$(PLUGIN_INC_DIR)
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GEN_VSRC_DIR = $(BUILD_DIR)/generated-src
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VSRC_DIR = $(abspath ./src/test/vsrc/common)
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SIM_VSRC = $(shell find $(VSRC_DIR) -name "*.v" -or -name "*.sv")
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# DiffTest support
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DIFFTEST_CSRC_DIR = $(abspath ./src/test/csrc/difftest)
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DIFFTEST_CXXFILES = $(shell find $(DIFFTEST_CSRC_DIR) -name "*.cpp")
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ifeq ($(NO_DIFF), 1)
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SIM_CXXFLAGS += -DCONFIG_NO_DIFFTEST
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else
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SIM_CXXFILES += $(DIFFTEST_CXXFILES)
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SIM_CXXFLAGS += -I$(DIFFTEST_CSRC_DIR)
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ifeq ($(DIFFTEST_PERFCNT), 1)
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SIM_CXXFLAGS += -DCONFIG_DIFFTEST_PERFCNT
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endif
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endif
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# ChiselDB
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WITH_CHISELDB ?= 1
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ifeq ($(WITH_CHISELDB), 1)
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SIM_CXXFILES += $(BUILD_DIR)/chisel_db.cpp
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SIM_CXXFLAGS += -I$(BUILD_DIR) -DENABLE_CHISEL_DB
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SIM_LDFLAGS += -lsqlite3
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endif
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# ConstantIn
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WITH_CONSTANTIN ?= 1
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ifeq ($(WITH_CONSTANTIN), 1)
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SIM_CXXFILES += $(BUILD_DIR)/constantin.cpp
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SIM_CXXFLAGS += -I$(BUILD_DIR) -DENABLE_CONSTANTIN
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endif
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ifeq ($(WITH_IPC), 1)
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SIM_CXXFLAGS += -I$(BUILD_DIR) -DENABLE_IPC
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endif
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# REF SELECTION
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ifneq ($(REF),)
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ifneq ($(wildcard $(REF)),)
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SIM_CXXFLAGS += -DREF_PROXY=LinkedProxy -DLINKED_REFPROXY_LIB=\\\"$(REF)\\\"
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SIM_LDFLAGS += $(REF)
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else
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SIM_CXXFLAGS += -DREF_PROXY=$(REF)Proxy
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REF_HOME_VAR = $(shell echo $(REF)_HOME | tr a-z A-Z)
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ifneq ($(origin $(REF_HOME_VAR)), undefined)
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SIM_CXXFLAGS += -DREF_HOME=\\\"$(shell echo $$$(REF_HOME_VAR))\\\"
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endif
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endif
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endif
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# co-simulation with DRAMsim3
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ifeq ($(WITH_DRAMSIM3),1)
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ifndef DRAMSIM3_HOME
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$(error DRAMSIM3_HOME is not set)
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endif
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SIM_CXXFLAGS += -I$(DRAMSIM3_HOME)/src
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SIM_CXXFLAGS += -DWITH_DRAMSIM3 -DDRAMSIM3_CONFIG=\\\"$(DRAMSIM3_HOME)/configs/XiangShan.ini\\\" -DDRAMSIM3_OUTDIR=\\\"$(BUILD_DIR)\\\"
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SIM_LDFLAGS += $(DRAMSIM3_HOME)/build/libdramsim3.a
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endif
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# out ipc info on temporary txt file, mainly applied to support qemu multi-core sampled data
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ifneq ($(OUTPUT_CPI_TO_FILE),)
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SIM_CXXFLAGS += -DOUTPUT_CPI_TO_FILE=$(OUTPUT_CPI_TO_FILE)
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endif
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ifeq ($(PMEM_CHECK),1)
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SIM_CXXFLAGS += -DPMEM_CHECK
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endif
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ifeq ($(RELEASE),1)
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SIM_CXXFLAGS += -DBASIC_DIFFTEST_ONLY
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endif
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# VGA support
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ifeq ($(SHOW_SCREEN),1)
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SIM_CXXFLAGS += $(shell sdl2-config --cflags) -DSHOW_SCREEN
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SIM_LDFLAGS += -lSDL2
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endif
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# GZ image support
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IMAGE_GZ_COMPRESS ?= 1
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ifeq ($(IMAGE_GZ_COMPRESS),0)
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SIM_CXXFLAGS += -DNO_GZ_COMPRESSION
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else
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SIM_LDFLAGS += -lz
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endif
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# ZSTD image support
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ifneq ($(NO_ZSTD_COMPRESSION),)
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SIM_CXXFLAGS += -DNO_ZSTD_COMPRESSION
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else
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SIM_LDFLAGS += -lzstd
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endif
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# spike-dasm plugin
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WITH_SPIKE_DASM ?= 1
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ifeq ($(WITH_SPIKE_DASM),1)
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SIM_CXXFLAGS += -I$(abspath $(PLUGIN_CSRC_DIR)/spikedasm)
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SIM_CXXFILES += $(shell find $(PLUGIN_CSRC_DIR)/spikedasm -name "*.cpp")
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endif
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# runahead support
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ifeq ($(WITH_RUNAHEAD),1)
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SIM_CXXFLAGS += -I$(abspath $(PLUGIN_CSRC_DIR)/runahead)
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SIM_CXXFILES += $(shell find $(PLUGIN_CSRC_DIR)/runahead -name "*.cpp")
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endif
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# Check if XFUZZ is set
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ifeq ($(XFUZZ), 1)
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XFUZZ_HOME_VAR = XFUZZ_HOME
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ifeq ($(origin $(XFUZZ_HOME_VAR)), undefined)
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$(error $(XFUZZ_HOME_VAR) is not set)
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endif
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FUZZER_LIB = $(shell echo $$$(XFUZZ_HOME_VAR))/target/release/libfuzzer.a
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SIM_LDFLAGS += -lrt -lpthread
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endif
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# Link fuzzer libraries
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ifneq ($(FUZZER_LIB), )
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SIM_CXXFLAGS += -DFUZZER_LIB
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SIM_LDFLAGS += $(abspath $(FUZZER_LIB))
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FUZZING = 1
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endif
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# Fuzzer support
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ifeq ($(FUZZING),1)
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SIM_CXXFLAGS += -DFUZZING
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endif
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# FIRRTL Coverage support
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ifneq ($(FIRRTL_COVER),)
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SIM_CXXFLAGS += -DFIRRTL_COVER
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endif
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# LLVM Sanitizer Coverage support
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ifneq ($(LLVM_COVER),)
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SIM_CXXFLAGS += -DLLVM_COVER
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SIM_LDFLAGS += -fsanitize-coverage=trace-pc-guard -fsanitize-coverage=pc-table
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endif
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ifeq ($(IOTRACE_ZSTD),1)
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SIM_CXXFLAGS += -DCONFIG_IOTRACE_ZSTD
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endif
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# Do not allow compiler warnings
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ifeq ($(CXX_NO_WARNING),1)
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SIM_CXXFLAGS += -Werror
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endif
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include verilator.mk
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include vcs.mk
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include palladium.mk
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include libso.mk
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clean: vcs-clean pldm-clean
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rm -rf $(BUILD_DIR)
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format: scala-format clang-format
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scala-format:
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mill -i mill.scalalib.scalafmt.ScalafmtModule/reformatAll __.sources
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CLANG_FORMAT_VER = 18.1.4
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clang-format:
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ifeq ($(shell clang-format --version 2> /dev/null| cut -f3 -d' ' | tr '.' '_'), $(shell echo $(CLANG_FORMAT_VER) | tr '.' '_'))
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clang-format -i $(shell find ./src/test/csrc -name "*.cpp" -or -name "*.h")
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else
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@echo "Required clang-format Version: $(CLANG_FORMAT_VER)"
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@echo "Your Version: $(shell clang-format --version)"
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@echo "Please run \"pip install --user clang-format==$(CLANG_FORMAT_VER)\", then set PATH manually"
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endif
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.PHONY: sim-verilog emu difftest_verilog clean format scala-format clang-format
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