Update the scalafmt configuration (#275)

.scalafmt.conf

@@ -34,6 +34,7 @@ rewrite.rules = [
 rewrite.redundantBraces.methodBodies = false
 rewrite.redundantBraces.stringInterpolation = false
 rewrite.imports.sort = scalastyle
+rewrite.trailingCommas.style = multiple
 
 rewriteTokens = {
   "⇒": "=>"

src/main/scala/Bundles.scala

@@ -84,7 +84,7 @@ class InstrCommit(val numPhyRegs: Int = 32) extends DifftestBaseBundle with HasV
 
   def setSpecial(
     isDelayedWb: Bool = false.B,
-    isExit: Bool = false.B
+    isExit: Bool = false.B,
   ): Unit = {
     special := Cat(isExit, isDelayedWb)
   }
@@ -155,7 +155,7 @@ class ArchIntRegState extends DifftestBaseBundle {
   def toSeq: Seq[UInt] = value
   def names: Seq[String] = Seq(
     "$0", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2",
-    "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
+    "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
   )
 
   def ===(that: ArchIntRegState): Bool = {
@@ -169,7 +169,7 @@ class ArchIntRegState extends DifftestBaseBundle {
 class ArchFpRegState extends ArchIntRegState {
   override def names: Seq[String] = Seq(
     "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
-    "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+    "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",
   )
 }
 

src/main/scala/DPIC.scala

@@ -87,7 +87,7 @@ class DPIC[T <: DifftestBundle](gen: T, config: GatewayConfig)
       ((_: DifftestBundle) => config.hasDutZone, Seq("dut_zone")),
       ((_: DifftestBundle) => config.isBatch, Seq("dut_index")),
       ((x: DifftestBundle) => x.isIndexed, Seq("io_index")),
-      ((x: DifftestBundle) => x.isFlatten, Seq("io_address"))
+      ((x: DifftestBundle) => x.isFlatten, Seq("io_address")),
     )
     val rhs = dpicFuncArgs.map(_.map(_._1).filterNot(s => filters.exists(f => f._1(gen) && f._2.contains(s))))
     val lhs = rhs

src/main/scala/Difftest.scala

@@ -266,7 +266,7 @@ object DifftestModule {
     gen: T,
     style: String = "dpic",
     dontCare: Boolean = false,
-    delay: Int = 0
+    delay: Int = 0,
   ): T = {
     val difftest: T = Wire(gen)
     if (enabled) {

src/main/scala/Gateway.scala

@@ -34,7 +34,7 @@ case class GatewayConfig(
   diffStateSelect: Boolean = false,
   isBatch: Boolean = false,
   batchSize: Int = 32,
-  isNonBlock: Boolean = false
+  isNonBlock: Boolean = false,
 ) {
   if (squashReplay) require(isSquash)
   def hasDutZone: Boolean = diffStateSelect
@@ -72,7 +72,7 @@ case class GatewayResult(
   cppMacros: Seq[String] = Seq(),
   vMacros: Seq[String] = Seq(),
   instances: Seq[(DifftestBundle, String)] = Seq(),
-  step: Option[UInt] = None
+  step: Option[UInt] = None,
 )
 
 object Gateway {
@@ -107,14 +107,14 @@ object Gateway {
         cppMacros = config.cppMacros,
         vMacros = config.vMacros,
         instances = endpoint.instances,
-        step = Some(endpoint.step)
+        step = Some(endpoint.step),
       )
     } else {
       GatewaySink.collect(config)
       GatewayResult(
         cppMacros = config.cppMacros,
         vMacros = config.vMacros,
-        step = Some(1.U)
+        step = Some(1.U),
       )
     }
   }

src/main/scala/Squash.scala

@@ -213,6 +213,6 @@ class SquashControl(config: GatewayConfig) extends ExtModule with HasExtModuleIn
        |
        |
        |endmodule;
-       |""".stripMargin
+       |""".stripMargin,
   )
 }

src/main/scala/common/Flash.scala

@@ -106,7 +106,7 @@ class FlashHelper extends ExtModule with HasExtModuleInline {
       |`endif // SYNTHESIS
       |
       |endmodule
-     """.stripMargin
+     """.stripMargin,
   )
 }
 

src/main/scala/common/Mem.scala

@@ -170,7 +170,7 @@ class MemRHelper extends ExtModule with HasExtModuleInline with HasReadPort with
        |    $r_func
        |  end
        |endmodule
-     """.stripMargin
+     """.stripMargin,
   )
 }
 
@@ -193,7 +193,7 @@ class MemWHelper extends ExtModule with HasExtModuleInline with HasWritePort wit
        |   $w_func
        |  end
        |endmodule
-     """.stripMargin
+     """.stripMargin,
   )
 }
 
@@ -223,7 +223,7 @@ class MemRWHelper extends ExtModule with HasExtModuleInline with HasReadPort wit
        |    end
        |  end
        |endmodule
-     """.stripMargin
+     """.stripMargin,
   )
 }
 
@@ -277,11 +277,11 @@ class DifftestMem1P(size: BigInt, lanes: Int, bits: Int) extends DifftestMem(siz
       enable = write.valid,
       index = write.index * n_helper.U + i.U,
       data = write.data(i),
-      mask = write.mask(i)
+      mask = write.mask(i),
     )
     h.read(
       enable = read.valid,
-      index = read.index * n_helper.U + i.U
+      index = read.index * n_helper.U + i.U,
     )
   }
 }
@@ -292,7 +292,7 @@ class DifftestMem2P(size: BigInt, lanes: Int, bits: Int) extends DifftestMem(siz
     h.clock := clock
     h.read(
       enable = !reset.asBool && read.valid,
-      index = read.index * n_helper.U + i.U
+      index = read.index * n_helper.U + i.U,
     )
   }
 
@@ -303,7 +303,7 @@ class DifftestMem2P(size: BigInt, lanes: Int, bits: Int) extends DifftestMem(siz
       enable = !reset.asBool && write.valid,
       index = write.index * n_helper.U + i.U,
       data = write.data(i),
-      mask = write.mask(i)
+      mask = write.mask(i),
     )
   }
 }
@@ -341,7 +341,7 @@ class DifftestMemInitializer extends ExtModule with HasExtModuleInline {
       |end
       |`endif
       |endmodule
-      |""".stripMargin
+      |""".stripMargin,
   )
 }
 
@@ -375,7 +375,7 @@ object DifftestMem {
     lanes: Int,
     bits: Int,
     synthesizable: Boolean = false,
-    singlePort: Boolean = true
+    singlePort: Boolean = true,
   ): DifftestMem = {
     val mod = (synthesizable, singlePort) match {
       case (true, _)      => Module(new SynthesizableDifftestMem(size, lanes, bits))

src/main/scala/common/SDCard.scala

@@ -56,7 +56,7 @@ class SDCardHelper extends ExtModule with HasExtModuleInline {
        |`endif // SYNTHESIS
        |
        |endmodule
-     """.stripMargin
+     """.stripMargin,
   )
 }