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difftest
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difftest/vcs.mk

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Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project.
2021-06-04 09:06:35 +08:00
#***************************************************************************************
Update License comments (#134)
2023-09-06 16:40:04 +08:00
# Copyright (c) 2020-2023 Institute of Computing Technology, Chinese Academy of Sciences
misc: update PCL information
2021-07-27 17:05:42 +08:00
# Copyright (c) 2020-2021 Peng Cheng Laboratory
Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project.
2021-06-04 09:06:35 +08:00
#
Update License comments (#134)
2023-09-06 16:40:04 +08:00
# DiffTest is licensed under Mulan PSL v2.
Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project.
2021-06-04 09:06:35 +08:00
# You can use this software according to the terms and conditions of the Mulan PSL v2.
# You may obtain a copy of Mulan PSL v2 at:
# http://license.coscl.org.cn/MulanPSL2
#
# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
#
# See the Mulan PSL v2 for more details.
#***************************************************************************************
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
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VCS = vcs
VCS_TOP = tb_top
VCS_TARGET = $(abspath $(BUILD_DIR)/simv)
VCS_BUILD_DIR = $(abspath $(BUILD_DIR)/simv-compile)
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_CSRC_DIR = $(abspath ./src/test/csrc/vcs)
VCS_CONFIG_DIR = $(abspath ./config)
VCS_CXXFILES = $(SIM_CXXFILES) $(shell find $(VCS_CSRC_DIR) -name "*.cpp")
VCS_CXXFLAGS = $(SIM_CXXFLAGS) -I$(VCS_CSRC_DIR) -DNUM_CORES=$(NUM_CORES)
VCS_LDFLAGS = $(SIM_LDFLAGS) -lpthread -ldl
# DiffTest support
ifneq ($(NO_DIFF), 1)
VCS_FLAGS += +define+DIFFTEST
endif
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
difftest: add DIFFTEST macro This commit adds DIFFTEST macro to wrap difftest modules. Makefiles for verilator and vcs are updated as well.
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ifeq ($(RELEASE),1)
VCS_FLAGS += +define+SNPS_FAST_SIM_FFV +define+USE_RF_DEBUG
endif
vcs: could disable fsdb dump at compile stage usage: make simv CONSIDER_FSDB=0 Note: 1. $CONSIDER_FSDB is 1 at default. 2. Verdi is needed if wanna dump fsdb.
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# if fsdb is considered
vcs: set CONSIDER_FSDB default to none
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# CONSIDER_FSDB ?= 0
vcs: could disable fsdb dump at compile stage usage: make simv CONSIDER_FSDB=0 Note: 1. $CONSIDER_FSDB is 1 at default. 2. Verdi is needed if wanna dump fsdb.
2022-05-27 11:39:18 +08:00
ifeq ($(CONSIDER_FSDB),1)
EXTRA = +define+CONSIDER_FSDB
# if VERDI_HOME is not set automatically after 'module load', please set manually.
ifndef VERDI_HOME
$(error VERDI_HOME is not set. Try whereis verdi, abandon /bin/verdi and set VERID_HOME manually)
else
NOVAS_HOME = $(VERDI_HOME)
NOVAS = $(NOVAS_HOME)/share/PLI/VCS/LINUX64
EXTRA += -P $(NOVAS)/novas.tab $(NOVAS)/pli.a
endif
endif
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
ifeq ($(VCS),verilator)
VCS_FLAGS += --exe --cc --main --top-module $(VCS_TOP) -Wno-WIDTH
VCS_FLAGS += --instr-count-dpi 1 --timing +define+VERILATOR_5
VCS_FLAGS += -Mdir $(VCS_BUILD_DIR) --compiler gcc
VCS_CXXFLAGS += -std=c++20
else
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
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VCS_FLAGS += -full64 +v2k -timescale=1ns/1ns -sverilog -debug_access+all +lint=TFIPC-L
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_FLAGS += -Mdir=$(VCS_BUILD_DIR) -j200
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
# randomize all undefined signals (instead of using X)
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
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VCS_FLAGS += +vcs+initreg+random +define+VCS
VCS_CXXFLAGS += -std=c++11 -static
endif
VCS_FLAGS += -o $(VCS_TARGET)
vcs: fix incorrect random initialization (X) (#81) Set RANDOMIZE_DELAY to 0 will cause some random initialized reg be initialized to X. RANDOMIZE_DELAY should satisfy: * round(RANDOMIZE_DELAY) > 0 * RANDOMIZE_DELAY < reset delay See https://github.com/chipsalliance/firrtl/pull/835
2022-06-04 16:47:05 +08:00
VCS_FLAGS += +define+RANDOMIZE_GARBAGE_ASSIGN
VCS_FLAGS += +define+RANDOMIZE_INVALID_ASSIGN
VCS_FLAGS += +define+RANDOMIZE_MEM_INIT
VCS_FLAGS += +define+RANDOMIZE_REG_INIT
# manually set RANDOMIZE_DELAY to avoid VCS from incorrect random initialize
# NOTE: RANDOMIZE_DELAY must NOT be rounded to 0
VCS_FLAGS += +define+RANDOMIZE_DELAY=1
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
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# SRAM lib defines
difftest: add DIFFTEST macro This commit adds DIFFTEST macro to wrap difftest modules. Makefiles for verilator and vcs are updated as well.
2022-03-24 18:38:34 +08:00
VCS_FLAGS += +define+UNIT_DELAY +define+no_warning
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
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# C++ flags
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
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VCS_FLAGS += -CFLAGS "$(VCS_CXXFLAGS)" -LDFLAGS "$(VCS_LDFLAGS)"
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
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# search build for other missing verilog files
misc: expect rtl to be created at BUILD_DIR/rtl (#231)
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VCS_FLAGS += -y $(RTL_DIR) +libext+.v
vcs: enrich param dump-wave=[vpd,fsdb]
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# enable fsdb dump
vcs: could disable fsdb dump at compile stage usage: make simv CONSIDER_FSDB=0 Note: 1. $CONSIDER_FSDB is 1 at default. 2. Verdi is needed if wanna dump fsdb.
2022-05-27 11:39:18 +08:00
VCS_FLAGS += $(EXTRA)
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_VSRC_DIR = $(abspath ./src/test/vsrc/vcs)
VCS_VFILES = $(SIM_VSRC) $(shell find $(VCS_VSRC_DIR) -name "*.v")
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
$(VCS_TARGET): $(SIM_TOP_V) $(VCS_CXXFILES) $(VCS_VFILES)
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
$(VCS) $(VCS_FLAGS) $(SIM_TOP_V) $(VCS_CXXFILES) $(VCS_VFILES)
ifeq ($(VCS),verilator)
vcs: build the files sliently (#200)
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$(MAKE) -s -C $(VCS_BUILD_DIR) -f V$(VCS_TOP).mk CC=gcc-10 CXX=g++-10 LINK=g++-10
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
endif
simv: $(VCS_TARGET)
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
vcs-clean:
rm -rf simv csrc DVEfiles simv.daidir stack.info.* ucli.key $(VCS_BUILD_DIR)